Digitally Programmable Floating Impedance Converter using CMOS-DVCC

Transcription

1 nternational Journal of oputer Applications ( ) olue 66 o.7, March 3 Digitally Prograable Floating pedance onverter using MOSD Ahed M. ahhas Departent of Electrical Engineering, Faculty of Engineering and slaic Architecture, U Al Qura University, Makkah, Saudi Arabia ABSTRAT A novel digitally prograable floating ipedance converter circuit is realized using two MOS digitally prograable differential voltage current conveyors and three grounded passive eleents. The realized ipedance converter can provide digitally prograable floating ipedances like ideal floating resistor, capacitor, inductor and frequency dependent negative resistor through appropriate selection of three grounded passive eleents without any coponent atching constraint. The realized digitally prograable floating ipedance converter is designed and verified using PSPE and the results thus obtained justify the theory. Keywords urrent conveyors, D, ipedance converter.. TRODUTO For over last two decades the current conveyors have been doinating in the area of analog signal processing due to their functional versatility in addition to higher signal bandwidth and greater linearity. As a result vast variety of linear and nonlinear analog signal processing applications are reported in technical literature [34]. Recently, the introduction of digital control to the current conveyor () has eased the on chip control of continuous tie systes with high resolution capability and reconfigurability [56]. Such reconfigurable odules are suitable for realizing the field prograable analog array [4], [3537]. n analog signal processing applications the coponent siulators play an iportant role and several coponent siulators are reported in technical literature eploying current conveyors as well [734]. However, any of the use a coplex circuitry and coponent atching constraints. The coponent atching constraints increase the syste paraeter sensitivity to the unacceptable level [34]. n this paper a novel digitally prograable floating ipedance converter (DPF) is presented which uses two digitally prograable differential voltage current conveyors (DPD) and three grounded passive coponents. The realized DPF can provide ideal floating resistor, capacitor, inductor and frequency dependent negative resistor (FDR) through appropriate selection of three grounded passive eleents without any coponent atching constraint. All the DPF based siulated floating coponents can be digitally controlled and possess low sensitivity. To verify the proposed theory the DPF is used to siulate the floating ideal inductor and floating ideal frequency dependent negative resistor (FDR). The siulated ideal floating inductor and ideal floating FDR, respectively have been used to realize the prototype second order low pass filter (LPF) and high pass filter (HPF). These the DPF based LPF and HPF are designed and verified using PSPE and the results thus obtained justify the theory.. THE MOS DPD The digitally prograable differential voltage current conveyor (DPD) sybol is shown in Figure (a) and its MOS ipleentation with 4bit current suing network (S) at portz is shown in Figure (b). The transfer atrix of the DPD can be expressed as Y Y Z Z Thus the port voltages and currents for the DPD can be expressed as Y Y Z Z Y Y where, is an nbit digital control word. The power integer = for current suing network (S) at portz and = for the S at port of the DPD [6]. Z Y Z Y Y Z Z Z Z Fig (a): Sybol for DPD () () 9

2 nternational Journal of oputer Applications ( ) olue 66 o.7, March 3 DD M 5 M 6 M9 M M 9 M M M 3 M 4 M 5 M 33 M 34 M 35 Y M M M 3 M 4 b b b b 3 M 6 M 7 M 5 M 8 M 9 M 3 M 3 M 3 Z M 39 M 4 M 4 M 4 b b b b 3 b b b b 3 Z BB b b b b 3 M 43 M 44 M 45 M 46 M 7 M 8 M M M 3 M 4 M M 6 M 7 M 8 M 36 M 37 M 38 SS Fig (b): The MOS ipleentation of a DPD with 4bit S at Z and Z terinals 3. THE DPF RUT The realized digitally prograable floating ipedance converter (DPF) using DPD of Figure with =, is given in Figure. Z Z Y Z Z Y Z Z 3 (ii) Digitally prograable ideal floating capacitor (): f Z =/s, Z =R and Z 3 =R 3, then =/s( R /R 3 ), with = ( R /R 3 ). (iii) Digitally prograable ideal floating inductor (L): f Z =R, Z =/s and Z 3 =R 3, then = s(r R 3 )/, with L = (R R 3 )/. (iv) Digitally prograable ideal floating FDR (D): f Z =/s, Z =R and Z 3 =/s 3, then = /s ( 3 R ), with D = ( 3 R ). Thus, the realized DPF siulates the digitally prograable ideal floating resistor, capacitor, inductor and FDR without any atching constraint. The increental sensitivity easures of the above realized floating ipedances with respect to various passive eleents and the control word, are analyzed and expressed as follows. Fig : The DPF circuit The routine analysis yields its adittance atrix as follows. Z ZZ 3 Thus the equivalent floating ipedance can be expressed as 3 Z (3) Z Z (4) The realized floating ipedance given in equation (4) can result the following digitally prograable floating ideal eleent siulators through appropriate selection of three grounded ipedances Z, Z and Z 3. (i) Digitally prograable ideal floating resistor (R): f Z =R, Z =R and Z 3 =R 3, then =(R R 3 /R ), with R = ( R R 3 /R ). S (5) Z, Z, Z3, Fro equation (5), it is evident that the increental sensitivity easures of the realized floating ipedance with respect to various passive eleents are unity in agnitude [34]. Taking the tracking errors of the DPD into account, the relationship of the terinal voltages and currents of the DPD can be rewritten as Y Z Z Y ( Y Y where, β is the voltage transfer gain fro Y to terinal and α is the current transfer gain of the D fro to Z terinal. The above transfer gains slightly deviate fro unity and the deviations are quite sall and technology dependent [3]. By including these nonideal effects the DPD the floating ipedance given in equation (4) is odified as follows. ) (6)

3 nternational Journal of oputer Applications ( ) olue 66 o.7, March 3 Z Z 3 (7) Z Thus, fro equation (7) it is observed that the agnitude of the floating ipedance ay get slightly affected due to non idealities of the DPD. 4. DESG AD ERFATO The realized DPF of Figure was designed and verified by perforing PSPE siulation with supply voltage ±.5, using MOS TSM.5 μ technology paraeters. The aspect ratios used are given in the Table. The DPF was used to design a digitally prograable ideal floating inductor (L) and FDR (D), which were used in second order Table : The aspect ratios of the MOSFETs of the DP cutoff frequency f = KHz and Q =.77 at =. Using equation (8) the designed values were found as R =R 3 =R= 37 KΩ, R =6.6KΩ, = ==.43 nf. Then to control the cutoff frequency f, the digital control word was changed to, 4, 8 and 5, and the poleq was readjusted to.77 through R. Thus the results observed are shown in Figure 3(c). L R MOSFETs M, M, M 3, M 4 M 5, M 6 M 7, M 8, M 9, M 3, M 4,, M, M 5, M 7, M 39 M 9, M 6, M 33, M 4 M, M 7, M 34, M 4 M, M 8, M 35, M 4 M, M 5, M 6, M, M 9, M 8, M 43 M, M 3, M 36, M 44 M 3, M 3, M 37, M 45 M 4, M 3, M 38, M 46 W μ L μ Fig 3(a): The prototype second order LPF Y Z Siulated Digitally Prograable deal Floating nductor with L = R R 3/ Y Z Z R R 3 R low pass filter (LPF) and high pass filter (HPF), respectively as shown in Figure 3(a) and Figure 4(a). Thus the resulting DPF based LPF and HPF, are respectively shown in Figure 3(b) and Figure 4(b). The cutoff frequency (f ) and poleq of the LPF with R =R 3 =R and = =, can be expressed as follows. f R 8(a) R 8(b) R Q Siilarly, the cutoff frequency (f ) and poleq of the HPF with = 3 = and R =R =R, can be expressed as follows. f R 9(a) Q 9(b) Thus fro equation (8) and (9) it is evident that the cutoff frequency f of the LPF is directly proportional to the digital control word while for HPF it is inversely proportional to. t is to be noted that with the poleq also increases in both the cases which can be readjusted with resistor R for LPF and with for HPF. nitially the LPF was designed for a Fig 3(b): The DPF based second order LPF = = = 4 = 8 = 5 Fig 3(c): The frequency response of the LPF using Digitally controlled ideal floating inductor realized fro DPF, at different control word Siilarly, the DPF based HPF of Figure 4(b) was also designed for a cutoff frequency f = KHz and Q =.77 at =. Using equation (9) the designed values were found as = 3 ==.43 nf, R =R =R= 37 KΩ, =.68 nf. Then to control the cutoff frequency f, the digital control word was changed to, 4, 8 and 5, and the poleq was readjusted to.77 through. The results observed for HPF are shown

4 nternational Journal of oputer Applications ( ) olue 66 o.7, March 3 in Figure 4(c). Thus the observed results of Figure 3(c) and Figure 4(c), show the close confority with the theory. reconfigurability along with the low sensitivity, over the other floating ipedance converters. D Table : The coparative results /s R L R Ref. o. [3] Fig 3(a) [3] Fig 3(bd) o. of Active Devices 3 o. of Passive Eleents Passive Eleents Matching Digital ontrol 3 o o 5 o o Fig 4(a): The prototype second order HPF and its /s transfored version Siulated Digitally Prograable deal Floating FDR with D = 3R [33] Fig 4 [34] Fig Proposed DPF Fig DD FOA DPD 3 Yes o 5 Yes o 3 o Yes Y Z Y Z Z R 3 R Fig 4(b): The DPF based second order HPF = = = 4 = 8 = 5 6. OLUSO A novel digitally prograable floating ipedance converter is presented which uses two digitally prograable differential voltage current conveyors and three grounded passive coponents. The realized digitally prograable floating ipedance converter provides ideal floating resistor, capacitor, inductor and frequency dependent negative resistor through appropriate selection of three grounded passive eleents without any coponent atching constraint. All the digitally prograable floating ipedance converter based siulated ideal floating coponents are digitally prograable and possess low sensitivity figures. These reconfigurable odules are suitable for realizing the field prograable analog array. To verify the proposed theory the digitally prograable floating ipedance converter is used to siulate the floating ideal inductor and floating ideal frequency dependent negative resistor. The siulated ideal floating inductor and ideal floating frequency dependent negative resistor, respectively have been used to realize the prototype second order low pass filter and high pass filter. The digitally prograable floating ipedance converter based low pass and high pass filters were designed and verified using PSPE and the results thus obtained justify the theory. Fig 4(c): The frequency response of the HPF using Digitally controlled ideal floating FDR realized fro DPF, at different control word 5. OMPARATE STUDY The digitally prograable floating ipedance converter presented in this paper, is copared with soe other floating ipedance converters available in recent technical literature and the coparative results are given in Table. t is observed fro the Table that DPF presented here, enjoys the additional feature of digital prograability and 7. REFEREES [] Wilson, B. 99, Recent developents in current conveyors and currentode circuits, EE Proceedings G, ol. 37,, [] Elwan, H. Q. and Solian, A. M. 997, ovel MOS differential voltage current conveyor and its applications, EE Proc. ircuits Devices Systes, ol. 44, 3, 95. [3] Touazou,., Lidgey, F. J. and Haigh, D. G. 998, Analogue Design: The urrentmode Approach, EE, York, UK. [4] Khan,. A. and Maheshwari, S., Siple first order allpass section using a single, nternational Journal of Electronics, ol. 87, 3, 3336.

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