Equal Area Criterion Scheme to Reduce DC Bus Voltage Stress of Single Stage Single Switch Power Factor Corrected Converter

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1 Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics Available online at SSN (Print): , SSN (Online): , SSN (CD-ROM): AJRSTEM is a refereed, indexed, peer-reviewed, ultidisciplinary and open access journal published by nternational Association of Scientific nnovation and Research (ASR), USA (An Association Unifying the Sciences, Engineering, and Applied Research) Equal Area Criterion Schee to Reduce DC Bus Voltage Stress of Single Stage Single Switch Power Factor Corrected Converter Bindu S J and C A Babu Departent of Electrical and Electronics Engineering School of Engineering, CUSAT, Kochi, Kerala, ndia Abstract: Single Stage Single Switch Power Factor converter topology is selected in such a way that input PFC stage is Discontinuous Current Mode (DCM) boost converter and output stage is Continuous Current Mode (CCM) fly back converter providing wide bandwidth response. Major proble associated with the converter is strong dependency of dc bus voltage stress with the output load. A design solution to avoid this proble is presented by suitable selection of boost inductor using Equal Area Criterion (EAC) and by ipleenting siple closed loop control. Design, siulated studies using Orcad and experiental verifications have been perfored. Proble of voltage stress was found alost eliinated. Keywords: EAC, S4SMR, Switch ode rectifier, power factor converter, PFC. ntroduction ine current haronics are injected to the electrical network by non-linear loads connected to the network, and are ultiples of 50Hz. Coon exaples of such devices found in industrial environents include variable frequency drives, welders, switched ode power supplies, battery chargers, UPS systes, coputers, electronic lighting etc. Usually power converters use a diode rectifier followed by a bulk capacitor to convert AC voltage to DC voltage. Conventional diode rectifiers used in electronic equipent draw pulsed current fro the utility line. Consequently the power factor becoes poor ( ) due to high haronic distortion of the current wavefor. The siple solution to iprove the power factor is to add a passive filter which is usually coposed of a capacitor and an inductor. However, this passive filter is bulky and inefficient since it operates at line frequency. Therefore, a power factor correction stage has to be inserted to the existing equipent to achieve a good power factor. A typical switching power supply presents a nonlinear load to the power source. The high current drawn fro the line is due to the sall conduction angle. Since these power converters draw pulsed current fro the utility line the power factor becoes poor due to high haronic distortion of the current wavefor. Therefore, a power factor correction stage has to be inserted to the existing equipent to achieve a good power factor. Several standard and review articles in the literature have addressed power quality related issues in AC to DC converters. New configurations of power factor corrections are being developed to itigate the haronic effects on the input line current and iprove the power factor. EEE 59 and EC have being developed to specify the liits of haronic pollution levels to acceptable levels that can occur on the syste. The new faily of power factor corrected switching power supplies norally consists of two stages in the power circuit, viz. The input power factor correction stage and the output DC to DC converter stage. Continuous efforts to further ake these power converters copact and cost effective too lead to the developent of new class of power supplies known as Single Stage Single Switch Switch Mode Rectifier, which is the integration of PFC stage and the DC to DC converter stage. t uses only one switch and controller to shape the input current and regulate the output voltage. The energy storage device in between is necessary to absorb and supply the difference between the pulsating instantaneous input power and constant output power []. A ajor proble associated with Single Stage Single Switch power factor converter is strong dependency of DC bus voltage stress across the capacitor with the output load [], []. Power unbalance between PFC stage and DC- DC stage is the inherent reason for causing high DC bus voltage stress. Frequency control is other solution proposed to overcoe high DC voltage stress [3]. But this call for coplex control circuit. The concept of series charging, AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 74

2 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp parallel discharging capacitor schee is another solution.[4].but this call for ore coponent count in the power circuit n this paper a design solution is proposed to avoid the proble of energy unbalance between energy stored during on period of switch and energy dissipated in the load by optially sizing the boost inductor. Maxiu energy stored in the inductor shall be liited to such a value that this energy atches with axiu output power required. The instant at which axiu power delivered shall be atched with the instant when the input ac voltage is at the. Also consider the fact that axiu power is delivered at a duty ratio which is slightly less than the liiting duty ratio (0.5) for DCM operation. Equal Area Criterion is applied between theoretically calculated fundaental coponent of input ac current and the inductor current when t on is axiu. Using this approach the design was carried out, and siulated testing as well as experiental observation showed only a very sall rise in DC bus voltage at light load condition, even under open loop. After introducing closed loop control with output voltage as controlled variable and duty ratio as anipulated variable the DC bus voltage stress was found alost insignificant.. The Bifred Converter Figure : The BFRED PFC ac/dc converter One of the basic configurations of single stage single switch SMR is the BFRED converter which is the acrony for Boost ntegrated with Fly Back Rectifier / Energy storage / DC- DC converters which is shown in Fig..t integrates a DCM boost converter with dc-dc converter. When S is turned on, rectified line input voltage appears across the boost inductor and the output agnetizing inductor stores their energy independently during the on interval of the switch. When the switch is turned off, the stored energies are delivered to the bulk capacitor and to the load. Under light load condition the PFC stage without realizing this, stores the sae energy as that of the heavy load leading to an unbalanced power between the input and the output []. This unbalanced power gets stored across the bulk capacitor causing the dc- bus voltage to increase. One way to take care of this proble is through closed loop control which will autoatically reduces the on duration of the switch by sensing the output voltage thus by striking a power balance. But the dynaic response of the syste being poor this ethod is found not so attractive [].. PFC Converter With Dc Bus Voltage Feedback Figure : Converter with power stage negative feedback An alternative ethod was proposed to use a negative feed back schee in the power stage instead of in the control loop []. Fig shows this schee. A negative feedback voltage V f is obtained by using a feed back winding coupled with the isolation transforer. This will ake the resultant voltage available across boost inductor less when the DC-bus voltage increases, thus putting liit on to the input power drawn and by striking a power balance. AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 75

3 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp V. The Proposed Single Stage Single Switch Pfc Converter Figure 3: The Proposed Single Stage Single Switch PFC converter Proposed converter, shown in Fig. 3, is a odified BFRED converter, which avoids the use of D and the negative voltage feedback V f. Equal area criterion (EAC) is applied to achieve optiu design of boost inductor, coupled with a closed loop control with output dc voltage as controlled variable and duty ratio as anipulated variable so as to eliinate the proble of dc bus voltage stress at light load. V. Design Of PFC Stage By Equal Area Criterion. Figure 4: nput current pulse superiposed on reference current. The rectifier input current is discontinuous in nature. A typical input current pulse superiposed on the reference current Sinωt, is shown in Fig. 4. T = t 0n + t off + t 3 ω ton - On period of boost switch. ω toff - Off period of boost switch. ω t3 - Non-conducting period (dead period). α - nstantaneous switching angle AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 76

4 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp EAC applied to single stage single switch power factor converter eans equalizing the area under a sinusoidal reference current and the area under the input current in the total period of one switching cycle [4]. A. EAC applied to design of boost inductor for the proposed single stage single switch power factor converter Magnitude of the reference current is selected such a way that- P V.. out rs rs ref nstantaneous current i r in on ode of boost switch is, E ir + [ cos cos ( + t)] Where α<ωt<ωt on i in off ode, r E ( V + n V ) () dc ir (cos ton ) cos( + ton t) t At the beginning = 0 E During on tie, ir [cos cos( t)] Where < t< ton (3) Off ode current becoes zero at t t E ( V + n V ) dc 3 [cos ( ton ) cos( + ton t)] t B. Design of Boost nductor. At the end of on duration is axiu ( ). off () Where < t< toff (4) occurs at = 90 and duty cycle is axiu. The off duration followed by this will be iniu. Value of has to be selected in such a way that current at the end of this iniu off duration is zero. Fro (3) E sinton (5) sinton ton since switching frequency is high. E t E t E DT (6) on on E DT Where D is duty cycle (7) C. DC bus voltage, output voltage and Duty ratio. Fro (4), (5) with 3 =0 and assuing t3 0 ` ( dc + n ) 0 E ( sin ton sin ton toff ) V V toff (8) ( dc + n ) 0 E (sinton sin ton ) E sin( ton toff ) V V toff (9) ( Vdc + n V ) E t ( t t ) (0) off on off ( V + n V )( t t ) E T () dc on ( V + n V ) t ( V + n V ) t E T () dc dc on AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 77

5 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp ton ( Vdc + n V E) = T ( Vdc + n V ) (3) E D ( Vdc + n V ) (4) E Vdc nv D (5) V. Design Of Output Converter Stage[8]. A. Voltage transfer function for fly back converter. Always volt second balance should be there. Priary Volt sec/turn= Sec volt sec/turn. DT ( V Vd )( D) T ( V Vswic ) (6) N N V ND V N ( D ) (7) B. Voltage Transfer function of single stage single switch power factor converter We can write output voltage V as V V E D ( nv ) D n ( D) ED n( D) C. Design of fly back converter. For Volt second transforer balance ( V V ) D n( V V )( D) (0) sat f At critical inductance, the inductor current is twice the average. V T c on p () C V D p () f s C f p s C V D (3) we have n P( D) V i( avg ) (4) R V P (5) R( D) n fro (), (5) ( V V f ) R( D) n C (6) Vf s (8) (9) AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 78

6 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp V. Design of A 00 Watt, 30 V, 50 Hz, 50 V Dc Single Stage Single Switch Power Factor Converter A. Calculation of using EAC. Switching instant is considered as = 90 f 0kHz, s D 0.6 P V out rs rs 00 rs A A Value of is calculated using EAC as follows A 6 DTE /.57H.696 B. Calculation of C C is calculated for D = 0.6 Using (4), (33).H C C. Calculation of energy storage capacitor. DTE = Ap Energy Stored = J Energy Stored = CV CV C C 6F 3 We have p = V. Relationship between D and oad = Vo = = AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 79

7 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp f=rn (-D) R= n (-D) = n(-d)= -D= D= Fro the above equation we can conclude that for a given circuit duty ratio is function of load. X. Siulation Results. Siulation of the proposed single stage single switch power factor converter with the designed value of circuit paraeters was carried out using Orcad software package. Siulation results were found eeting the design intends. Figure 5: Shows that nput PFC converter works in DCM Figure 6: Shows that DC-DC converter operates in CCM Under closed loop condition when load is suddenly reduced due to the instantaneous power unbalance, the dc bus voltage and output voltage tend to increase. Fig. 7 shows the increase in output voltage is iediately detected by the controller and duty cycle is autoatically reduced, the closed loop is found taking the corrective action leading to a new energy balance. AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 80

8 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp Figure 7: Shows the autoatic reduction in the agnitude of input current under closed loop control when the load is reduced after 35s Figure 8: Shows that under open loop there is substantial increase in output voltage when load is reduced after 45 s also very sall changes in the dc bus voltage and no change in input current is seen. Fig. 8 shows under open loop condition input current does not know what happens at the output converter. Figure 9: Shows haronic spectru of input current in closed loop AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 8

9 Bindu S J et al., Aerican nternational Journal of Research in Science, Technology, Engineering & Matheatics, 6(), March-May, 04, pp Fig.9 indicates fundaental frequency of 50 Hz is doinant and higher order coponents are insignificant X. Experiental Results Experiental 30V, 50Hz input, 0-00V dc, 00w single stage single switch power factor converter has been built and tested using MOSFET RFPF50 as switch, to verify the results obtained during siulated test. Experiental results are found in line with the results obtained during siulation when tested in open loop as well as closed loop condition. Fig. 0 shows sinusoidal nature of input line current and input power factor close to unity. Figure 0: Shows that inductor current drawn is sinusoidal in DCM operation of PFC stage. X. Conclusion Single stage single switch power factor corrected converter design by applying EAC to deterine value of boost inductance and by using closed loop control is presented. The dc bus voltage stress at light load is found copletely eliinated under closed loop operations. Output voltage regulation using duty ratio variations and fixed switching period is the ost siple ethod of control. For noral perforance of the converter the duty ratio needs to be liited up to 0.5. Experiental results deonstrate that it is possible for the proposed converter to have fast response and low line current haronic content. X. References []. M. Madigan, R. Erickson and E. sail, "ntegrated High Quality Rectifier Regulators" in EEE power Electronics Specialist Conf. 99. p.p []. Jinrong Qian, Fred C. ee, "Single - Stage Single - Switch p -f-c Ac/Dc converters with DC - Bus voltage feedback for universal line applications"in EEE transactions on P.E. vol: 3, No-6 Nov 998 p.p [3]. Esa Haid sail, Robert Erickson, "Single Switch 3 phase PWM low Haronic Rectifiers" in EEE Transactions on P.E. vol:, No-, arch 996 p.p [4]. Manjusha S. Dawande, Gopal K. Dubey, Prograable nput PFC ethod for SMR" in EEE Transactions on P.E. vol:, No-4 July 996 p.p [5]. A.R. Prasad, P.D. Ziogas. Stefanos Manias, "An active PFC Technique for 3 phase diode rectifiers" in EEE Transaction on P.E. vol: 6, No-, January 99 p.p [6]. Richard, Balogh, Nathan O.Sokal, A new faily of single stage isolated PFC with fast regulation in PESC p.p [7]. Yiin Jiang and Fred C. ee, "Single - stage Single - Phase parallel power factor correction schee" in PESC 94 p.p [8]. DC -DC Switching regulators by D.M. Mittchel [9]. C Qiao and Keyue M. Sedley, "A Topology Servey of Single - Stage P.F.C. with a Boost Type input Current - shaper." n EEE APEC February 6 0. [0]. Stefanos Manias, Phoivos D. Ziogas and Guy Olivier "An AC to DC converter with iproved input power factor and high power density"in EEE Transaction on.a., vol: A -, No - 6 Nov/Dec 986. p.p []. Manjusha S. Dawande, Vilas R. Kanetkar and Gopal k. Dubey "Three-Phase Switch Mode Rectifier with Hysterisis Current control" in EEE Transactions on P.E., vol:, No-3, May 996 p.p []. Design of Magnetic Coponents for Switched Mode Power Converters by. Uanand and S. R. Bhat, p37, p [3]. Martin H.. Chow, Yi-Shu ee, and Chi K. Tse Single-Stage Single-Switch solated PFC Regulator with Unity Power Factor, Fast Transient Response, and ow-voltage Stress in EEE Transactions on P.E., vol: 5, No-, Jan 000 p.p [4]. A.K Jha,B.G Fernandes and A.Kishore A Single Phase Single Stage AC/DC converter with high input power factor and tight output regulation in Progress in Electroagnetic Research Syposiu 006,Cabridge,USA,March 6-9.pp 3-38 [5]. Mohan,N.,T.M. Undeland and W.P.Robbins, Power Electronics, Converters, Applications, And Design, nd Edition,John Wiley and Son,nc. Newyork,995. [6]. Oscar 8]Oscar Garcia,Jose A. Cobos,Pedro alou, Roberto Prieto,snd Javier Uceda, "A Siple Single-Switch Single-Stage AC/DC Converter with Fast Output Voltage Regulation " in EEE Transactions.on Power Electronics,, Vol.7,No.March 00. AJRSTEM 4-3; 04, AJRSTEM All Rights Reserved Page 8