Tunable Gm-C Floating Capacitance Multiplier

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2 Tunable Gm-C Floating Capacitance Multiplier Wipavan arksarp Yongyuth aras Department of Electrical Engineering, Faculty of Engineering, Siam University, Siam U Bangkok, Thail wipavan.nar@siam.edu,yongyuth.nar@siam.edu Vinai Silaruam Department of Telecommunication Engineering, Faculty of Engineering, Mahanakorn University of Technology, MUT Bangkok, Thail vinai@mut.ac.th Abstract This paper presents a realization of Gm-C floating capacitance multiplier. t employs MOS transistors as transconductors only one grounded capacitor. The circuit offers the attractive features of simple configuration, electronically tunable capacitance multiplication factor, low sensitivities to variation of active passive elements suitability for integrated circuit implementation. The parasitic effects of the transconductors on the proposed floating capacitance multiplier are investigated. The performance of the proposed circuit is demonstrated on second-order b-pass filter. The SCE simulations using TSMC 0.8 µm CMOS process parameter are also given to confirm the theoretical analysis. Keywords floating capacitance multiplier; grounded capacitor; transconductor; high-pass filter; b-pass filter. TRODUCTO A capacitor is an important element in circuit design can be used in many blocks such as filters, oscillators, impedance matching circuitry. n modern integrated circuit design, the fabrication of high-valued integrated capacitors is a major problem, owing to their large occupation of silicon area. A possible solution of the problem is represented using the capacitance multiplication method. Thus, capacitance multipliers have received considerable attention. This attention is widely focused on the capacitance multiplication employing several active building blocks such as second generation current conveyors (CCs) [-, 4, 5], operational amplifier (OAM) operational transconductance amplifiers (OTAs) [3], current-controlled differential difference current conveyors (CCDDCCs) [6], voltage differencing buffered amplifier (VDBA) [7] Current amplifier DUA [8]. The circuit of [-5] provides a grounded capacitance multiplier. However, a floating capacitance multiplier can offer wider applications than a grounded capacitance multiplier. The floating capacitance multipliers have been reported [3-6]. The circuit of [5] requires two OTAs, an OAM, a voltage buffer, an ungrounded capacitor. The circuit enjoys the attractive feature of electronic tuning of capacitance multiplication factor. But it might have the bwidth the slew rating problems because of the OAM used not attractive for integrated circuit implementation. Since the CC offers several advantages such as larger dynamic range, wider bwidth, greater linearity over voltage-mode counterpart like OAM [9-0], it is very attractive for realization of the floating capacitance multiplier. The CC-based floating capacitance multipliers have been proposed [4-5]. However, the floating capacitance multipliers do not offer electronic tunability. The new floating capacitance multiplier recently reported in [6] employs three CCDDCCs a grounded capacitor. t provides the attractive features of electronic tuning of the capacitance multiplication factor suitable for integration. Unfortunately, the circuit employs many transistors consequently suffers from high power consumption large area occupation in integrated circuit fabrication. Reference [7] has been proposed the tunable capacitance multiplier with a VDBA. t consists of one floating capacitor an external resistor. Recently, [8] is presented the floating capacitance multiplier. However, the floating capacitor is employed in the same as [7]. n this paper, a new floating capacitance multiplier based on Gm-C is presented. t consists of sixteen MOS transistors as transconductors a grounded capacitor. The multiplication factor of the proposed capacitance multiplier can be tuned electronically by current bias of the transconductor. Since the circuit employs the grounded capacitor no external resistor, it is suitable for integrated circuit implementation. SCE simulation results of the proposed circuit its application show good agreement with the theoretical analysis.. CRCUT DESCRTO A. Basic Circuit Configuration The basic circuit of the proposed floating capacitance multiplier is shown in Fig. (a), consisting of five voltagecontrolled current sources only one grounded capacitor. n Fig. (b), its equivalent circuit is shown. The current voltage relations of node A node B produce skc VA ( V V). () kk 3 Setting k 4 = k 5 gives k V, () 4 A k V. (3) 4 A Substituting () into () (3) yields the following short circuit admittance matrix 4 Y sk k C kk 3, (4) /8/$ EEE 43

3 where k i is the transconductance gain of the i th voltagecontrolled current source. From (4), the basic circuit realizes a floating capacitance multiplier with the equivalent capacitance as C eq k ( V V ) kk 4 C. (5) kk A 3 kv 4 A kv B 3 A 5 A V V kv B kv V V DD B M M M3 M4 B V SS (a) V V V V (b) Fig.. (a) Simple transconductor, (b) its equivalent circuit. gv m gmv C (a) V C eq V (b) Fig.. (a) roposed basic circuit, (b) its equivalent circuit. t is noticed that the equivalent capacitance value is tuned by changing the transconductance gains. The proposed floating capacitance multiplier based on G m -C is described in the following section. B. roposed Floating Capacitance Multiplier As previously discussed in the last section, the proposed floating capacitance multiplier employs the transconductors. Thus, the significant properties of the transconductor are briefly reviewed. A simple transconductor using four CMOS transistors two bias current sources is shown in Fig. (a) []. t is assumed that all transistors operate in the saturation region have the same transconductance parameters. The equivalent circuit of the transconductor is illustrated in Fig. (b). The output currents of the transconductor yield g V, (6) m g V, (7) m where g m is the transconductance value of the MOS transistor defined by W gm ( ncox B ), (8) where µ n is the electron mobility, C ox is the oxide capacitance per unit area, W/ is the aspect ratio of the transistor B is the bias current of the transconductor. Since the voltagecontrolled current sources of the basic circuit as shown in Fig. (a) replaced by the transconductor of Fig. (a), the realization of the proposed floating capacitance multiplier is shown in Fig. 3. Fig. 3. roposed floating capacitance multiplier. This proposed circuit employs four transconductors only one grounded capacitor. Routine analysis of the circuit yields the following admittance matrix m m4 Y sg g C gmgm3, (9) where g mi is the transconductance value of the transconductor. Comparison of (4) (9) results k i = g mi, then the equivalent capacitance of the proposed circuit can be expressed as C eq gmgm4 C g g. (0) m m3 From (0), the capacitance multiplication factor is given by gmgm4 K. () g g m m3 Thus, the multiplication factor, K, can be electronically adjusted by changing the bias currents of the transconductors. The sensitivities of the equivalent capacitance with respect to active passive elements yield the acceptably low values as follows: C C C C C g g g g C eq eq eq eq eq S S S S S. () m m m3 m4 i th 44

4 C. High Frequency Consideration From (9), the short circuit admittance matrix of the proposed circuit has been realized by considering the ideal description of the transconductor. For high frequency application, the parasitic elements of the transconductor affect the frequency response of the proposed circuit. The equivalent circuit of the transconductor with the parasitic elements is shown in Fig. 4. t is shown that input terminal exhibits lowvalue capacitances C + C - output terminals exhibit low-value capacitances C C with low-value conductances G G, respectively. Considering the above parasitic elements, routine analysis of the proposed circuit as shown in Fig. 3 gives the following short circuit admittance matrix Z X // ZT Z T Y3, (3) ZT Z X // Z T where ZX ZX s( C C ) G s( C C ) G Z T 4 4 m m gmgm3 T [ s( C C C3) G3],where Δ T is g g [ s( C C C ) G ] given by T s( C C C 3 C 4) G G. ote that the terms of impedances /[s(c + +C 4 ) + G 4 ] /[s(c - + C 4 ) + G 4 ] are effective at very high frequencies. t is also high frequency limitation depending on the passive element selection. The limitation at high frequencies is found to be G3 G4 G4 min,,.(4) C C C3 C C 4 C C4 t is seen from (4) that C is chosen as small as possible to increase the high frequency performance of the proposed circuit.. ACATO EXAMES A. Second-order High-pass B-pass Filters To illustrate an application of the proposed floating capacitance multiplier of Fig. 3, it is used to implement an active capacitor in a second-order b-pass filter (BF) as shown in Fig. 5 []. V R roposed floating capacitance multiplier Ceq Fig. 5. Second-order b-pass filter. The transfer function of the filter can be expressed as H BF gmgm3 s g m g m4 RC () s gmgm3 gmgm3 s s g g RC g g C m m4 m m4 V O (5) The center or resonant frequency ω 0, quality factor Q bwidth BW of the BF can be given as g g g g C m m3 m m4 0, Q R gmgm4c g m g m3 gmgm3,an BW. g g RC m m4 The sensitivities of the filter parameters are found as Sg S m g S m g S m3 g S m4 SC, (6) Q Q Q Q Q Q Q Sg S m g S m g S m3 g S m4 SC S R, (7) BW BW BW BW BW BW S S S S S S, (8) gm gm gm3 gm4 R C which are all no more than unity in absolute value. Thus, the proposed circuit exhibits an attractive sensitivity performance. V C C V gv m gmv C C Fig. 4. The equivalent circuit with parasitic elements of the transconductor. G G V. SMUATO RESUTS To verify the performance of the proposed floating capacitance multiplier as shown in Fig.3, it has been simulated using SCE program based BSM3 level 7 transistor models for the TSMC 0.8µm CMOS process with ±0.9 V supply voltage. The parameters of the MOS the MOS transistors are listed in [3] available from MOSS. The aspect ratios (W/) of CMOS transistors are assumed of 3.6 µm/0.54 µm for MOS 9 µm/0.54 µm for MOS. Fig. 6 shows impedance values relative to frequency of the proposed circuit with different bias current of the first transconductor, B. Similarly, the floating capacitances were simulated by adjusting B. The results of the capacitances are shown in Fig. 45

5 7. They confirm that the simulated capacitance can be adjusted by control the bias currents of the transconductors. Fig. 6. mpedance characteristics of the proposed circuit for different bias current. Fig. 7. Variation of the simulated capacitances versus ideal ones as the bias current is varied. Fig. 8. Simulated ideal frequency responses of the BF as shown in Fig. 6. For the application example, Fig. 8 shows the simulated ideal frequency responses of the BF as shown in Fig. 5. The filter is designed on the nf proposed floating capacitance multiplier of Fig. 3 passive elements of R =.3 kω =.3 mh, resulting in the center frequency of f 0 = 50 khz, a quality factor of Q =, a bwidth of BW = khz. The proposed capacitance multiplier is set as follows: B = B4 = 00 µa, B = B3 = 0 µa, C = 00 pf. t should be noticed that the simulated result of the filter very closely approximates the theoretical one. V. COCUSO The floating capacitance multiplier-based G m -C is proposed in this paper. ts configuration is very simple. t employs only a grounded capacitor without another passive element, so the proposed capacitive multiplier is particularly attractive for C implementation. Moreover, the multiplication factor of the proposed circuit can be electronically tuned by changing the bias current of the transconductor. The simulation results of the proposed capacitance multiplier its application show good agreement with the theoretical predictions. REFERECES [] G. Ferri. Guerrini, High-valued passive element simulation using low-voltage low-power current conveyors for fully integrated applications, EEE Trans. Circ. Syst.: Analog Digital Signal rocessing, vol. 48, no. 4, p , 00. [] A. A. Khan, S. Bimal, K. K. Dey, S. S. Roy, Current conveyorbased R- C- multiplier circuits, nt. J. Electron. Commun., vol.56, no. 5, p. 3 36, 00. [3] M. T. Ahmed,. A. Khan,. Minhaj, ovel electronically tunable C-multipliers, Electron. ett.,, vol. 3, no., p. 9, 995. [4] S. Minael, E. Yuce, O. Cicekoglu, A versatile active circuit for realising floating inductance, capacitance, FDR admittance converter, Analog ntegr. Circ. Sig. rocess., vol. 47, no., p. 99 0, 006. [5] E. Yuce, Floating inductance, FDR capacitance simulation circuit employing only grounded passive elements, nt. J. Electron., vol. 93, no. 0, p , 006. [6]. rommee M. Somdunyakanok, CMOS-based current-controlled DDCC its applications to capacitance multiplier universal filter, nt. J. Electron. Commun., vol.65, no., p. 8, 0. [7] S. Unhavanich, O. Onjan, W. Tangsrirat, Tunable capacitance multiplier with a single voltage differencing buffered amplifier, roc.mecs06, Hong Kong, March 06. [8] M. A. Al-absi, A new tunable floating capacitance multiplier, nt. J. Electron. ett., p-0, Febuary 07. [9] C. Toumazou, A. ayne, D. Haigh, Analog C Design: The Current Mode Approach. ondon: eter eregrinus, 990. [0] G. Ferri. C. GUERR, ow Voltage ow ower CMOS Current Conveyors. Boston: Kluwer Academic ublishers, 003. [] A. F. Arbel,. Goldminz, Output stage for current-mode feedback amplifiers, theory applications. Analog ntegrated Circuits Signal rocessing, 99, vol., no.3, p [] A. B. Williams, F. J. Taylor, Electronic Filter Design Hbook: C, Active, Digital Filters. nd ed. Singapore: McGraw-Hill, 988. [3] The MOSS Service, United States. Wafer electrical test data SCE model of TSMC 0.8 µm CMOS process parameter. 4 pages. [Online] Cited Available at: 46