Radio Frequency and Analog CMOS Integrated Circuit Design Methods for Low-Power Medical Devices with Wireless Connectivity

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Radio Frequency and Analog CMOS Integrated Circuit Design Methods for Low-Power Medical Devices with Wireless Connectivity"

Transcription

1 Radio Frequency and Analo OS Interated ircuit Desin ethods for Low-Power edical Deices with Wireless onnectiity A Dissertation Presented by HUN-HSIANG HANG To The Departent of ELETRIAL AND OPUTER ENGINEERING in partial fulfillent of the requireents for the deree of Doctor of Philosophy in the field of ELETRIAL ENGINEERING Northeastern Uniersity Boston assachusetts Noeber 05

2 Abstract The onoin iproeents of copleentary etal-oxide seiconductor (OS) technoloies are enablin the interation of an increasin nuber of analo and diital circuits into sinle chips which is a trend that continuous to result in perforance enhanceents and saller portable electronic deices with wireless connectiity. A ajor challene is that the radio frequency (RF) front-end section consues excessie power in any new battery-powered wireless deices. For this reason it is essential to create noel analo circuit desin ethods with sinificant power reductions for shortrane counication applications. In this dissertation linearity enhanceent techniques for analo RF front-ends are proposed and deonstrated with a subthreshold low-noise aplifier (LNA) and an actie down-conersion ixer. The linearization ethods inole extra passie coponents to accoplish partial cancellation of third-order nonlinearity products thereby reducin the distortion caused by subthreshold biasin to enable ore widespread adoption of low-power desin techniques. A.8GHz LNA was desined and fabricated with 0.µ OS technoloy to proe the concepts. Test chip easureent results reeal that the linearized low-power LNA has a 5. db oltae ain a 3.8dB noise fiure and a -3.7dB third-order interodulation intercept point (IIP3) with a power consuption of 0.336W. Another.GHz LNA fabricated in 0.3µ OS technoloy has a 9dB oltae ain a 5.8dB noise fiure and a 0dB IIP3 with a power consuption of 0.3W. A linearized low-power RF receier frond-end (LNA and ixer) was also fabricated in 0.µ OS technoloy and ealuated with easureents. This.95 GHz RF front-end has 0.6dB oltae ain a 6dB double-side band noise fiure and a -0.8dB IIP3 with a power consuption of 0.9W. Another product of this research is an input ipedance boostin ethod that was deeloped for lon-ter onitorin of electroencephaloraphy (EEG) sinals. An instruentation aplifier (IA) hain a power consuption of 93.6μW in 0.3μ OS technoloy was desined with a neatie capacitance eneration technique to

3 cancel the aderse effects of input capacitances fro the electrode cables and printed circuit boards. The IA with neatie capacitance eneration feedback (NGFB) does not consue any extra power to boost the easured ipedance fro below 40Ω to aboe 500Ω at 50Hz after proper adjustent of its diitally proraable capacitors when the equialent capacitance at the input is 50pF. Based on siulation and easureent results the iportant instruentation aplifier perforance paraeters are not sinificantly affected by addition of the proposed input capacitance cancellation technique. 3

4 Acknowledeents First and foreost I would like to thank y dissertation adisor Prof. arin Onabajo for his uidance and support throuhout these past four and half years. I would also like to thank y coittee ebers Prof. Yon-Bin Ki and Prof. Nian X. Sun for their uidance throuh the final staes of y Ph.D. deree copletion; especially Prof. Ki who ade soe of the chip fabrications possible with his support and entorship. I would like to thank Li Xu and Kainan Wan who assisted e to easure the RF chips and discussed the results with e on nuerous occasions. I want to thank Alireza Zahrai Li Xu and Kainan Wan for collaboratin on the SAFELAB project. Without their hard work I could not hae copleted the input ipedance boostin technique for EEG applications. I also thank Hari hauhan In-Seok Jun and Yonsuk hoi for workin toether on an RF built-in testin project. I thank the National Science Foundation for financial support of the research projects under awards #34969 and #453. Finally to y wife Shih-wei thank you for encouraeent and support. Without you I could not hae finished y Ph.D. study. 4

5 Table of ontents. Introduction.... Oeriew of desin requireents in eerin applications.... Low-power RF front-end circuit desin challenes Analo circuit desin challenes in EEG front-ends ontributions of this research Subthreshold RF ircuit Analysis and Desin onsiderations /I D ethodoloy ontribution and distribution of parasitic capacitances Nonlinearity analysis Volterra series analysis oon-source aplifier sall-sinal odel..... oon-ate aplifier sall-sinal odel Linearization of Low-Power RF Frond-End ircuits Input ipedance atchin optiization for low-power low-noise aplifiers LNA input ipedance analysis and tunin ethod Siulation results onclusions Proposed low-noise aplifier desin techniques Analysis and desin of the linearized LNA LNA easureent results onclusion Proposed ixer desin techniques Analysis and desin of a linearized ixer ixer siulation results

6 3.3.3 RF front-end easureent results onclusion Analo Frond-End ircuits for Brain Sinal Acquisitions with Dry Electrodes Syste-leel considerations Instruentation aplifier Instruentation aplifier sall-sinal odel analysis Neatie capacitance eneration feedback analysis IA siulation results EEG front-end easureent results IA ain easureent results Input ipedance easureent results onclusion General onclusion and Future Work Appendices Appendix A Appendix B Appendix Appendix D References

7 List of Fiures Fiure. WBAN exaple for edical applications Fiure. oparison of power s. data rate for arious wireless standards Fiure 3. Basic perforance ealuation setup for an NOS deice Fiure 4. Drain current (I D ) with loarithic scale and current efficiency ( /I D ) s. oerdrie oltae (V OV )... 8 Fiure 5. ontribution of parasitic capacitances to the total ate capacitance ( ) s. /I D... 9 Fiure 6. Transition frequency (f T ) s. /I D... 9 Fiure 7. Noralized nd-order and 3rd-order transconductance characteristics of an NOS deice Fiure 8. (a) S aplifier (b) nonlinear sall-sinal odel of a S aplifier.... Fiure 9. (a) G aplifier (b) nonlinear sall-sinal odel of a G aplifier Fiure 0. onentional cascode LNA with inductie source deeneration Fiure. Sall-sinal odel of transistor... 7 Fiure. Siplified sall-sinal odel of transistor Fiure 3. A eneral odel of the iller effect related to transistor Fiure 4. Siplified equialent circuit of Fiure Fiure 5. Scheatic of the n-bit capacitor network for S copensation Fiure 6. Input ipedance atchin coparison between conentional and proposed equations for different operatin reions Fiure 7. Input ipedance atchin coparison between conentional and proposed equations for different transconductance alues of Fiure 8. Layout of the reference LNA Fiure 9. Layout of the tunable LNA Fiure 0. Linearized subthreshold LNA Fiure. Diitally-proraable capacitor ( d_ext ) for linearity tunin Fiure. Nonlinear sall-sinal odel of the LNA s input stae with... 4 Fiure 3. Nonlinear sall-sinal odel of the LNA s cascode stae with

8 Fiure 4. (a) Siulated oltae ain fro V in to V x of the LNA with and without L and d_ext (ideal coponents) and (b) calculated results of ε(δωω) for L with three d_ext cobinations in the cascode stae (with ) Fiure 5. Siplified sall-sinal odel for reerse isolation analysis of transistor Fiure 6. hip icroraph of the fabricated linearized subthreshold LNA in Donbu 0.µ OS technoloy Fiure 7. LNA PB with IIP3 tunin functionality Fiure 8. Setup for S-paraeter easureents Fiure 9. Two-tone test setup Fiure 30. Setup for noise easureent Fiure 3. easured scatterin paraeters of the linearized LNA with buffer (5.9dB loss) Fiure 3. easured noise fiure of the linearized LNA with buffer Fiure 33. (a) easured IIP3 of the linearized LNA with buffer (b) output spectru fro a test with two tones at.8 GHz and.7995 GHz and an input power of -35 db Fiure 34. easured -db copression point of the linearized LNA with buffer at.8 GHz Fiure 35. Linearized subthreshold LNA in IB 0.3µ OS technoloy (a) scheatic and (b) chip icroraph Fiure 36. IIP3 s. d_ext coparison (siulation s. easureent results) Fiure 37. Proposed linearized subthreshold ixer Fiure 38. Sall-sinal odel of the linearized ixer Fiure 39. (a) Equialent half-circuit of the sall-sinal odel in Fiure 38 (b) siplified sall-sinal odel Fiure 40. Nonlinear sall-sinal odel of the ixer s transconductance stae Fiure 4. Exaple ealuation: ε(δω ω) s. L for different alues of c Fiure 4. Sall-sinal odel for conersion ain analysis Fiure 43. Layout of the linearized ixer Fiure 44. Output spectru fro a siulation with -30 db input power

9 Fiure 45. IIP3 cure (typical corner case in Table 9) Fiure 46. Siulated ixer IIP3 and oltae ain s. LO power (typical corner case in Table 9) Fiure 47. Scheatic of the linearized subthreshold RF front-end Fiure 48. hip icroraph of the fabricated linearized subthreshold RF front-end in Donbu 0.µ OS technoloy Fiure 49. PB for RF front-end testin Fiure 50. Block diara of the RF front-end easureent setup Fiure 5. easured S of the RF front-end Fiure 5. easured NF DSB of the RF front-end (IF = 0 Hz) Fiure 53. (a) easured IIP3 of the RF front-end with balun (9.5dB loss) (b) output spectru fro a test with two tones at 0 Hz and Hz and an input power of db Fiure 54. easured -db copression point of the RF front-end with input and output baluns (at IF = 0 Hz) Fiure 55. easured output aplitude before the output balun Fiure 56. Basic neatie ipedance conerter (NI) where Z in = -Z when R = R Fiure 57. Analo front-end for EEG sinal easureents with electrode cable capacitances and calibration blocks for input ipedance boostin Fiure 58. urrent injection with the test current enerator Fiure 59. (a) Instruentation aplifier (IA) with direct current feedback and neatie capacitance eneration feedback (NGFB); (b) ariable R ipleentation; (c) input biasin circuitry Fiure 60. (a) Sall-sinal odel of the IA s input and feedback staes; (b) sall-sinal odel of the IA s output stae Fiure 6. Neatie capacitance eneration feedback (NGFB) with proraable capacitors between nodes i+ and (and nodes i- and D ) Fiure 6. Voltae swins at the IA input with current injection fro the OTA for two cases: i.) with NGFB ii.) without NGFB. (Noise was actiated durin the transient siulations based on the interated noise density fro 0.0Hz to 00Hz.)

10 Fiure 63. onte arlo siulation results of both IAs. RR: (a) IA without NGFB and (b) IA with NGFB PSRR: (c) IA without NGFB and (d) IA with NGFB THD: (e) IA without NGFB and (f) IA with NGFB Fiure 64. Noise distributions: (a) IA without NGFB (b) IA with NGFB Fiure 65. Ipedances at the IA inputs with and without NGFB for different sp and sn alues: (a) sp = sn = 00 pf (b) sp = 00 pf and sn = 50 pf Fiure 66. Input ipedance coparison (at Z inp ) for the IAs with and without NGFB in different process corner cases Fiure 67. hip icroraph of the fabricated EEG front-end with input ipedance boostin capability in IB 0.3µ OS technoloy Fiure 68. Four oltae ain settins of the IA: (a) 0dB (b) 30dB (c) 40dB and (d) 50dB Fiure 69. easured EEG front-end frequency responses for four ain settins Fiure 70. Output-referred noise easureent of the coplete EEG front-end Fiure 7. HD3 easureent at 5Hz with a 5Hz sinusoidal input hain a differential aplitude of (a) 00μV and (b) 600μV Fiure 7. Input coon-ode ain easureent: differential front-end output spectru durin a test with a 5V sinusoidal coon-ode input sinal at 0Hz Fiure 73. Power supply ain easureent: differential front-end output spectru durin a test with a 5V sinusoidal sinal injected at the power supply rail with a frequency of 0Hz Fiure 74. Test setup for IA input ipedance easureents Fiure 75. Input ipedances s. different codes: (a) in = 50pF (b) in = 00pF and (c) in = 50pF

11 List of Tables Table Suary of popular low-power wireless standards... 3 Table. Desin paraeters of the reference LNA and tunable LNA Table 3. Post-layout siulation coparison of the reference LNA and tunable LNA at.4 GHz Table 4. Tunable LNA perforance coparison with other published results Table 5. Linearized subthreshold LNA desin paraeters Table 6. oparison of LNA easureent results Table 7. Gain and third-order interodulation distortion of the subthreshold LNA in IB 0.3µ OS technoloy for all linearity tunin settins Table 8. ixer desin paraeters Table 9. Siulation results with f RF =.4 GHz f RF =.398 GHz and f LO =.4 GHz for process corner cases (V DD = 0.6V) Table 0. oparison of ixer desins Table. RF front-end desin paraeters Table. oparison of low-power RF front-ends Table 3. Paraeters of the IA desins in IB 0.3μ OS technoloy without and with NGFB Table 4. oparison of instruentation aplifier siulation results... 89

12 . Introduction The onoin iproeents of copleentary etal-oxide seiconductor (OS) processin technoloies are enablin the interation of an increasin nuber of analo and diital circuits into sinle chips which is a trend that continuous to result in perforance enhanceents and saller portable electronic deices with wireless connectiity. A ajor challene is that radio frequency (RF) front-end odules often consue ore than 60% of the power budet in transceiers []. Therefore it is not only necessary to deelop wireless standards for low-power short-rane counication applications but also to create noel analo circuit desin ethods with sinificant power reductions.. Oeriew of desin requireents in eerin applications any kinds of low-power wireless standards and circuit desin approaches hae been deeloped for low-rate wireless personal area network (WPAN) or wireless body area network (WBAN) applications []-[]. These standards include IEEE IEEE Bluetooth low enery (BLE) Near Field ounication (NF) and Global Positionin Syste (GPS). The applications of low-power wireless standards include health onitorin fitness payent and sart hoe applications. Fiure illustrates a WBAN scenario as an exaple of reote edical onitorin. In this application patients could use iplantable or wearable bioedical sensors with wireless connectiity to upload their health inforation to doctors iediately [6]-[9]. Table suarizes the key paraeters for BLE IEEE and IEEE for the physical layer [4] []. As shown in Fiure the required power consuption of the WBAN deices is lower than other existin wireless standards [6]. Fro Table and Fiure low-data rate wireless standards hae two key characteristics which are low-power consuption and short counication distance.

13 Fiure. WBAN exaple for edical applications. Table Suary of popular low-power wireless standards BLE IEEE IEEE Frequency rane ghz.4ghz/ 868Hz/ 95Hz Data rate bps 0 kbps up to 50 kbps ghz/.36-.4ghz(us)/ (400/868/95/950Hz) 75.9 kbps up to 97.4 kbps Network size Undefined Up to deices Up to 56 deices Rane

14 Fiure. oparison of power s. data rate for arious wireless standards.. Low-power RF front-end circuit desin challenes The current deand for cost-effectie low-power RF front-end circuit desins is hih because of the iportant need to extend the battery life of portable deices such as in obile wireless consuer electronic deices and personal health onitors. Transistors operated in the subthreshold (or weak inersion) reion offer opportunities to iniize power consuption in low-power OS RF front-ends. Oer the past years soe subthreshold (weak inersion) LNAs and ixers were reported to achiee lower power consuption []-[7] which is ade possible by hiher transconductance-to-drain current ratio ( /I D ) and lower power supply oltae (V DD ). Howeer the prealent desin challene associated with subthreshold LNAs is linearity deradation. For exaple in published subthreshold LNAs and ixers []-[7] the third-order interodulation intercept point (IIP 3 ) is typically less than -0 db. There are three distinuishin characteristics for subthreshold biasin copared to stron inersion biasin: ) Hiher power efficiency: transistors biased in subthreshold can proide a hiher /I D ratio than those biased in stron inersion. Furtherore the drain-to-source oltae (V DS ) can be lower which perits the use of lower power supply oltaes at the expense of slihtly hiher noise fiure. 4

15 ) The chane of the contribution and increase of parasitic capacitances: In subthreshold the ate-to-source capacitance ( s ) no loner doinates iplyin that the ate-to-drain capacitance ( d ) and the ate-to-bulk capacitance ( b ) hae to be taken into account for ore sophisticated desin. oreoer to achiee siilar transconductance ains as in stron inersion it is required to increase the transistor widths which results in hiher parasitic capacitances and lower transition frequency (f T ). 3) Linearity deradation due to hihly positie 3 / : The sin of 3 chanes fro neatie to positie when the transistor biasin is chaned fro stron inersion to subthreshold. In addition the alue of 3 / stronly depends on the /I D ratio (where = ) when biasin transistors in the subthreshold reion..3 Analo circuit desin challenes in EEG front-ends Battery-powered portable or iplantable biopotential and bioipedance easureent deices are becoin increasinly widespread in the edical dianostics field. The sinal acquisitions of the ain biosinal-sensin applications such as electroencephaloraphy (EEG) and electrocardioraphy (EG) inole oltae easureents fro a few icroolts to seeral illiolts [8]-[30]. Biopotentials are conentionally acquired usin electrodes coered with electrolyte els or solutions to decrease the contact ipedance at the skin interface to alues below 0 KΩ. Howeer wet-contact easureents cause discofort and dry out in noel lon-ter onitorin applications such as in brain-coputer interfaces where EEG sinals are acquired and analyzed oer hours or loner [3]. In eneral dry electrodes such as inexpensie A/Al are better suited for lonter onitorin but their use is associated with increased contact resistances that can be aboe Ω [3]. This characteristic coplicates the easureent of sall biopotentials in the rane of a few icroolts for EEG applications by requirin ery hih input ipedance at the analo front-end aplifier of at least 500 Ω [33]. Neertheless a sinificant proble is that this ipedance is affected by parasitic capacitances of the interated circuit packae as well as electrode cable and printed circuit board (PB) capacitances that could be as hih as pf at the input of an instruentation aplifier (IA). For instance when the oal is to record EEG sinals with frequencies up 5

16 to 00 Hz an interface capacitance of 00 pf would liit the input ipedance at 00 Hz to approxiately 8 Ω which is uch less than 500 Ω and would cause excessie attenuation such that the EEG sinal cannot be easured reliably..4 ontributions of this research This dissertation suarizes two ain research efforts. In the first part linearization techniques for RF front-end circuits are introduced with diital tunin features to proide copatibility with built-in test and calibration approaches such as the one deeloped at Northeastern Uniersity with Fourier fast transfor (FFT) enines [34]- [35]. Noel linearization ethods for LNAs and ixers biased in subthreshold hae been deonstrated without additional power consuption to oercoe the linearity deficiency. In addition diitally proraable eleents hae also been proposed to counteract the sensitiity to anufacturin process ariations. A test chip with a subthreshold LNA has been fabricated in Donbu 0.µ OS technoloy and easured to deonstrate the feasibility of the desin technique. To obtain additional easureent results for the proof of concept a ixer has been fabricated in Donbu 0.µ OS technoloy and another LNA in IB 0.3µ OS technoloy. In the second project an input ipedance boostin technique for instruentation aplifiers was created which toether with an on-chip test sinal enerator shows proise to enable lon-ter brain sinal easureents. The instruentation aplifier was interated into an analo EEG front-end with on-chip calibration desined by other research roup ebers. This prototype chip was erified with easureents to conclude this dissertation work. The oranization of this dissertation is as follows. The analyses of noralized parasitic capacitances and nonlinearity coefficients based on the /I D ethodoloy are presented in hapter. The nonlinear sall-sinal odels for coon source (S) and coon ate (G) aplifiers are also deried in hapter usin Volterra series analysis. Noel linearization techniques for subthreshold LNAs and ixers are proposed in hapter 3. The input ipedance boostin ethod is presented in hapter 4. onclusions and future work are ien in hapter 5. 6

17 . Subthreshold RF ircuit Analysis and Desin onsiderations In this dissertation the /I D ethodoloy is applied for the noralized estiations of parasitic capacitances and nonlinearity coefficients [36]. Usin the Volterra series approach the nonlinear sall-sinal odel is analyzed to derie the three-order nonlinearity products under consideration of the eory effects fro capacitances and inductances.. /I D ethodoloy onsider the NOS deice confiuration in Fiure 3 where the drain-to-source oltae (V DS ) is fixed and equal to VDD/ and the oerdrie oltae (V OV = V GS - V th where V GS is the ate-to-source oltae and V th is the threshold oltae) is a ariable. In this chapter a 0.3µ OS technoloy and a iniu lenth are used in ealuations. Based on Fiure 3 the basic inforation about I D and parasitic capacitances ( s d and b ) can be extracted by sweepin V OV fro the subthreshold reion to the stron inersion reion. As shown in Fiure 4 the current efficiency ( /I D ) decreases when the bias point chanes fro the subthreshold reion to the stron inersion reion. Accordinly it is a possible option to use circuits biased in the subthreshold reion to sae power. In the followin analyses the /I D ratio is also eployed as a desin reference for parasitics and nonlinearity coefficients. Fiure 3. Basic perforance ealuation setup for an NOS deice. 7

18 Fiure 4. Drain current (I D ) with loarithic scale and current efficiency ( /I D ) s. oerdrie oltae (V OV )... ontribution and distribution of parasitic capacitances As isualized in Fiure 5 the siulated s / ( = s + d + b ) ratio decreases approxiately 0% when /I D is swept such that the bias point chanes fro the stron inersion reion to the subthreshold reion. As a result s no loner doinates in the subthreshold reion. Hence the ate-drain capacitance d and the ate-bulk capacitance b should be taken into account for precise input ipedance atchin calculation and linearity estiation. In addition Fiure 6 shows that the transition frequency f T chanes fro 70 GHz to a few GHz when the transistor bias is aried fro the stron inersion to the subthreshold reion. In the past transistors biased in subthreshold reion were not seriously considered for analo or RF circuit desin because f T was seerely liited [37]. Howeer new OS process technoloies hae sinificantly iproed f T alues which has ade it possible to desin subthreshold circuits with operatin frequencies up to seeral iahertz. 8

19 Fiure 5. ontribution of parasitic capacitances to the total ate capacitance ( ) s. /I D Fiure 6. Transition frequency (f T ) s. /I D... Nonlinearity analysis For a weakly nonlinear aplifier the relationship of the input oltae ( in ) and output current (i d ) can be expressed by the first three power series ters [38] [39] i d 3 in in 3 in () 9

20 where and 3 are the linear ain second-order nonlinear coefficient and third-order nonlinearity coefficient of the aplifier respectiely. Notice that these paraeters can be obtained by takin deriaties of I D with respect to V GS at the D bias point: I D I D V GS! V GS I D 3 3 3! V 3. () Fiure 7 shows the noralized and 3 transconductance characteristics of an NOS transistor in 0.3µ OS technoloy where and 3 are diided by. The plots show that the / ratio is always positie but the sin of 3 / depends on the ode of operation. In the subthreshold reion 3 / is positie and its alue depends stronly on the /I D ratio. GS Fiure 7. Noralized nd-order and 3rd-order transconductance characteristics of an NOS deice.. Volterra series analysis In this section eneral Volterra series analyses of coon-source (S) and coon-ate (G) aplifiers are presented and parasitic capacitances are included for ore accurate perforance estiations. 0

21 .. oon-source aplifier sall-sinal odel Fiure 8 shows the S aplifier and its nonlinear sall-sinal odel where ipedance Z is part of the input atchin network Z is the source-deeneration ipedance and Z 3 is the ipedance connected to the drain of the transistor. R S is the resistance of the sinal source V x. The third-order interodulation intercept point of the transistor can be deried after Volterra series analysis [40]-[4] as IIP 3 6 R H s 3 A (3) where ω is the center frequency of the two interodulation tones at ω RF and ω RF Δω is defined as ω RF - ω RF and R s is the source resistance (that often is 50Ω). H (ω) is the third-order nonlinearity transfer function fro V in to the drain-source current (i d ) A (ω) is the linear transfer function fro the input oltae (V x ) to the ate-to-source oltae (V s ) and ε(δωω) represents the nonlinear contribution fro the second-order and third-order ters. iniization of the ter ε(δωω) in (3) leads to iproed IIP 3. Here the analysis of the ε(δωω) ter is focused on the S and G aplifier staes because they are coonly used in the RF aplifier confiurations of interest as deonstrated by the exaple desins in this dissertation. The ε(δωω) ter of the S aplifier can be expressed as where (4) 3 ob ob (5) 3 j d [ Z Z ] j [ Z Z 3 s j [ j Z ] Z b d 3 (6) Z Z Z j [ j Z ] Z Z b d 3 (7) j Z Z Z Z Z Z ore detailed deriations are included in Appendix A. d Z 3 R s Z (8) i 3 ]

22 Fiure 8. (a) S aplifier (b) nonlinear sall-sinal odel of a S aplifier... oon-ate aplifier sall-sinal odel Fiure 9 depicts a G aplifier and its nonlinear sall-sinal odel where Z ext represents bondin parasitics or an equialent linearized coponent. Note that Z in this case odels the ipedance of the sinal source at the source of the transistor. The followin equations ie insihts into the linearity of the G aplifier. Usin Volterra series [4] analysis the aplitude at the third-order interodulation intercept point (A IIP3 ) of the G aplifier can be deried as 4 A. (9) IIP3 3 3 H A The definition of ε(δωω) is the sae as in (3) and can be rewritten as (0) 3 ob where ob () 3 j Z d 3 j j [ j Z ] Z s d Z Z s d 3 () j Z Z The linear transfer function A (ω) in equation (9) is deried in Appendix B. d 3 d 3 Z. (3) _ ext Z // j b

23 Fiure 9. (a) G aplifier (b) nonlinear sall-sinal odel of a G aplifier. 3

24 3. Linearization of Low-Power RF Frond-End ircuits Perpetual proress with interation of oice ideo and internet features on chips is a hallark of the inforation ae that requires sall low-power interated circuits. Portable wireless deices continue to be ore prealent in our lies so that ital situations depend on reliable operation of interated circuits. onsequently there is an increasin incentie to incorporate self-test and correction features to iproe reliability of wireless deices. This is especially true in edical and ilitary applications where life-sain inforation is transitted and receied. Althouh new technoloies allow the desin of saller chips with ore functionality their anufacturin process ariability and post-production ain effects pose rowin desin and test challenes. Therefore the deelopent of adaptie sinle-chip systes is essential for hih reliability in odern nanoeter copleentary etal-oxide-seiconductor (OS) technoloy. For this reason the analo circuit and desin techniques introduced in this dissertation include the use of diitally tunable eleents to enable on-chip calibrations after fabrications of the chips. The ost widely used IIP3 iproeent ethods for RF frond-end circuits in narrowband applications can be broadly diided into three cateories. The first coon approach is to use the neatie feedback topoloy that can reduce IIP3 by a factor of (+T 0 ) 3/ where T 0 is the linear open-loop ain if 0 [39]-[40]. The second ethod is to use one or two auxiliary transistors biased in the weak inersion reion to cancel the third-order nonlinearity coefficient ( 3 ) but the ain transistor has to be operated in stron inersion with hiher linear transconductance ( = ) than in the auxiliary path [39]-[4]. The third way is to operate the ain transistor between the oderate inersion and subthreshold reions for findin the optiu bias zone [40] [63]. Howeer linearization ethods hae not yet been reported with easureents of RF aplifiers usin only transistors biased in the subthreshold reion. 3. Input ipedance atchin optiization for low-power low-noise aplifiers Handheld battery-powered consuer products with wireless connectiity such as cellular phones wireless edical onitorin deices and lobal positionin syste 4

25 (GPS) receier units continue to require power consuption reductions. Eerin receier applications in wireless sensor networks wireless body area networks [43]- [44] and enery harestin ipose een ore strinent deands on the perissible power dissipation. Furtherore any reported built-in test and calibration approaches rely heaily on diital sinal processor resources to achiee ore robust diitallyassisted analo circuits [46]-[50]. For such applications the construction of analo circuits with features for perforance tunin is needed. A sinificant aspect of eerin ariation-resilient desin ethods is that bias oltaes or currents are enerated with diital-to-analo conerters or proraable eleents which can be utilized to iproe the reliability of nanoeter OS systes-on-a-chip [5]. Preiously reported diitally-assisted perforance boostin techniques hae tareted arious blocks in the receier path for which a few exaples are the tunin of transconductance alues in baseband filters [5] third-order linearity in baseband filters [53] second-order linearity of ixers [54] and ain of low-noise aplifiers (LNAs) [55]. 3.. LNA input ipedance analysis and tunin ethod 3... Deriation of equations for ipedance atchin The input ipedance of the conentional cascode LNA in Fiure 0 can be deried as [56] Z in L j ( L L ) L ( at resonance ) s s T s (4) s s where ω T = / s is the transition frequency and the couplin capacitor B is oitted under the assuption that its alue is lare. The real part of the input ipedance can be expressed under consideration of the ate-drain capacitance [56]: Re[ Z in ] R s L T ( s d s ) (5) where R s is the input oltae source (e.. antenna) resistance to which Re[Z in ] should be atched. 5

26 In this work the followin additional paraeters were considered to analyze the input ipedance: d (parasitic ate-drain capacitance) b (parasitic ate-bulk capacitance) ds (parasitic drain-source capacitance) r o (sall-sinal drain-source resistance) b (body effect transconductance) and r (ate resistance). The sall-sinal equialent circuit of transistor is displayed in Fiure. To siplify the ipedance analysis at the source terinal of the sall-sinal odel can be odified as in Fiure when the alue of r is relatiely sall. d d in Fiure is the output iller capacitance while b and the input iller capacitance of d at the ate hae been reoed because they are rounded at both terinals when r is neliible. Thus the ipedance at the source terinal of can be written as Z Z Z o D (6) ( Z Z ) s G Z ) ( o D s o where: Z r // o o s ds Z D Z // D s d Z D R d // sl d // s L and G b. I BIAS L d R d out B d R BIAS I D R S B L in L s Fiure 0. onentional cascode LNA with inductie source deeneration. 6

27 r d + b s s s b s Z o Z D - s Z Fiure. Sall-sinal odel of transistor s G s Z o Z D d s Z Fiure. Siplified sall-sinal odel of transistor. An analysis of the LNA input stae with consideration of d can be perfored by takin the iller effect (Fiure 3) into account. Therefore the total equialent capacitances fro the ate and drain terinals of transistor to round can be calculated as F (7) ( A ) d b B ( ) d. (8) A The oltae ain A in the aboe equations can be deried as A G Z (9) eff out where G -eff and Z out are proided in Appendix. 7

28 d -A F B Fiure 3. A eneral odel of the iller effect related to transistor. Z in Z in L r F s + s - s s b s Z o Z B L s Fiure 4. Siplified equialent circuit of Fiure 0. A coplete analysis of the input ipedance Z in ies Z in sl r Z // in. (0) s F Typically Z o (Fiure 4) and Z o (Fiure ) are sinificantly larer than the other ipedances in the sall-sinal odels under consideration. Assuin that Z o and Z o are at least one order of anitude larer than the related ipedances the followin approxiations can be ade: Z () G G s L s s b s () eff d ( sl s ( b s s )) 8

29 Z Z // out (3) s d Z ' sl L. (4) in s s s s s At resonance L s should be selected properly such that the real ter of Z in is equal to R s - r.voltae ain A is a coplex nuber which coplicates hand calculations. A atlab script to calculate L s and L is proided in Appendix D. Note that off-chip bondin wire and packae parasitics were excluded fro the analysis for siplicity but the equations could be adapted to include the. Nonetheless the equations are intended to aid the initial desin and optiizations rather than to replace coprehensie circuit siulations with odels for off-chip parasitics S tunin capability Tunin of input ipedance atchin is desirable to copensate for anufacturin process ariations. Such as other on-chip S built-in test [57] and self-calibration [58] ethods the proposed input ipedance tunin ethod is particular for the LNA block. Howeer the diitally-assisted tunin feature to be discussed in this section can also be utilized as part of a syste-leel calibration that is controlled by the diital sinal processor of an interated receier. Based on the presented input atchin equations a S -tunable circuit usin an n-bit etal-insulator-etal (I) capacitor network (shown in Fiure 5) can be ipleented to optiize the input ipedance atchin under the influence of ariations. Node G in Fiure 5 is connected to the ate terinal of transistor in Fiure 0. After this odification the input ipedance Z in with capacitance I can be expressed as Z in sl //( r Z // ) in (5) s s I F where I is the contribution of the n-bit I capacitor. Note that the diitallyassisted tunin of I allows direct copensation of the effectie input iller capacitance F in equations (7) and (0) which is ore sensitie to ariations of parasitic 9

30 transistor capacitances when subthreshold biasin is used. Thus the inclusion of a proraable I capacitance fro the ate of to round is ore appropriate in subthreshold desins than the custoary tunin (when is biased in stron inersion) of an additional capacitance in parallel with s. The tunin rane of I can be decided based on anticipated ariations fro siulations with deice corner odels. In the discussed exaple desin a 5-bit binary-weihted proraability is sufficient as deonstrated by the siulation results in Section 3... In the discussed exaple desin the axiu and iniu capacitance alues occur with D 5 D 4 D 3 D D = [] and [00000] respectiely where indicates that the ate of the transistor connects to the supply oltae and 0 desinates that the ate is rounded. Alternatiely analo tunin capability could be realized usin a OS aractor siilar to the S tunin ethod in [59] but with the difference that the aractor ( I ) would be connected fro the ate of in Fi. directly to round instead of to the source of as in [59]. Howeer the linear tunin rane with a OS aractor at the input is ore liited than with a bank of I capacitors. G In... I I Dn D n D D D D Fiure 5. Scheatic of the n-bit capacitor network for S copensation. 3.. Siulation results 3... Validation of the input ipedance atchin equations To copare the proposed siplified equations with the conentional approxiations the LNA in Fiure 0 was desined in 0.8 µ OS technoloy. adence Spectre siulations were perfored to ealuate the accuracy of the equations that were 30

31 used to calculate the inductances L and L s required for atchin at.4 GHz with a transconductance ( ) of equal to 0 S. Fiure 6 shows the siulated alues of the frequency at which S is atched (left y-axis) toether with the correspondin iniu S alue (riht y-axis) for different operatin conditions ( /I D ratios) fro the stron inersion reion to the subthreshold reion. Since the /I D ratio chane requires a different channel width/lenth ratio for in order to aintain the sae alue each desin point on the x-axis in Fiure 6 leads to different parasitic capacitances. When usin the proposed siplified equations ()-(4) to calculate L and L s the siulated atchin frequencies and their correspondin iniu S alues are close to.4 GHz and below -0 db for all cases. With the conentional equations (4) and (5) the atchin frequencies ( GHz) deiate fro the desired.4 GHz and the correspondin S alues are below -5 db as the operatin point is chaned fro the stron inersion reion to the subthreshold reion. The results in Fiure 6 deonstrate that the proposed equations predict the input ipedance ore accurately especially in the subthreshold reion where effects fro parasitic capacitances becoe ore influential. The siulation results in Fiure 7 were obtained by aryin of fro 7 S to 3 S while aintainin a constant /I D ratio equal to such that the LNA operates in the subthreshold reion. The purpose of this assessent is to erify whether the atchin frequency prediction is also alid for different transconductance alues of. Usin the proposed equations to select L and L s the siulated atchin frequencies and their associated S alues in Fiure 7 are around.43 GHz and below -8 db respectiely. In coparison when calculatin the inductance alues with the conentional equations the atchin frequencies at which S is below -8 db are around.6 GHz which is sinificantly further away fro the.4 GHz taret. 3

32 Fiure 6. Input ipedance atchin coparison between conentional and proposed equations for different operatin reions. Fiure 7. Input ipedance atchin coparison between conentional and proposed equations for different transconductance alues of Tunin capacity Table contains the key desin paraeters of the reference LNA and the tunable LNA operatin at.4 GHz while biased in the subthreshold reion. Both LNAs were desined with the topoloy in Fiure 0 to achiee alost identical specifications with siilar coponent alues. An additional 78 ff I capacitor (extra s ) was added between the ate and source terinals of in the reference LNA to obtain coparable 3

33 oerall perforance for both desins with a siilar quality factor in the atchin network. In this exaple desin the extra capacitance deraded the siulated noise fiure by less than 0.3 db. The tunable LNA was desined with a 5-bit binary-weihted capacitance where the capacitor for the sallest bit is 0 ff. Therefore I aries fro 0 ff to 60 ff as the control word (D 5 D 4 D 3 D D ) is chaned fro [00000] to []. A fine resolution was selected in this exaple to deonstrate the tunin capability of the ethod. Dependin on the S requireent a shorter control word could be used if only coarse tunin is needed. The layouts of both LNAs are shown in Fiure 8 and Fiure 9 reealin that the occupied die area increased fro 0.4 to 0.45 to allow tunin. Post-layout siulation results (with extracted parasitics) for the two LNAs are listed in Table 3 which suarizes different scenarios that include specification paraeters with different deice corner odels power supply ariation teperature ranes as well as L s and L ariations. Pads bondin wires (L bond ) and QFN packae parasitics ( pack ) at the input/output pins were odeled with 0 ff nh in series with. Ω and 60 ff respectiely [60]. In the typical corner case with.8 V supply at roo teperature the siulated specifications of the two LNAs are coparable. For breity Table 3 only includes soe additional cases with seere ariations to deonstrate the tunin feature. In the third siulation condition for instance the LNA tunin iproes S by 8.7 db and the linearity paraeters by ore than 3 db in coparison to the reference desin but at the expense of 0.9 db S reduction with a noise fiure increase of 0.9 db due to the slihtly lower quality factor after tunin. On the contrary in condition 5 the tuned LNA has a. db hiher S with 0.9 db noise fiure iproeent and slihtly better linearity. But under condition 5 the S paraeter of the reference LNA is only -7.6 db whereas S of the tuned LNA is -6. db. If the S recoery requires a hiher I alue as for the third siulation condition in Table 3 then the tunin could cause a slihtly lower S and NF copared to the reference LNA due to the lower quality factor in the input atchin network. A syste-leel calibration schee should take this atter into account. Instead of tunin for optiu S reardless of the oerall perforance the I alue should be adjusted as part of the syste-leel calibration after it has been deterined that the specifications are not et with the default I alue. In suary 33

34 the proposed tunin ethods enables to recoer fro seere S deradations while aintainin the other specification paraeters within acceptable ariation liits copared to the reference LNA desin. Table 4 suarizes the perforance paraeters in coparison to those of other reported LNAs based on the fiure of erit (Fo) defined in [6]. The LNAs in [6] and [6] are operatin with transistors in stron inersion and the others include transistors biased in the subthreshold reion. The results indicate that the proposed tunable LNA achiees the hihest Fo aon subthreshold desins with the exception of [68] where three nh inductors are eployed. Howeer the P db NF and Fo of the tunable subthreshold LNA with 0.55 A drain current are not as ood as the sae specifications with stron inersion biasin. For exaple the desin in [6] with a drain current of. A has a hiher Fo. Table. Desin paraeters of the reference LNA and tunable LNA Key coponent alue Reference Tunable L s [nh] L [nh] Extra s [ff]* 78 N/A R d [Ω] L d [nh] d [ff] W/L per finer ( and B ) [μ/μ] 5/0.8 5/0.8 Nuber of finers ( and B ) I D [μa] V dd [V].8.8 Layout area (0.8 µ OS) [ ] * Parasitic s + extra s = 385 ff 34

35 685μ V in 830μ V DD V out Itail 50μ GND 80μ Fiure 8. Layout of the reference LNA. 690μ V in 860μ V DD V out I tail D 5 D 4 D 3 D D GND 530μ 70μ Fiure 9. Layout of the tunable LNA. 35

36 Table 3. Post-layout siulation coparison of the reference LNA and tunable LNA at.4 GHz Reference LNA Tunable LNA ondition : TT odels 7 o V dd S [db] [000] S [db] NF [db] P db [db]* IIP3 [db] ondition : FF odels 85 o +0% V dd S [db] [0] S [db] NF [db] P db [db]* IIP3 [db] ondition 3: FF odels 85 o +0% V dd -5% L s -5% L S [db] [00] S [db] NF [db] P db [db]* IIP3 [db] ondition 4: SS odels -40 o -0% V dd S [db] [00] S [db] NF [db] P db [db]* IIP3 [db] ondition 5: SS odels -40 o -0% V dd -5% L s +5% L S [db] [000] S [db] NF [db] P db [db]* IIP3 [db] ondition 6: SS odels -40 o -0% V dd -5% L s +5% L +5% L bond -5% pack S [db] [0000] S [db] NF [db] P db [db]* IIP3 [db] * Defined as the point where the ain chanes by db. (Gain expansion occurs when P in > P db in this circuit leadin to increased ain but non-linear operation.) 36

37 Table 4. Tunable LNA perforance coparison with other published results Reference Gate lenth (μ) f c (GHz) S (db) Gain (db) P -db (db) NF (db) V DD /I D (V/A) Fo (Hz) Reference LNA* / (OS) Tunable LNA* / [6]** [6]** [68]** [4]** [7]** [6]** N.A. (SiGe) 0.8 (OS) 0.8 (OS) 0.3 (OS) 0.8 (OS) 0.8 (OS) * Siulation result ** easureent result / / / / / / onclusions A coprehensie input ipedance analysis for OS inductor-deenerated coon-source LNAs operated in the subthreshold reion has been presented. Siulation results reealed that the equations perit hihly accurate calculation of the required ate and source inductance alues for ipedance atchin under the influence of lare parasitic capacitances. In addition an input ipedance tunin ethod was proposed that inoles a proraable capacitance to proide diital calibration control. Siulations of a tunable.4 GHz LNA desin and a coensurate reference LNA were perfored with corner deice odels teperature ariations supply oltae ariations and odels for off-chip bondin and packae parasitics in order to ealuate the effectieness of the S tunin and to erify that it does not cause any sinificant perforance deradation of other specification paraeters. The results showed that the tunin technique leads to 8.5 db or ore S iproeent copared to the reference LNA desin. 37

38 3. Proposed low-noise aplifier desin techniques Fiure 0 shows the scheatic of the proposed LNA where inductor L and diitally-proraable capacitor d_ext can iproe the IIP3 in the presence of ariations. Inductor L inductor L buffer and capacitor buffer are off-chip coponents for ipedance atchin purposes. d_ext is ipleented with a fixed etal-insulator-etal (I) capacitor ( d_ext0 ) and a 3-bit diitally-proraable I capacitor ( d_ext d_ext and d_ext3 ) as illustrated in Fiure. Preliinary siulations showed that OS capacitors can also be eployed to realize d_ext but resultin in slihtly increased LNA ain ariation and less linearity iproeent copared to etal-insulatoretal capacitors. All passie deices (with frequency-dependent quality factor liitations) and actie deices were siulated usin foundry-supplied odels. In this section the bondin/packae parasitics and buffer stae were nelected to siplify the sallsinal analysis. It has been shown in [64] that an inductor between the ate of the cascode transistor and the power supply can iproe stability of a coon-source cascode LNA by creatin a sharp notch in the transfer function of the reerse isolation (S) around the operatin frequency. In another related work [4] a fully differential coon-source LNA topoloy with an inductor at the ate of the cascode transistor and a cross-couplin capacitor between the ate of the cascode transistor and the source of the opposite cascode transistor was introduced to decrease the noise fiure iproe the linearity and enhance the oltae ain. Neertheless this LNA was biased in the stron inersion reion. The linearization ethod described in the next subsection was deeloped for subthreshold coon-source cascode LNAs and does not require crosscouplin for nonlinearity cancellation. 38

39 Fiure 0. Linearized subthreshold LNA. Fiure. Diitally-proraable capacitor ( d_ext ) for linearity tunin. 39

40 3.. Analysis and desin of the linearized LNA 3... Linearity analysis In this linearity analysis the input stae (transistor ) and cascode stae (transistor ) of the proposed LNA in Fiure 0 are split into two indiidual parts. Fiure shows the nonlinear sall-sinal odel of the input stae where the extra etalinsulator-etal capacitor ( s_ext ) is luped into the parasitic capacitance s. The IIP3 of transistor can be deried after Volterra series analysis (as in Section..): IIP (6) R H A s where ω is the center frequency of the two interodulation tones at ω RF and ω RF Δω is defined as ω RF - ω RF and R s is the antenna ipedance of 50Ω. H (ω) is the thirdorder nonlinearity transfer function fro V in to the drain-source current (i d ) of A (ω) is the linear transfer function fro the input oltae (V x ) to the ate-to-source oltae (V s ) and ε (Δωω) represents the nonlinear contribution fro the secondorder and third-order ters of transistor. iniization of the ter ε (Δωω) in (6) leads to iproed IIP 3. For this reason we will now exaine the ε (Δωω) ter for transistors and. The ε (Δωω) ter of can be expressed as 3 ob (7) where ob (8) 3 j d [ Z j [ j Z ] Z b d 3 (9) Z Z Z ] j [ Z Z 3 s Z j [ j Z ] Z Z b d 3 (30) j Z Z Z Z Z Z d Z 3 R j L s (3) jl s Z (3) 3 ] 40

41 Z 3 j d Z 3 j [ j j Z ] Z s d s d 3 (33) [ j ] [ Z Z ] s Z Z d d s j L j (34) // b R // jl j. (36) // 3 d d The parasitic capacitance b was included aboe to further iproe the accuracy of the analysis for which ore detailed deriations are included in Appendix A. The ariables and 3 are the linear ain second-order nonlinearity coefficient and third-order nonlinearity coefficient of transistor respectiely. d 3 Fiure. Nonlinear sall-sinal odel of the LNA s input stae with. Fiure 3 depicts the nonlinear sall-sinal odel of the cascode stae where the extra etal-insulator-etal capacitor d_ext is ered with the parasitic capacitance d. A cascode deice whose ate is connected to an A round typically only has a sall ipact on the oerall linearity of a cascode coon-source LNA. On the other hand the cascode stae with additional coponents at the ate of in Fiure 0 has a sinificant ipact on the oerall linearity perforance. The followin equations ie insihts into the linearity effect of the cascode deice which has not yet been clearly analyzed in the literature for the subthreshold topoloy in Fiure 0. Usin the Volterra series analysis ethod in Section.. the aplitude at the third-order interodulation intercept point (A IIP3 ) of transistor can be deried as 4

42 4 A. (37) IIP3 3 3 H A The definition of ε (Δωω) is the sae as in equation (7) and can be rewritten as 3 ob (38) where ob (39) 3 j d Z Z s d 3. (40) j Z Z j j [ j Z ] Z s Z 3 d d The linear transfer function A (ω) in equation (37) is deried in Appendix B. Paraeters and 3 are the linear ain second-order nonlinear coefficient and third-order nonlinear coefficient of. d 3 3 Fiure 3. Nonlinear sall-sinal odel of the LNA s cascode stae with. In addition to the nonlinearity cancellation analyzed aboe a secondary echanis leads to linearity enhanceent thanks to the extra coponents at the ate of. Fiure 4(a) displays the siulated oltae ain fro V in to V y (in Fiure 0). In Fiure 4

43 4(a) the LNA with L = 3.5 nh and d_ext = 50 ff has lower oltae ain (V y /V in ) than the conentional cascode coon-source LNAs. Hence the attenuation due to L and d_ext contributes to linearity iproeent by preentin that transistor liits the IIP3 perforance. Fiure 4(b) isualizes the nuerical calculations of ε (Δωω) ersus L for three alues of d_ext based on the aboe equations. In this desin the cascode stae dictates the oerall linearity due to the V s oltae swin boostin effect that is eident fro the equations in Appendix B. onsequently an L alue around 3.5 nh leads to optiu IIP3 in this exaple. While the aboe equations proide a theoretical foundation for the proposed linearization technique in practice a desiner can select a reasonable d_ext alue and sweep L in circuit siulations. A standard IIP3 etric can be onitored durin the siulations in lieu of the ε (Δωω) ter. The related reerse isolation (S) and stability aspects for the selection of L and d_ext alues are discussed in Section

44 (a) (b) Fiure 4. (a) Siulated oltae ain fro V in to V x of the LNA with and without L and d_ext (ideal coponents) and (b) calculated results of ε(δωω) for L with three d_ext cobinations in the cascode stae (with ). 44

45 3... Voltae ain The oltae ain of the linearized LNA can be separated to identify the contributions associated with the transistors and. In Appendices A and B the linear transfer functions fro V x to V 3 (in Fiure ) and fro V to V 3 (in Fiure 3) are deried which represent the frequency-dependent oltae ains (ω) and (ω) of the two staes. Fro equations (A.0) and (B.0) these oltae ains can be cobined to deterine the oerall LNA ain: A. (4) Input atchin network The input atchin of a subthreshold coon-source LNA was analyzed in [65] without inductor L. For the odified LNA (with linearization) presented in this section it can be shown that the input ipedance under consideration of the extra coponents can be estiated as where Z Z in * j L Z // ; (4) in j F s j L (43) * in j s s L s F A d b (44) G A G Z (45) eff 3 j (46) eff d j L ( s j and Z 3 (ω) is defined in equation (33) Noise The noise factor analysis for the subthreshold coon-source LNA with inductie source deeneration has been reported in [66] with the followin result: s ) 45

46 R n V o s T s s F Q c in (47) t I 5 5 D t t where t = s + s_ext ω 0 is the operatin frequency γ and δ are the channel and ate noise coefficients α = / d0 d0 is the channel conductance with zero drainsource oltae V T is the theral oltae Q in is the quality factor of the input atchin network and c is the correlation paraeter between the ate and channel noise currents Reerse isolation and stability opared to conentional coon-source cascode LNAs the proposed linearization ethod requires an inductor at the ate of the cascode transistor. As described in [64] the reerse isolation of such an LNA can be iproed in the desired frequency band with proper sizin of the inductor at the ate of the cascode transistor. To analytically estiate the ipact on reerse isolation the transfer function fro V out_lna to V y in Fiure 0 can be deried fro the sall-sinal circuit in Fiure 5: H ( s) 3 V y s b s b 0 (48) 3 V a s a s a s a out _ LNA 3 0 where a 3 = + b / d a = (r o +Z + r o Z )/( s r o Z )+(r o +Z )/( d r o Z )+ b (+ r o +r o /Z )/( s d r o ) a = /( d L ) a 0 = (+ r o +r o /Z )/( s d r o L ) b = /( s r o ) + /( d r o )+ / s + b /( s d r o ) b 0 = /( s d r o L ) r o is the drain-source resistor of transistor and Z is the equialent ipedance lookin into the drain of transistor. Note that L and d_ext hae to be chosen properly for enhanced reerse isolation in the desired frequency band. 46

47 Fiure 5. Siplified sall-sinal odel for reerse isolation analysis of transistor. The stability factor of the LNA is defined in [4] and [64]: K S S (49) S S where Δ = S S S S. The unconditional stability requireent is K > and Δ <. Note that S and S are close to zero when the input and output of the LNA are atched to the source and load ipedances. Based on the easured S-paraeters (LNA and buffer cobination) presented later in this chapter the alue of Δ is less than and the alue of K is ore than in the frequency rane fro 0. GHz to 8.5 GHz. The Δ and K alues are 0.05 and 7.67 at.8ghz respectiely. Fro LNA siulations without buffer the reerse isolation at.8 GHz with L = 3.5 nh and d_ext = 50 ff is slihtly better (-9.7 db) than without L and d_ext (- 7.4 db). As S decreases the alue of K increases and Δ decreases resultin in iproed stability. Howeer it is iportant to consider that the alues of L and d_ext can derade reerse isolation and stability if they are not carefully selected. If L and d_ext becoe too lare then the peak of the transfer function in equation (48) oes fro hiher to lower frequency which can cause a stability proble. 3.. LNA easureent results A.8 GHz linearized subthreshold LNA has been desined and fabricated in Donbu 0.µ OS technoloy. Fiure 6 displays the chip icroraph of the LNA with an area of 80 µ 770 µ. The L alue of this desin was selected to be 47

48 3.48nH (with a quality factor of 6.5 at.8 GHz) and final post-layout siulations were perfored with foundry-supplied deice odels for all on-chip coponents. As shown in Fiure 7 the prototype chip was bonded to a conentional QFN6 packae that was assebled on a printed circuit board (PB) for easureents. Fiures 8 9 and 30 show the easureent setups for S-paraeters the two-tone test and noise characterization respectiely. Table 5 lists the key desin paraeters of the LNA. It consues a 480 µa current (with exclusion of the buffer) fro a 0.7 V power supply instead of the noinal. V supply oltae for this technoloy. In order to liit the linearity deradation due to the output buffer that was desined to test the LNA a. V supply is used for the buffer. Table 5. Linearized subthreshold LNA desin paraeters oponent VALUE V DD 0.7 V I D 480 µa /I D S/A L L L s s_ext d_ext03 L d d R d W/L per finer ( ) 7.5 nh 3.5 nh.4 nh 30 ff 70 ff/ 0 ff/ 40 ff/ 80 ff 6.4 nh 88 ff 70 Ω 6µ / 0.3µ Nuber of finers ( ) 64 48

49 Fiure 6. hip icroraph of the fabricated linearized subthreshold LNA in Donbu 0.µ OS technoloy. Fiure 7. LNA PB with IIP3 tunin functionality. 49

50 Fiure 8. Setup for S-paraeter easureents. Fiure 9. Two-tone test setup. 50

51 Fiure 30. Setup for noise easureent Perforance The control switch settins for d_ext of D 3 D D = 00 resulted in the best linearity after fabrication process ariations. Fiure 3 shows the easured scatterin paraeters of the linearized subthreshold LNA. S and S are both below -0 db at.8 GHz. The easured oltae ain of 9.5 db at.8 GHz is the cobination of the LNA and buffer. Also note that S is under -40 db around the frequency of interest. Fiure 3 displays the plot of the easured noise fiure (NF) that is 6.3 db at.8 GHz with the buffer. The oltae ain and noise fiure of the LNA are 5. db and 3.8 db after de-ebeddin the effects of the buffer stae loss SA cables and power cobiner. As part of the de-ebeddin process the siulated ain and noise fiure of the LNA and buffer cobination were copared to the easureent results. The oerall noise fiure was within 0.9 db which supports that the easured LNA ain is at least 5. db because any sinificant reduction of the LNA ain would sinificantly derade the oerall noise fiure of the cobined LNA and buffer staes. Notice that the -5.9 db ain of the buffer in Fiure 0 is in the presence of parasitics due to the bondin the interated circuit packae and the PB at the interface to the easureent equipent with 50Ω terination. 5

52 Fiure 33 shows the easured IIP3 of the LNA and the output spectru fro a test with a two-tone input sinal (.8 GHz and.7995 GHz) and an input power of -35 db. Fiure 34 contains the plot of output power easureents fro a power leel sweep of a sinle.8 GHz tone to deterine the -db copression point (P db ) of the LNA. The IIP3 and P db of the linearized LNA are -3.7 db and -.6 db respectiely. Table 6 suarizes the perforance of narrowband low-power RF LNAs with operatin frequencies ranin fro to 3 GHz in coparison to the presented desin. ost of the reported low-power LNA easureent results reeal that the IIP3 is constricted to below -0 db except in this work as well as in [63] and [68]. The linearized LNA fabricated with Donbu 0.µ OS technoloy is listed as work in Table 6. Fiure 35 shows the scheatic and chip icroraph of the other linearized LNA that was fabricated with IB 0.3µ OS technoloy and is listed as work in Table 6. As displayed in Fiure 35(a) the LNA was desined with a source follower buffer. The fiure of erit (FO) fro [67] is used here which is defined as 0 lo{(ain IIP3 f c )/[(NF-) P D ]}. opared to this work with packaed chip easureents at.8ghz on a printed circuit board the GHz LNA in [68] was easured on a probe station. Furtherore the desin in [68] contains a sinle transistor and three nh inductors. Een thouh the cascode stae of a subthreshold LNA has neatie ipact on linearity as discussed in Section 3... we opted to include the cascode transistor to aintain adequate reerse isolation (S ) in this work with linearization enhanceent. On a different note reardin Table 6 the work in [63] is a ood indicator for the stateof-the-art in low-power LNA desin because this recently published fully differential LNA was desined in 90n OS technoloy and easured on a probe station. 5

53 Fiure 3. easured scatterin paraeters of the linearized LNA with buffer (5.9dB loss). Fiure 3. easured noise fiure of the linearized LNA with buffer. 53

54 (a) (b) Fiure 33. (a) easured IIP3 of the linearized LNA with buffer (b) output spectru fro a test with two tones at.8 GHz and.7995 GHz and an input power of -35 db. 54

55 Fiure 34. easured -db copression point of the linearized LNA with buffer at.8 GHz. 55

56 (a) (b) Fiure 35. Linearized subthreshold LNA in IB 0.3µ OS technoloy (a) scheatic and (b) chip icroraph. 56

57 Table 6. oparison of LNA easureent results WORK * WORK * [3] [4] [5] [6] [63] # [68] f c [GHz] Gain [db] NF [db] IIP3 [db] P db [db] n/a -0. P D [W] Tech. [n] Area [ ] 0.64 $ 0.4 $ 0.77 $ 0.63 $ $ $ FO [db] * after de-ebeddin the effect of the buffer # fully differential structure $ without pads with pads 3... IIP3 tunability The iniu and axiu capacitance alues of d_ext (in Fiure ) of the LNA in Donbu 0.µ OS technoloy occur with D 3 D D = [] and D 3 D D = [000] where and 0 indicate that the switch is connected to V DD or round respectiely. Table 7 lists the eiht different capacitance cobinations with the correspondin easureent results of ain and the third-order interodulation distortion (I3) when two tones at.8 GHz and.7995 GHz were applied with an input power of -35 db. The results indicate that chanin d_ext fro 70 to 0 ff has a inor effect on the ain while perittin to diitally tune for optiu third-order linearity perforance. Fiure 36 isualizes the IIP3 s. tunin code fro siulations and easureents with different d_ext capacitance alues. In suary the easured results deonstrate the feasibility of the proposed technique to boost the IIP3 to achiee state-of-the-art oerall LNA perforance under consideration of the key paraeters in Table 6. 57

58 Table 7. Gain and third-order interodulation distortion of the subthreshold LNA in IB 0.3µ OS technoloy for all linearity tunin settins ode [D 3 D D ] d_ext [ff] Gain* [db] I3 [dbc] with -35dB input power * after de-ebeddin the effect of the buffer Fiure 36. IIP3 s. d_ext coparison (siulation s. easureent results) onclusion A.8 GHz subthreshold LNA with an IIP3 enhanceent technique was desined analyzed and fabricated in Donbu 0.µ OS technoloy. The proposed linearization ethod inoles extra passie coponents to accoplish partial cancellation of 58

59 third-order nonlinearity products. It does not require any auxiliary aplification circuitry that would increase the power consuption. Therefore the presented linearization technique is well-suited for low-power applications. easureent results of the W LNA on the prototype chip deonstrated an IIP3 of -3.7 db a oltae ain of 5. db and a noise fiure of 3.8 db. The other. GHz subthreshold LNA with an IIP3 enhanceent technique was fabricated in IB 0.3µ OS technoloy. easureent results of the 0.3 W LNA on the prototype chip deonstrated an IIP3 of 0 db a oltae ain of 9 db and a noise fiure of 5.8 db. 3.3 Proposed ixer desin techniques The third-order interodulation intercept point (IIP3) of ixers in RF receier paths is a critical desin specification because the ixer IIP3 is scaled down by the 0-0 db low-noise aplifier (LNA) ain durin the calculation of the syste s inputreferred IIP3 [69]. An IIP3 below -0 db has been the nor for preiously published subthreshold actie ixers [7] and [70] akin it difficult to eet the IIP3 requireent for low-power wireless standards such as IEEE (ZiBee) [7]. Soe linearization ethods for ixers are aailable such as those in [7]-[73] but the ain transistors ust be biased in stron inersion. Furtherore these linearization ethods require auxiliary actie circuits for IIP3 enhanceent which leads to increased power consuption. In our preious work [74] the IIP3 of a subthreshold cascode LNA with additional passie deices was iproed by oer 0 db copared to a coensurate LNA. Based on a siilar concept this ethodoloy introduces an IIP3 enhanceent technique for subthreshold actie ixers with extra passie coponents to iniize the power consuption Analysis and desin of a linearized ixer The capacitie cross-couplin G -boostin technique is widely used for fully differential coon-ate LNAs (G-LNAs) [75]-[78]. This technique can siultaneously iproe the noise and reduce the bias current for a differential G-LNA. In [4] an inductor connected at the ate of the cascode transistor and a cross-couplin capacitor between the drain of the ain transistor and the ate of the cascode transistor were used 59

60 to reduce the noise and to iproe the linearity of a differential cascode coon-source LNA (S-LNA). In [77] and [79] the capacitie cross-couplin technique has been eployed in ixers with transistors operatin in stron inersion. The concept was applied to coon-ate RF staes in order to iniize noise and to iproe linearity. Howeer the input ipedance with these desin techniques is typically uch lower (~ /[ RF ]) than that of a ixer with a coon-source input stae. For instance in case an LNA with a hih output ipedance is connected to a linearized coon-ate ixer then a power-consuin buffer stae should be inserted to drie the ixer. Fiure 37 shows the scheatic of the proposed ixer [80] where inductor L inductor L and capacitor c enable IIP3 iproeent. The transconductance staes ( ) and switches ( ) are biased in subthreshold which increases the oltae headroo as a result of the low drain-source oltae oerdrie requireent. Transistors 3 and 6 are drien by LO+ while 4 and 5 are drien by LO- where LO+ and LO- are anti-phase sinals. Fiure 38 shows the sall-sinal odel of the ixer under the assuption that the sinals at LO+/LO- are lare enouh to odel 3-6 as switches. Based on siulations it is desirable to operate 3-6 in deep subthreshold to iproe the transconductances ( 3-6 ) of these switchin transistors. The parasitic capacitances at their sources are taken into account in the sall-sinal odel. The drain-to-source resistances (r ds3 - r ds6 ) of 3-6 are nelected in this analysis because they are uch larer than Z load = R out //(jω RF out ) -. Since the sall-sinal odel in Fiure 38 is a fully syetric circuit it can be siplified further with the equialent half-circuit shown in Fiure 39(a). The current suation equations for nodes and in Fiure 39(a) are RF d j ( ) j ( ) (50) RF d d s RF c d s Z ( 3 s j ) j ( ) RF s s RF c d (5) j L s RF where Z 3 ( j RF ) j RF L 3 j RF ( s 3 s 4 ) is the transconductance of d and s are the parasitic ate-to-drain and ate-to-source capacitances of respectiely and 3 = 4 = 5 = 6. Note that Z 3 is independent of Z load in this 60

61 analysis since r ds3456 >> Z load for RF frequencies and r ds3456 >> / 3. After replacin s by ( RF / - s ) equations (50) and (5) can be rewritten as RF ( j ) ( j ) ( j j ) RF d RF c s RF d RF c Z 3 d (5) ( j RF s ) RF j RF c d ( j RF s j RF c ) s. (53) j L RF Throuh rearraneents of equations (5) and (53) the transfer function K(jω RF ) fro s (jω RF ) to d (jω RF ) can be expressed as in equation (54) below. Usin this relation the equialent circuit in Fiure 39(b) is obtained fro Fiure 39(a). (54) K ( j RF ( j d RF ) ( j ( j ( j RF RF s d d RF ) ) j j RF RF c c j Z 3 RF L ) L j ) Z RF 3 d s RF RF ( ( s s d d d s c c s d c ) c ) Fiure 37. Proposed linearized subthreshold ixer. 6

62 Fiure 38. Sall-sinal odel of the linearized ixer. (a) (b) Fiure 39. (a) Equialent half-circuit of the sall-sinal odel in Fiure 38 (b) siplified sall-sinal odel. 6

63 3.3.. Linearity analysis Seeral linearity analyses for ixers hae been presented usin Volterra series [8]-[85]. Howeer none of these analyses focused on IIP3 estiation for subthreshold ixers. In this section the IIP3 of the transconductance stae (RF V-I conerter ) represented in Fiure 40 is ealuated based on the analysis for the coparable transconductance stae in LNAs. Usin Volterra series analysis [40] [4] the IIP3 of the transconductance stae can be expressed as: IIP 3 6 R s H ( ) A ( ) 3 ( ) (55) where: ( ) (56) 3 ob Z x ob (57) 3 ( ) ( ) ( ) j Z ( ) Z ( ) j Z ( ) Z ( ) d 3 s x (58) Z ( ) Z j Z Z Z Z Z Z ] x (59) [ d 3 3 Z /( R / j (60) ) s b Z /( jl ) j ( K ( j (6) c )) /( Z ) j ( / K ( j. (6) 3 c Z )) 3 In the precedin equations ω is the center frequency of two interodulation tones at ω RF and ω RF Δω is defined as ω RF - ω RF A (ω) is the linear transfer function fro the input ( in in Fiure 40) to the ate-to-source oltae of and H(ω) is the thirdorder nonlinearity transfer function fro the input to the drain-source current of. Ipedances Z (ω)-z 3 (ω) are annotated in Fiure 40. Equations (54) and (56)-(6) were ealuated usin the paraeters of an exaple ixer desin with subthreshold biasin. Fiure 4 shows the calculated result of ε(δωω) ersus L for three cobinations of L and c. The iniu ε(δωω) occurs when L has alues between. nh and.5 63

64 nh in this exaple indicatin that the IIP3 can be iproed by the proper selection of L L and c. oreoer Fiure 4 reeals that there are ultiple solutions to iniize ε(δωω) which relate to the followin desin tradeoffs: a hiher L alue typically results in a lower quality factor and larer layout area and a hih c alue could reduce the conersion ain as discussed in the next section. Fiure 40. Nonlinear sall-sinal odel of the ixer s transconductance stae L = 3.5nH & c = 60fF L = 5.5nH & c = 30fF L = 7.5nH & c = 60fF ( ) L [nh] Fiure 4. Exaple ealuation: ε(δω ω) s. L for different alues of c. 64

65 3.3.. onersion ain Fiure 4 displays the equialent circuit of the proposed ixer in which produces a current equal to s. Usin equations (53) and (54) the relationship between the input oltae RF / and d can be expressed as oltae ain α which can be diided by Z 3 to obtain the correspondin current flowin throuh L. The sall-sinal current (I out ) can be expressed by takin into account that the current throuh L splits accordin to the ipedances of s3 + s4 and / 3 which is captured by factor α : I RF t cos t (63) out Z 3 RF where: RF s (64) j RF c ( j j RF s j K ( j RF RF ) c j RF L ) 3. (65) j ) 3 ( RF s 3 s 4 Fro equation (63) the oltae conersion ain can be deried by odelin the operation with a ultiplication of I out by a square waefor [69]: G ixer Z 3 Z D (66) where Z D = R out //(jω IF out ) - is equal to Z load ealuated at ω IF. 65

66 Fiure 4. Sall-sinal odel for conersion ain analysis ixer siulation results The ixer in Fiure 37 was desined in Donbu 0.µ OS technoloy with an RF frequency of.4 GHz (second tone in two-tone tests at.398 GHz) and an local oscillator (LO) frequency of.4 GHz. Table 8 lists its ain desin paraeters. Fiure 43 displays the layout of the linearized ixer. Bondin and packae parasitic includin bondin wire (L bond and R bond ) and QFN packae capacitance ( pack ) at the external pins (V DD round V BIAS RF port LO port and IF port) were odeled with 90 ff 0.79 nh in series with 0.09 Ω and 6 ff durin the post-layout siulation [86]. Table 9 suarizes the siulated specification paraeters of the linearized ixer with a supply oltae of 0.6 V (half of the noinal supply for this process) usin 66

67 deice odels for three different process corners in adence Spectre. This linearization technique enables to achiee an IIP3 of -0.0 to 6.7 db and a db copression point (P db ) of -4.6 to -9.6 db with low power consuption ranin fro 309 to 55 µw dependin on the process corner case. In the fast and slow corner cases the ε(δωω) ter is no loner optial due to the chanes of the contribution and distribution of the parasitics at the transconductance and switchin staes. The ain ariation in the corner cases also ipacts the IIP3 accordin to equation (55). Fiure 44 displays output spectru fro a transient siulation with an input power leel of -30 db at which the interodulation distortion tones are approxiately 73 db below the two test tones. Fiure 45 shows the IIP3 plot for the linearized ixer which deonstrates the capability of the third-order nonlinearity cancellation for input power leels up to -5 db. The proposed ixer can achiee the best IIP3 and oderate oltae ain by selectin the appropriate power leel at the LO port. Fiure 46 shows the IIP3 and oltae ain ersus power leel at the LO port. Under the best IIP3 condition the switches ( and 6 ) are biased in deep subthreshold as entioned in hapter. opared to desins with stron inersion biasin the LO sinal swin required for switchin is saller because the subthreshold transistors hae a reduced ate-source oerdrie oltae which translates into ore power sains in the LO sinal eneration and buffer circuitry. The RF and switchin staes are operated in subthreshold and a lare LO sinal swin causes the drain-source oltae ( DS ) of the RF input transistors ( and ) to be lare. Hence the total current fro transistors and will be odulated due to the DS oltae swin in cobination with short-channel effects. Furtherore the resultin /I D ariations also chane the instantaneous operatin points of transistors and. As a consequence the ixer will not operate at its optial IIP3 point. Table 0 suarizes the perforance paraeters in coparison to those of other reported low-power ixers. Althouh the ixers in [87] and [88] are operatin with transistors in stron inersion their power consuptions are low copared to conentional desins. The double-sideband noise fiures reported in [70] and [7] were conerted to sinlesideband equialents for the coparison in Table 0. In suary the results indicate that the proposed linearization technique achiees the hihest IIP3 and the lowest power with acceptable ain and noise fiure copared to the references. The layout 67

68 area of the proposed ixer is relatiely lare copared to the references due to the extra inductors. Howeer the layout in Fiure 43 has a siilar size as other hih-perforance ixers that use inductors for perforance enhanceents such as the ixer in [87] and the. ixer in [89]. Table 8. ixer desin paraeters Key oponent Value V DD [V] 0.6 L [nh].47 L [nh] 5.45 c [ff] 340 R out [Ω] 85 out [pf].8 W/L per finer ( ) [μ/μ] 6/0.3 Nuber of finers ( ) 64 W/L per finer ( 3456 ) [μ/μ] 5.8/0.3 Nuber of finers ( 3456 ) µ L L 866 µ L L Fiure 43. Layout of the linearized ixer. 68

69 Output Power [db] Table 9. Siulation results with f RF =.4 GHz f RF =.398 GHz and f LO =.4 GHz for process corner cases (V DD = 0.6V) orner ase SS TT FF Gain [db] NF SSB [db] P db [db] IIP3 [db] I D [µa] P D [µw] Fiure 44. Output spectru fro a siulation with -30 db input power Input Power [db] Fiure 45. IIP3 cure (typical corner case in Table 9). 69

70 IIP3 [db] Gain [db] IIP3 Gain Power of LO Port [db] 6 Fiure 46. Siulated ixer IIP3 and oltae ain s. LO power (typical corner case in Table 9). Reference Table 0. oparison of ixer desins This work* [70]* [7]* [87]# [88]# RF [GHz] IF [Hz] P LO [db] Gain [db] NF SSB [db] P db [db] IIP3 [db] P D [W] Layout area [ ] Tech. [μ] * subthreshold ixer # stron inersion ixer [70]: Results are fro probe easureents. The chip size is 0.8 includin fie pads RF front-end easureent results A.95 GHz low-power linearized subthreshold RF receier front-end (in Fiure 47) has been desined and fabricated in Donbu 0.µ OS technoloy with an RF frequency of.95 GHz (second tone in two-tone tests at.948 GHz) and an LO frequency of.96 GHz. Fiure 48 displays the front-end chip icroraph of the fully differential LNA and ixer with an area of.5.. As shown in Fiure 49 the prototype chip was bonded to a conentional QFN4 packae that was assebled on 70

71 a printed circuit board (PB) for easureents. Fiure 50 isualizes the test setup of the RF front-end. Table lists the key desin paraeters of the LNA and ixer. The front-end consues a 500 µa current fro a 0.6 V power supply instead of the noinal. V supply oltae in 0.µ OS technoloy. Fiure 47. Scheatic of the linearized subthreshold RF front-end. Fiure 48. hip icroraph of the fabricated linearized subthreshold RF front-end in Donbu 0.µ OS technoloy. 7

72 Fiure 49. PB for RF front-end testin. Fiure 50. Block diara of the RF front-end easureent setup. 7

73 Table. RF front-end desin paraeters oponent VALUE LNA circuit V DD 0.6 V I D 875 µa L L L s s_ext d_ext L d d R d W/L per finer ( 34 ) Nuber of finers ( 34 ) 64 ixer circuit V DD 6. nh 3.5 nh.4 nh 30 ff 50 ff 6.4 nh 88 ff 70 Ω 6µ / 0.3µ 0.6 V I D 65 µa L L c out R d W/L per finer ( 56 ).7 nh 5.8 nh 337 ff 78 ff KΩ 6µ / 0.3µ Nuber of finers ( 56 ) 64 W/L per finer ( 7890 ) 5.8µ / 0.3µ Nuber of finers ( 7890 ) 64 Fiure 5 shows the easured S of the linearized subthreshold RF front-end. S is below -0 db at.95 GHz. Fiure 5 displays the plot of the easured doubleside band noise fiure (NF DSB ) that is 4 db at 0 Hz with the input balun. After deebeddin the effect of the input balun loss (5.5 db) the sinle side band noise fiure of the RF front-end is 9.5 db at 0 Hz. Fiure 53 shows the easured IIP3 of the frontend and the output spectru fro a test with a two-tone input sinal and an input power of db. Fiure 54 contains the plot of output power easureents fro a power leel sweep of a sinle 0 Hz tone to deterine the -db copression point (P db ) of 73

74 the RF front-end. The IIP3 and P db of the subthreshold RF front-end are -0.8 db and -.7 db respectiely. After de-ebeddin the effect of the output balun loss (9.5dB) based on the easured transient output oltae waefor in Fiure 55 the oerall oltae ain of the RF front-end is 0.6 db. Table suarizes the perforance of narrowband low-power RF front-ends with operatin frequencies ranin fro.95 to 5. GHz in coparison to the presented desin. opared to other works our desin has the lowest power consuption and can achiee the lowest noise fiure. Furtherore the desins in [90]-[93] contain sinle LNAs to sae power in coparison to the fully differential LNA stae in this work that has the benefit of creatin robustness to phase shift ibalances. Fiure 5. easured S of the RF front-end. Fiure 5. easured NF DSB of the RF front-end (IF = 0 Hz). 74

75 (a) (b) Fiure 53. (a) easured IIP3 of the RF front-end with balun (9.5dB loss) (b) output spectru fro a test with two tones at 0 Hz and Hz and an input power of db. 75

76 Fiure 54. easured -db copression point of the RF front-end with input and output baluns (at IF = 0 Hz). Fiure 55. easured output aplitude before the output balun. 76

77 Table. oparison of low-power RF front-ends THIS WORK [90] * # [9] # [9] # [93] f RF [GHz] f IF [Hz] n/a P LO [db] -9-5 n/a n/a n/a S [db] -0 n/a -7 n/a -0.6 Gain [db] NF BSB [db] n/a IIP3 [db] P db [db] -.7 n/a P D [W] Tech. [n] Area [ ].65 $ $.44 $ * passie ixer # sinle LNA $ without pads with pads onclusion A.4 GHz ixer was desined in Donbu 0.µ OS technoloy to deonstrate a proposed IIP3 enhanceent technique for subthreshold ixers. Post-layout siulations resulted in an IIP3 of 6.7 db a oltae ain of 8.6 db and a sinlesideband noise fiure of 9. db with a power consuption of 0.43 W. The linearization ethod ixer does not require an auxiliary aplifier to boost the ixer linearity akin it suitable for low-power narrow-band wireless standards. For further alidation of the new desin technique a.95 GHz RF receier front-end includin an LNA and a ixer was fabricated in Donbu 0.µ OS technoloy. easureents resulted in an IIP3 of -0.8 db a oltae ain of 0.6 db and a sinle-sideband noise fiure of.5 db with a power consuption of 0.9 W. 77

78 4. Analo Frond-End ircuits for Brain Sinal Acquisitions with Dry Electrodes A possible solution for boostin input ipedance would be to add a classical neatie ipedance conerter (NI) at the input of an instruentation aplifier (IA). Fiure 56 shows a siplified NI circuit that could be used to enerate a neatie capacitance at the input node of the IA if the coponent Z is a capacitor [94]. Howeer this approach would require an additional aplifier whose power and area consuption is undesirable. Furtherore the additional noise fro the operational aplifier at the input of the IA would hae to be carefully assessed. Fiure 56. Basic neatie ipedance conerter (NI) where Z in = -Z when R = R. 4. Syste-leel considerations The neatie capacitance eneration schee proposed in this chapter is interated into the IA and thereby aoids an extra aplifier. The discussed IA was desined as part of a larer research project in which the oal is to autoate the input capacitance cancellation as isualized in Fiure 57 with on-chip onitorin usin a diital sinal processor (DSP) and with a proraable capacitor bank within the IA for tunin [95]- [96]. The calibration syste will include an on-chip test current enerator (i test ) with hih output ipedance and low output noise. As shown in Fiure 58 the test current enerator consists of a relaxation oscillator a liiter a frequency diider and an operational transconductance aplifier (OTA) [97]-[98]. The on-chip oscillator enerates a 0 KHz 78

79 rail-to-rail square wae which is diided down to 9.5 Hz. A oltae liiter conerts the rail-to-rail sinal to a leel (80 V differential peak-to-peak) that is copatible with the OTA input requireent. The OTA s transconductance is desined to be 5 ps which akes the i test anitude equal to pa. If the input ipedance of the IA is boosted to aboe.5 GΩ at 9.5 Hz the oltae swin at the IA s inputs would be ore than 5 V peak-to-peak because of the haronics. Subsequently the oltae swin is aplified and filtered for input ipedance ealuation based on aplitude estiation with oltae leel detectors or an analo-to-diital conerter (AD). This chapter concentrates on desin aspect of one critical circuit of the technique suarized in Fiure 57: the IA with neatie capacitance eneration. IA desin with input capacitance cancellation for ipedance boostin has eneral usefulness in eerin biopotential and bioipedance easureent applications reardless of how the tunin ethod is ipleented. Fiure 57. Analo front-end for EEG sinal easureents with electrode cable capacitances and calibration blocks for input ipedance boostin. 79

80 i test i test OTA Liiter V out V in Instruentation Aplifier Frequency Diider N Oscillator Z in ~ i test Z in A IA Fiure 58. urrent injection with the test current enerator. 4. Instruentation aplifier Fiure 59(a) shows the scheatic of the widely used IA topoloy with direct current feedback where the D ain of the IA is decided by the ratio R /R and the doinant pole depends on R and [95] [99] [00]. For the input ipedance test of the IA the resistor R has been desined with diital proraability to ipleent four different ain odes as illustrated in Fiure 59(b) where the sallest ain settin is 0dB. The aplifier B was realized as in [99]. Fiure 59(c) shows the input biasin circuity of the IA usin pseudo resistors [0]. The effectie ipedances fro the inputs ( i+ i- ) of the IA to V bias are 4.7 GΩ at D and 3.36 GΩ at 00Hz respectiely. The transfer functions fro the inputs ( i+ i- ) to A B D E F H I J K and o are analyzed in Section 4.. to ealuate the possibilities for neatie capacitance eneration feedback (NGFB). Since nodes and D in Fiure 59(a) are the ost appropriate locations to obtain suitable ains for eneratin neatie capacitances at the inputs ( i+ i- ) the NGFB realization at these two nodes is elaborated in Section

81 (a) (b) (c) Fiure 59. (a) Instruentation aplifier (IA) with direct current feedback and neatie capacitance eneration feedback (NGFB); (b) ariable R ipleentation; (c) input biasin circuitry. 8

82 8 4.. Instruentation aplifier sall-sinal odel analysis Fiure 60(a) shows the sall-sinal odel of the IA s input stae and the current feedback loop for solin the transfer functions fro the inputs to internal nodes. All parasitic capacitances are oitted durin the analysis because the typical applications of this IA are at low frequencies (below KHz). It is also noteworthy that the sall-sinal inputs ( A and B ) of the differential pair ( 5 and 6 ) in the feedback loop are not truly differential due to the asyetric characteristics lookin into A ( 3 is diode-connected) and B ( 4 is not diode-connected). Hence the phase of B follows that of A and G is not a irtual round. For this reason the sall-sinal drain-source resistance (/ dstail ) of tail should be taken into account durin the analysis. Without the effect of the NGFB the current suation equations at nodes throuh 4 in Fiure 60(a) are: 0 ) ( 9 D i E F E R (67) 0 ) ( 0 i F F E R (68) 0 ) ( 4 A i F (69) 0 ) ( B A G tail ds b b ; (70) where - 0 are the transconductances of - 0 b5 and b6 are the body effect transconductances of 5 and 6 and dstail is the sall-sinal drain-source adittance of tail. Fro Fiure 60(a) the oltaes A D G can be expressed as 3 ) ( i E A (7) ) ( A G b (7) ) ( B G b D (73) ) ( b A G. (74) Note that the conditions = 3 = 4 5 = 6 7 = 8 9 = 0 and b5 = b6 are alid for this analysis in the absence of deice isatches. Furtherore the

83 83 sae definitions as in [95] are used next: in = i+ - i- = E - F where i+ = in / and i- = - in /. With these definitions the followin oltae ains fro in to A-G can be deried fro the aboe equations: D A tail ds in A A V 7 (75) D R A tail ds in B B V (76) D R A tail ds in V (77) D R A tail ds in D D V (78) D A tail ds in E E V 7 3 (79) D A tail ds in F F V 7 3 (80) D A in G G V ; (8) where: D=[( 5 + b5 + dstail ) dstail ] R. For the output stae of the IA the current suation equations at nodes 5 and 6 in Fiure 60(b) are: 0 ) ( ) ( 3 o I H I V Z (8) 0 ) ( 4 D H H I Z ; (83) where Z = R (/s ). Note that the desin conditions = 3 = 4 and 5 = 6 are assued for this analysis in the absence of deice isatches. Fro Fiure 60(b) the oltaes K J and o can be expressed as

84 ) ( o I K (84) 6 4 H J (85) ) ( K J B V o A. (86) Based on (84) (85) and (86) if the oltae ain (A VB ) of B is approxiated to be infinite for siplicity o can be rewritten as H I o. (87) Note that 9 = is another condition used in this desin. The oltae ains fro in to H-K and to o can be deried fro the aboe equations and conditions: D R A tail ds in H H V (88) D R R Z A tail ds in I I V (89) D R A tail ds in J J V (90) D R A tail ds in K K V (9) 9 R Z R Z A in o o V. (9) Fro (75) and (76) it can be obsered that A VB is always larer than A VA and that A VA and A VB hae the sae phase. Equations (77) and (78) show that A V and A VD are in anti-phase. Althouh these ain anitudes are not equal nodes and D are well-suited as points at which the NGFB can be added. Fro (79) and (80) the ains A VE and A VF hae the sae phase if 3 7 dstail /( D) > 0.5 which would coplicate the use of nodes E and F for the NGFB. The ains A VH A VI A VJ and A VK

85 in the output stae of the IA hae the sae phase. Thus these nodes are not suitable for addin the proposed NGFB. (a) Fiure 60. (a) Sall-sinal odel of the IA s input and feedback staes; (b) sall-sinal odel of (b) the IA s output stae. 85

86 4.. Neatie capacitance eneration feedback analysis Fiure 6 shows the proposed NGFB ipleentation with an 8-bit diitally-controlled capacitor ( p - 7 p ) and one fixed capacitor ( p0 ) between nodes i+ and. The axiu and iniu capacitance alues occur with S p = [] and [ ] respectiely where '' or '0' indicate that the switch is turned on or off. The sae proraable capacitor confiuration was connected between nodes i- and D with control switches S n Nelectin the ery hih resistance at the ates of the transistors the input ipedances (Z inp and Z inn ) in Fiure 57 can be deried as Z inp ( s) (93) s s sp total i Z inn ( s) ; (94) s s sn total i where sp and sn are the luped cable and PB capacitances at the positie and neatie inputs of the IA and totali+ and totali- represent the IA s total equialent capacitances at the inputs i+ and i- respectiely. The tunin rane of the 8-bit capacitors can be desined to copensate for the pf capacitances fro the cables and PB by eneratin neatie totali+ and totali- alues throuh the presented NGFB confiuration. This property becoes eident after usin iller approxiations to express totali+ and totali- in ters of preiously deried ains: total i s [ ( A p 0 p V E ) 7 i 0 ( i d S pi ( A V A )] ( A ) V (95) ) total i s [ ( A n 0 n V F 7 i 0 ) ( i d S ni ( A V B )] ( A ) V D ; (96) ) where sx and dx are the parasitic ate-source and ate-drain capacitances of transistor X. The siulation result in Fiure 6 reeals that the input ipedance is reatly boosted by the NGFB actiation and that the oltae swin at the IA input is far aboe the noise leel durin the test current injection with the OTA. 86

87 Fiure 6. Neatie capacitance eneration feedback (NGFB) with proraable capacitors between nodes i+ and (and nodes i- and D ). Voltae Swin into IA (V) p =50pF w/o NGFB p =50pF w NGFB Tie (s) Fiure 6. Voltae swins at the IA input with current injection fro the OTA for two cases: i.) with NGFB ii.) without NGFB. (Noise was actiated durin the transient siulations based on the interated noise density fro 0.0Hz to 00Hz.) 4.3 IA siulation results The IA in Fiure 59 was desined in IB 0.3μ OS technoloy for EEG sinal easureent applications. A coensurate IA without NGFB was desined as reference for coparison. Table 3 contains the key desin paraeters of both IAs. Identical supply oltaes of. V and total currents of 78 μa were used for both desins. p0 p n0 and n were selected to coer cable/pb capacitances fro 50 pf to 87

88 00 pf for the IA across all deice corner odel cases. Notice that p0 is not equal to n0 and that p is not equal to n due to the different ains and phases discussed in Section 4... Ipleentin lare capacitors as off-chip capacitors is frequently done in analo front-ends for biosinal acquisitions as in [8] [9] [30]. Therefore it is assued here that would not be laid out on the chip. Table 4 suarizes the siulated specification paraeters of both IAs desined in IB 0.3μ OS technoloy. The two desins hae the sae ain bandwidth output offset oltae and noise in the typical corner case with sp = sn = 00 pf (Fiure 57). The coon-ode rejection ratio (RR) was desined to be coparable to a coercial IA [0]. The onte arlo results in Fiure 63 were obtained with foundrysupplied statistical deice odels usin actiated process and isatch ariations. They show that there are no sinificant differences in the anticipated RR PSRR or THD of both IAs. Fiure 64 displays the siulated noise density ersus frequency for both IAs which is also not ipacted by the addition of the NGFB ethod. Fiure 65 shows the input ipedances of Z inp and Z inn for both aplifiers in the typical corner case for different sp and sn alues. The ipedances at Z inp and Z inn for the IA with NGFB reach 500 Ω or ore at 00 Hz. As described in Section 4. a tunin schee such as in Fiure 57 is required to adjust the proraable capacitors in Fiure 6 to a alue that cancels ost of the capacitance at each input. For exaple the case with sp = sn = 00 pf in Fiure 65(a) requires that S p = [0000] and S n = [00000]. On the other hand without the NGFB ethod the ipedances at Z inp and Z inn are only below 0 Ω at 00 Hz which fall short of the 500 Ω requireent for easureents with dry electrodes [33]. The siulation results in Fiure 65(b) indicate that the IA with NGFB has the capability to copensate for different cable capacitances at each input ( sp = 00 pf and sn = 50 pf). Fiure 66 shows the ipedances at Z inp for the IAs with and without NGFB in different process corner cases with sp = 00 pf. The ipedances at 00 Hz for the IA with NGFB are oer 500 Ω in all corner cases after adjustin the switch settins (S p ) of the capacitor array. In contrast the ipedances at 00 Hz for the IA without NGFB are less than 0 Ω in all process corner cases. The proposed tech- 88

89 nique boosts the input ipedance sinificantly ore than the ethod in [03] where the ipedance increases fro 6 Ω to 30 Ω. Howeer the trade-off is that the presented IA has hiher power consuption copared to the μw IA in [03]. Table 3. Paraeters of the IA desins in IB 0.3μ OS technoloy without and with NGFB oponent/paraeter Without NGFB With NGFB V DD [V].. Power supply current [μa] R [KΩ] R [KΩ] [nf] p0 [pf] p [pf] n0 [pf] -.3 n [pf] Table 4. oparison of instruentation aplifier siulation results Perforance Without NGFB With NGFB Gain [db] Bandwidth [Hz] Hz [db]* Hz [db]* Hz [db]* for V pk-pk input Output offset oltae [V]*.8.8 Total input-referred oltae noise [μv] (noise bandwidth: Hz).7.7 * Results are the ean fro 500 onte arlo siulation runs includin process and isatch ariations fro foundry-supplied deice odels. 89

90 60 0 u = sd = N = u = sd = N = (a) 0 30 u = sd = N = (b) 0 30 u = sd = 7.44 N = (c) u = sd = N = (d) u = sd = N = () 500 (e) () (f) Fiure 63. onte arlo siulation results of both IAs. RR: (a) IA without NGFB and (b) IA with NGFB PSRR: (c) IA without NGFB and (d) IA with NGFB THD: (e) IA without NGFB and (f) IA with NGFB. 90

91 3 3 V/sqrt(Hz) (uv/sqrt(hz)) V/sqrt(Hz) (uv/sqrt(hz)) freq (Hz) (a) 00 k k freq (Hz) Fiure 64. Noise distributions: (a) IA without NGFB (b) IA with NGFB. (b) (a) (b) Fiure 65. Ipedances at the IA inputs with and without NGFB for different sp and sn alues: (a) sp = sn = 00 pf (b) sp = 00 pf and sn = 50 pf. 9

92 Fiure 66. Input ipedance coparison (at Z inp ) for the IAs with and without NGFB in different process corner cases. 9

93 4.4 EEG front-end easureent results Fiure 67 displays the icroraph of the analo EEG front-end chip with interated test sinal enerator and diital calibration for input ipedance boostin desined by other ebers of our research roup. The instruentation aplifier with input ipedance boostin was deeloped within the scope of this dissertation. The 4 4 prototype chip was bonded to an 84PL packae that was assebled on a printed circuit board (PB) for easureents. The front-end operates with the noinal. V supply oltae in IB 0.3µ OS technoloy. Fiure 67. hip icroraph of the fabricated EEG front-end with input ipedance boostin capability in IB 0.3µ OS technoloy IA ain easureent results To enable easureent of the input ipedance in addition to noral operation the IA has four different ain settins (0dB 30dB 40dB 50dB) correspondin to different diital codes as annotated in the easured frequency responses in Fiure

94 (a) (b) (c) Fiure 68. Four oltae ain settins of the IA: (a) 0dB (b) 30dB (c) 40dB and (d) 50dB. (d) 94

95 Since the IA on the test chip is ebedded in the analo EEG front-end with liited accessibility for characterization of the differential sinal after the IA output buffer arious characteristics were ealuated with syste-leel easureents at the VGA output. Note that the easureent results in the reainder of this subsection include perforance paraeters that are liited by other blocks in the syste. Neertheless they ie insihts into the IA s feasibility for EEG sinal easureent applications as part of the analo front-end. Fiure 69 displays the frequency responses of the coplete EEG front-end. The easured ains of the front-end are 66dB 75dB 8dB and 9dB (easured IA iniu ain and axiu ains: 3dB and 4dB VGA iniu ain and axiu ains: 34dB and 50dB). The attenuation at the notch frequency around 60Hz is ore than 60dB for each ain settin. The ain alues in Fiure 69 were de-ebedded to account for a 40dB resistie attenuator that was added at the input to reduce the test sinal aplitude to a typical EEG sinal leel and to account for the 6dB ain of an output buffer on the PB. Fiure 70 shows the output noise easureent result without de-ebeddin. The noise interated fro 0.5 to 45Hz is 3.75µV usin the axiu ain settin in the IA stae and the iniu ain settin in the VGA stae. Fiure 7(a) shows that the third-order haronic distortion (HD3) coponent is at least 5.3dB below the fundaental sinal (5.3dBc) with the axiu ain settin of the IA the iniu ain settin of the VGA (total ain: 75dB) and a peak-to-peak differential input oltae of 00µV at 5Hz. This input aplitude and ain settin cobination was chosen to ensure that the input aplitude is within the typical EEG sinal rane while each stae has sufficient oltae headroo and the third-order haronic is not isible (i.e. below the noise floor). Howeer with the axiu IA ain the input D offset of the LPNF stae can ipair the oerall linearity perforance. Note that the axiu IA ain was only chosen for this test to deonstrate the low-distortion characteristic but in noral ode of operation a low ain settin would be used when the EEG sinal strenth is hih. With hiher (copared to the typical EEG sinal leel) input aplitude of 600µV pk-pk at the IA and the lowest front-end syste ain settin the HD3 is at least 57dBc as shown in Fiure 7(b). The RR is 76.5dB which was calculated fro the test case in Fiure 7 where the coon-ode input and differential output aplitudes are 5V and 4.V at 0Hz usin the front-end ain settin of 95

96 75dB. Based on the easureent in Fiure 73 the PSRR is 74.0dB at the differential output when the input and output aplitudes are 5V and 6.V at 0Hz with a frontend ain of 76dB. Fiure 69. easured EEG front-end frequency responses for four ain settins. Fiure 70. Output-referred noise easureent of the coplete EEG front-end. 96

97 (a) (b) Fiure 7. HD3 easureent at 5Hz with a 5Hz sinusoidal input hain a differential aplitude of (a) 00μV and (b) 600μV. 97

98 Fiure 7. Input coon-ode ain easureent: differential front-end output spectru durin a test with a 5V sinusoidal coon-ode input sinal at 0Hz. Fiure 73. Power supply ain easureent: differential front-end output spectru durin a test with a 5V sinusoidal sinal injected at the power supply rail with a frequency of 0Hz. 98

99 4.4. Input ipedance easureent results Fiure 74 displays the input ipedance easureent setup for the IA. Test resistors are placed in series with the IA inputs such that the attenuation at the inputs can be used to calculate the IA input ipedance. With a known sinusoidal (khz) input aplitude the output aplitude can be onitored because the sinle-ended IA output is routed to a pin on the chip for testin purposes. After perforin easureents with and without the test resistors the input ipedance of the IA was calculated fro the output aplitude chane that results fro the attenuation due to the easured resistance of R TEST in Fiure 74 and the IA input ipedance. The ain of the IA was set to 30dB for this test durin which the control codes of the NGFB block in Fiure 59 were anually set to calibrate for hih input ipedance. Three different in alues (50pF 00pF 50pF) were used to exaine the functionality of the neatie capacitance eneration. Fiure 75 contains plots of the IA input ipedances with these input capacitance alues for seeral control codes of interest. The axiu (boosted) differential input ipedances for in of 50pF 00pF and 50pF are GΩ 800Ω and 550Ω respectiely. Note that the codes on the x-axes are not continuous because the selected easureents were perfored to isualize the ipedance boostin effect for codes of interest. Since the calibration ethod inoles cyclin throuh all codes to find the optiu the linearity of the Z in s. code plots is not iportant. To identify the oer-copensation reions in Fiure 75 an oscillation detector has been incorporated into the autoatic calibration syste (Fiure 57) usin an on-chip coparator [96]. Ailent 3350A Waefor Generator BN AD83 Sinle-ended to Differential On-Board Test PB RTEST in in RTEST VIN+ VIN- Instruentation Aplifier BN Tektronix DPO04B Oscilloscope Fiure 74. Test setup for IA input ipedance easureents. 99