A 100KHz 20MHz source follower continuous time filter for SDR applications

Transcription

1 A 00KHz 0MHz source follower continuous tie filter for SDR applications SRaasay, SKuaravel and DrBVenkataraani ABSTRACT The source follower based filters are proposed in the literature for wireless LAN applications and are preferred as they dissipate lower power copared to the filters usin other architectures To coply with ultitude standards, filters with bandwidth proraable fro 00KHz 0MHz are required In this paper, a second order, coposite source follower based filter is ade to work in weak inversion in order to achieve wide tunin rane and to iniize power consuption The centre frequency of this filter is varied usin current steerin DAC The proposed filter is desined and ipleented on TSMC-08µ CMOS process with V supply The siulation results deonstrate the tunability of the centre frequency fro 00KHz to 0MHz which eets the requireents of zero IF receivers for SDR applications The third order input intercept point (IIP3) is found to be 5 dbvp for an input sinal of 00Vp The power dissipated by the filter is µw and 0µW at 00 KHz and 0 MHz respectively The proposed filter consues 4 ties less power than that proposed in the literature at the cost of 5 ties increase in the noise A 55µVrs noise ives a dynaic rane of 66dB Keywords analo baseband filter, continuous-tie filter, Software Defined Radio, subthreshold, reconfiurable filter, source follower, current steerin DAC INTRODUCTION The rowin popularity and iportance of obile counication, and the evolution of different standards for voice and data are pushin the research towards the ipleentation of fully interated ulti standard transceivers []- [6] Such transceivers should switch sealessly aon different standards in order to achieve the so-called lobal roain for both voice and data applications GSM and WCDMA (UMTS) are the doinant standards for voice and ixed voice/data obile services, while WLANs based on the IEEE 80a/b/ protocols are the ost iportant standards for hih data rate wireless internet access Finally, bluetooth protocol enables wireless connectivity for various appliances at low data rates over a short distance This ultitude of standards requires ultiode terinals to be capable of adjustin their confiuration and reception ode dependin on the standard and quality of service requireents In addition to eetin the traditional perforance etrics such as power, area and price, a sinle handset should now coply with this ultitude of standards A software defined radio (SDR) proves to be a proisin technoloy for this deand In these systes, analo baseband filter plays a key role as it provides channel selection and anti-aliasin For SDR applications [], zero IF receivers are coonly used In this paper, a low-pass filter capable of bein tuned over a wide rane of frequencies suitable for zero-if receiver is proposed Continuous tie filters are quite suited for applications with oderate speed and low power requireents Traditionally, continuous tie CMOS filters with G -C architecture have been desined with MOS transistors operatin in stron inversion reion when bandwidth of interest is of the order of several tens of MHz A nuber of architectures have been proposed in the literature for ipleentin the transconductor Analo baseband filters for UMTS/WLAN applications have been proposed usin active R-C cells in [4] and Active G -RC in [5] The latter schee requires less area as it shares the capacitor for various applications Continuous tie filter usin switchable operational aplifier and capacitor arrays is proposed in [6] to achieve flexible trade off between power and bandwidth A G C Lowpass Filter for zero-if Mobile Applications with a tunin rane of 00 KHz to MHz is achieved in [7] usin Si-Ge process Push-pull inverters are proposed in [8] for realizin the transconductor This does not have any internal node and results in lare bandwidth However, for realizin proraable filters, this schee requires the power supply voltae to be varied This is not suitable for low voltae applications and it results in poor power supply rejection ratio (PSRR) [8] To solve this proble, floatin battery ipleentation is proposed in [9] But this schee requires a lare bias resistor, which introduces an additional pole in the reion of interest Crobez et al [0] uses Nauta s [8] architecture with novel, but coplex switchin schee to satisfy noise and linearity levels for reconfiurability with provision for independent transconductance and capacitance tunin However, it uses coplex switchin echanis and its power consuption is hih The source follower filter for WLAN applications reported in [] consues less power but does not have proraable bandwidth feature In this paper, a second order, coposite source follower based filter is ade to work in weak inversion in order to achieve wide tunin rane and to iniize power consuption This paper is oranized as follows Section describes source follower based second order low pass filter operatin in weak inversion reion Section 3 presents the structure of the DAC syste for bandwidth proraability The siulation results are iven in Section 4 followed by the conclusions in Section 5 THE PROPOSED SECOND ORDER RECONFIGURABLE LOWPASS FILTER Overview of the source follower based filter

2 The second order low pass filter havin source follower architecture is proposed for the first tie in [] This architecture has the followin advantaes: () It results in low output ipedance and a resistive load can be driven with neliible effects on the filter perforance in ters of linearity and filter transfer function accuracy () The inherent feedback present in the structure ives better linearity (3) Distortion introduced in the voltae to current conversion process in the case of current ode filters does not arise In order to enable tunability and to eliinate botto plate capacitance, filter proposed in [] is odified and is shown in Fi It has a fully differential structure and operates like a coposite source-follower It provides an ideal unity DC-ain All the transistors are desined to be of the sae size and draw the sae current As a result, they all exhibit the sae transconductance values Assuin that the transistor s output conductance ( ds ) is uch saller than the transconductance ( ), the filter transfer function can be shown [] to be that iven in () H ( S ) = S CC C + S + where is the transconductance of the transistor, C and C are the capacitors The filter paraeters (the pole frequency, the quality factor, and the DC-ain) are iven by C Q = () C ω 0 = π f 0 = (3) CC Fro (3), it is clear that by varyin the and the capacitor values, we can vary the frequency of operation Reconfiurable lowpass filter in subthreshold reion The odification of the low pass filter shown in Fi, for the bandwidth to be proraable fro 00KHz to 0MHz is considered next Let us assue that a butterworth filter with quality factor of 0707 and capacitors C and C of values 05pF and pf respectively are used for the filter For this filter, the required for this frequency rane varies fro 3µS 06µS This value, is obtained by operatin the transistor of source follower circuit in weak inversion/subthreshold reion The operation of the filter in weak inversion ode is quite suited for low power and low frequency applications because of the followin reasons: ) The axiu voltae swins between the terinals of the devices workin in the weak inversion reion are saller than those workin in stron inversion reion This perits the use of lower supply voltaes and there by reduces the power consuption () ) Low pass filters require saller transconductance ( ) and larer capacitance (C GS and C GD ) The value of these capacitances ay be increased by increasin the product of width (W) and lenth (L) of the device However, in order to obtain lower, the width has to be sall Hence, the lenth of the device is increased Use of devices with larer lenth results in better atchin of devices 3) The output coon ode voltae is self biased by the transistor V GS This relaxes the need for CMFB (coon ode feedback ) circuit which in turn reduces the power dissipation The transconductance ( ) of the transistor operatin in the subthreshold reion is iven by (4) = I D nφ T (4) where n is sub threshold slope factor ( 5) and Φ T is theral voltae (59 roo teperature ) I D is the current of a MOS transistor [] and is iven by (5), VGB VT0 I D = n k ΦT exp nφ T V SB VDB * exp exp ΦT ΦT where µ is obility, C ox is the oxide capacitance of the transistor, β = µc ox is the process ain factor and transconductance paraeter k = β (W/L), V GB, V SB, V DB are ate, source, drain voltaes wrt bulk respectively, V T0 is the threshold voltae when V SB is zero For operation in subthreshold reion, V DB > 5 Φ T and V SB = 0 In this case, (5) siplifies to that iven in (6) I D VGS V = n k Φ T exp nφ T Fro (4), it can be noted that for the required rane, the current is to be varied between 3nA to 8µA Usin (6) and assuin V T0 of 05V and W/L of the transistor to be 80µ /05 µ, V GS can be found to be 0V to 440V The supply voltae used is V This requires the DAC voltae to be varied in the rane 760V 980V The lenth of the transistors used for the above filter is chosen takin into account quality factor (Q) and linearity The sensitivity of the Q factor with respect to the output MOS conductance, ds, can be shown [] to be that iven in (7) Q Q ds S ds= ds Q 3 ds (7) In order to ake the Q factor to be independent of variations in output conductance ( ds ), ds has to be chosen to be sall Next, let us consider the effect of lenth of the transistor on the linearity of the filter As the filter structure is fully differential, second order haronic HD, ets cancelled out Assuin that the third T0 (5) (6)

3 haronic distortion (HD3) is the ain contribution to the total haronic distortion, when transistors operate in weak inversion, the HD3 can be shown to be that iven in (8) at low frequencies HD3= 6 vin kt n q + d0 6 v λ Fro (8), it ay be noted that the linearity can be increased by increasin λ (channel lenth odulation coefficient) This in turn requires the lenth of the transistors to be increased To have low ds value and hih linearity, the lenth of the transistor is chosen to be 05µ for our ipleentation in 08µ CMOS technoloy 3 Noise Perforance of the proposed filter At very low frequencies correspondin to the bioedical sinals, only the flicker noise coponent of the transistors is doinant In order to reduce the flicker noise, PMOS transistors are preferred The flicker noise is inversely proportional to ate area (WxL) In order to reduce this noise, the ate area should be increased However, since the proposed filter requires lower transconductance of the order of ns, the W/L ratio required is low and hence transistors with larer lenth and saller widths are chosen The input referred voltae noise of the second order source follower circuit ay be calculated usin the half circuit noise odel shown in Fi Let the ean square noise voltaes correspondin to the transistors M4, M and M0 be denoted as V n, V n and V n3 respectively It ay be noted that the diensions of all these transistors are the sae The ean square input-referred voltae noise ( V n ) due to the flicker noise of a transistor[3] is iven by V n K f W L f (9) cox where C ox is the oxide capacitance, f is the frequency, K f is the flicker noise coefficient It varies between 0 - to 0-4 The ean square input referred noise voltae of the second order source follower circuit usin the half circuit odel can be shown to that iven in (0) v 6 k f r cox f W L in ( +(r r ) ) o o o in, n (0) where r o and r o are the output resistance of the transistors M and, M respectively As the ain of the circuit is unity, both the output referred noise and the input referred noise are sae Usin (8), for a iven HD3, the value of V in,rs can be found out Usin this in (0), the dynaic rane is estiated and is iven by () (8) DR V 0 lo 0 V = in,rs () in,n 4 Miniu supply voltae required for the filter Since the desin proposed is tareted for low power application, the supply voltae should be as sall as possible In this paper, for the ipleentation of the filter in 08µ CMOS technoloy, V t of 05V, axiu V s of 450V and voltae swin of 00V are assued This akes the V sat of PMOS transistors to be 50V and it ensures the transistors to be in weak inversion reion Usin these voltaes, the iniu supply voltae required for the PMOS source follower filter shown in Fi is iven by () V dd, in 3v sat +vt + vswin () Fro (), it ay be verified that V dd, in should be at least 09V For our desin, a supply voltae of V is chosen 3 DAC DESIGN In this paper, a 7 bit current steerin DAC is used to produce necessary bias voltaes V bias required for frequency tunin The circuit diara of the proposed DAC is shown in Fi 3 As entioned in section 3, the bias voltae required to tune the filter fro 00KHz 0MHz is 980V 760V The supply voltae to the DAC is V To obtain 980V, the switch correspondin to the ost sinificant bit b7 is always tied to V The load resistor of DAC is fixed at 500 ohs The full scale voltae rane of the DAC is 0V The voltae resolution of least sinificant bit is 343V The W/L ratio of the current source transistor correspondin to bit b0 is calculated as 05µ /µ The successive bits b b7 are scaled accordinly The diensions of the switches are the sae as that of respective current source transistors When the bits b- b6 are all hih, the DAC produces 760V, akin the filter to exhibit a cutoff frequency of 0MHz Siilarly, if all bits b- b6 are low, DAC produces 980V, akin the filter to exhibit a cutoff frequency of 00KHz 4 SIMULATION RESULTS The reconfiurable G-C lowpass filter is ipleented in TSMC 08µ CMOS technoloy with V supply voltae Fro siulation, it is estiated that the lowpass filter block consues power of µw at 00 KHz and 0µW at 0 MHz The coarse tunability of the centre frequency of the filter for various DAC voltaes are shown in Fi 4 Fro these results it ay be noted that the bandwidth can be tuned fro 00 khz to 0 MHz achievin a tunin rane of ore than two orders of anitude This bandwidth rane eets alost all wireless applications (GSM, Bluetooth, CDMA000, W-CDMA/UMTS and WLAN a/b/ receivers with zero IF) The 7 bit CSDAC output voltae for counter input is shown in Fi 5 It deonstrates that it can provide bias voltaes in steps of 34V fro 980V 760V Finer resolution of tunin rane is possible by increasin

4 the resolution of the DAC The power consuption of the DAC is 865µW Fi 6 shows an IIP3 (Third order Input Intercept Point) easureent usin two in-band tones that are close in frequency with f 0 =0MHz An IIP3 of 5 dbvp is achieved Repeatin this test near f 0 =0MHz, the IIP3 drops to 7 dbvp and is shown in Fi 7 The SFDR plot for peak to peak input voltae of 300V wrt 0MHz input is shown in Fi 8 It can be noted fro this fiure that the upper bound on THD is -40dB (%) for 300Vpp sinal swin Fi 9 shows the equivalent input referred noise of the filter The total input referred interated noise is coputed to be 55µVrs This yields 66 db dynaic rane The siulation results of the proposed desin are copared with other filter realizations and are reported in Table The proposed filter consues 4 ties less power than that of [0] without any coproise on other paraeters The input referred noise of the source follower filter is 5 ties hiher than that of [0] is due to the fact that the ain of the source follower architecture is lesser than the forer 5 CONCLUSIONS A reconfiurable continuous tie low pass filter based on source follower is ipleented in TSMC 08 µ diital CMOS process Due to the subthreshold operation of the filter ore than two fold reduction in power is achieved than that of [0] The desined low pass filter features a ood center frequency tunin fro 00KHz to 0MHz which covers the frequency rane correspondin to analo baseband filters used in the physical layer of various wireless networks such as WLAN a/b/, UMTS, Bluetooth, GSM and CDMA Since the analo baseband circuit not only requires lower area and power, but also has a ood reconfiurablity, it is a stron candidate for utilization as one of the buildin blocks for SDR transceivers Fi Half circuit noise odel for source follower filter Fi 3 Seven bit CSDAC Fi 4 Manitude response of the filter for various DAC settins Fi Second order source follower filter Fi 5 Output voltae of CSDAC for counter input

5 Table Perforance suary Paraeters [0] This work Fi 6 IIP3 plot for in band tones (f 0 = 0MHz) Fi 7 IIP3 plot for in band tones (f 0 = 0MHz) Technoloy 03µ CMOS Filter nd order Butterworth 08µ CMOS Supply voltae V V IIP3 Input referred noise BW (Proraable) 36µVrs 00KHz to 0MHz nd order Butterworth 55 µvrs Tunin rane 00 >00 Active area KHz to 0MHz Power 4W 095W THD=- 40dB DR@ THD -40dB 00V 68dB 300V 66dB Fi 8 SFDR plot for 300Vpp, 0MHz input Fi 9 Input referred noise of the filter REFERENCES [] V Giannini, J Craninckx, A Baschirotto, Baseband Analo circuits for Software Defined Radio, Spriner, New York, 008, chapter 5 [] M Laueois, Reconfiurability Approach on Hardware Desin for MTS Terinal, MUMOR Project, Lausanne, 004 [3] Workshop on Multi-Mode Multi-Band Re-Confiurable Systes for 3 rd Enhanced Generation Mobile Phones, MUMOR Project Leuven, Beliu, 004 [4] SD Aico et al, Low-power reconfiurable baseband block for UMTS/WLAN transitters, Proc Of NORCHIP, pp 03-06,Noveber 004 [5] Stefano D Aico, Vito Giannini, and Andrea Baschirotto, A 4th-Order Active-G-RC Reconfiurable (UMTS/WLAN) Filter, IEEE JSolid- State Circuits, vol 4, pp , July 006 [6] VGiannini, J Craninckx, J Copiet, B Coe, S D Aico,ABaschirotto, Flexible baseband Low-Pass Filter and Variable Gain Aplifier for Software Defined Radio Front End, Proc Of ESSCIRC006, pp 03-06, Septeber 006 [7] D Chala, A Kaiser, A Cathelin, and D Belot, A G- C low-pass filter for zero-if obile applications with a very wide tunin rane, IEEE J Solid- State Circuits, vol 40, no 7, pp , Jul 005

6 [8] B Nauta, A CMOS transconductance-c filter technique for very hih frequencies, IEEE J Solid-State Circuits, vol 7, pp4 53, Feb99 [9] F Munoz, A Torralba, R G Carvajal, and J Rairez- Anulo, Two new VHF tunable CMOS low-voltae linear transconductors and their application to HF -C filter desin, in Proc ISCAS, May 000, ppv [0] P Crobez, J Craninckx, Piet Wabacq and M Steyaert, A 00-KHz to 0-MHz Reconfiurable Power-Linearity Optiized G C Biquad in 03 CMOS, IEEE Transactions on Circuits and Systes II: Express Briefs, vol 55, Mar 008, 33, pp4-8 [] S D Aico, Matteo Conta, and Andrea Baschirotto, A 4-W 0-MHz Fourth-Order Source- Follower-Based Continuous-Tie Filter with 79-dB DR, IEEE JSSC, vol4,no,pp 73-78, Dec 006