LINEARIZATION AND EFFICIENCY ENHANCEMENT TECHNIQUES FOR RF AND BASEBAND ANALOG CIRCUITS. A Dissertation MOHAMED SALAH MOHAMED MOBARAK

Transcription

1 INEAIZATION AND EFFIIENY ENHANEMENT TEHNIQUES FO F AND BASEBAND ANAOG IUITS A Dissertation y MOHAMED SAAH MOHAMED MOBAAK Suitted to the Office of Graduate Studies of Texas A&M University in partial fulfillent of the requireents for the deree of DOTO OF PHIOSOPHY Deceer Maor Suect: Electrical Enineerin

2 INEAIZATION AND EFFIIENY ENHANEMENT TEHNIQUES FO F AND BASEBAND ANAOG IUITS A Dissertation y MOHAMED SAAH MOHAMED MOBAAK Suitted to the Office of Graduate Studies of Texas A&M University in partial fulfillent of the requireents for the deree of DOTO OF PHIOSOPHY Approved y: hair of oittee, oittee Meers, Head of Departent, Edar Sanchez-Sinencio Jose Silva-Martinez Prasad Eneti Mahoud El-Halwai ostas N. Georhiades Deceer Maor Suect: Electrical Enineerin

3 iii ABSTAT inearization and Efficiency Enhanceent Techniques for F and Baseand Analo ircuits. (Deceer ) Mohaed Salah Mohaed Moarak, B.S., airo University, Eypt; M.S., airo University, Eypt hair of Advisory oittee: Dr. Edar Sanchez-Sinencio Hih linearity transitters and receivers should e used to efficiently utilize the availale channel andwidth. Power consuption is also a critical factor that deterines the attery life of portale devices and wireless sensors. Three ase-and and F uildin locks are desined with the focus of hih linearity and low power consuption. An architectural attenuation-predistortion linearization schee for a wide rane of operational transconductance aplifiers (OTAs) is proposed and deonstrated with a transconductance-capacitor (G-) filter. The linearization technique utilizes two atched OTAs to cancel output haronics, creatin a roust architecture. opensation for process variations and frequency-dependent distortion ased on olterra series analysis is achieved y eployin a delay equalization schee with on-chip proraale resistors. The distortion-cancellation technique enales an IM iproveent of up to db copared to a coensurate OTA without linearization. A

4 iv proof-of-concept lowpass filter with the linearized OTAs has a easured IM < -7dB and 54.5dB dynaic rane over its 95MHz andwidth. Desin ethodoloy for hih efficiency class D power aplifier is presented. The hih efficiency is achieved y usin hiher current haronic to achieve zero voltae switchin (ZS) in class D power aplifier. The atchin network is used as a part of the output filter to reove the hih order haronics. Optiu values for passive circuit eleents and transistor sizes have een derived in order to achieve the hihest possile efficiency. The proposed power aplifier achieves efficiency close to 6% at 4 MHz for -db of output power. Hih efficiency class A power aplifier usin dynaic iasin technique is presented. The power consuption of the power aplifier chanes dynaically accordin to the output sinal level. Effect of dynaic ias on class A power aplifier linearity is analyzed and the results were verified usin siulations. The linearity of the dynaically iased aplifier is iproved y adustin the preaplifier ain to uarantee constant overall ain for different input sinal levels.

5 v DEDIATION To the eory of y other To y father To y rothers and sisters To y wife For all their love and support

6 vi AKNOWEDGEMENTS I would like to express y deep ratitude to y advisor, Dr. Edar Sanchez- Sinencio, for his uidance and support throuhout the course of y research. His valuale coents and encouraeent ade this research possile and I deeply appreciate his iediate help in solvin any proles that I have faced durin y studies. I would like to thank Dr. Jose Silva-Martinez for ein a eer of y coittee and for his valuale input, suestions and coents especially on the G- filter linearization proect. I also would like to thank y coittee eers Dr. Prasad Eneti and Dr. Mahoud El-Halwai for their tie and valuale coents. I a rateful to Marvin Onaao for ein a ood friend and for his sinificant contriution to the G- filter proect. I also would like to express y appreciation to Erik Pankratz, Mohaed El-Nozahi, Hen Zhan, Jason Wardlaw, Mohaed Elsayed, and Mohaed Adul-atif for their valuale discussions. I enoyed the copany and discussions with any friends includin Faraarz Bahani, Faisal Hussien, Marvin Onaao, Mohaed Elsayed, Mohaed Adul-atif, Mohaed El-Nozahi, Ahed Aer, Eha Sohy, Ahed Hely, ay Saad, Ayen Aeen, Ahed aa, and Jason Wardlaw. Their help and encouraeent was an essential factor for e durin y study. I a indeted for y faily for their love, support, patience, and encouraeent throuhout y studies.

7 vii TABE OF ONTENTS Pae ABSTAT... DEDIATION... AKNOWEDGEMENTS... TABE OF ONTENTS... IST OF FIGUES... IST OF TABES... iii v vi vii ix xiii HAPTE I INTODUTION.... Motivation.... Dissertation Oranization... II ATTENUATION-PEDISTOTION INEAIZATION OF MOS OTAS FO OTA- FITE APPIATIONS Introduction Attenuation-Predistortion inearization Methodoloy Sinle-Ended ircuits Fully-Differential ircuits..... Scalin of Attenuation atios olterra Series Analysis ircuit evel onsiderations Fully-Differential OTA with Floatin-Gate FETs oon-mode Feedack Desin Proof-of-oncept Filter ealization opensation for PT ariations and Frequency-Effects....6 Measureent esults OTA Second Order ow Pass Filter Excess Phase opensation inearization without Power Budet Increase... 47

8 viii HAPTE III Pae HIGH EFFIIENY ASS D POWE AMPIFIE FO OW POWE APPIATIONS Introduction Hih Efficiency Power Aplifier Architectures lass E PA lass D PA Zero oltae Switchin in lass D PA ircuit evel Ipleentation lass D PA ircuit PA Driver ircuit Measureent esults I HIGH EFFIIENY ASS A POWE AMPIFIE WITH DYNAMI BIAS ONTO Introduction Dynaic Bias of lass A Power Aplifier Dynaic Bias Effect on Aplifier inearity Efficiency Iproveent Usin Dynaic Bias Power Aplifier ircuit Ipleentation Envelope Detector Desin Operational Aplifier Desin Experiental esults... ONUSIONS... 8 EFEENES... ITA... 6

9 ix IST OF FIGUES FIGUE Pae. Block diara of cross coupled aplifiers Block diara of the proposed attenuation-predistortion technique Attenuation-predistortion linearization schee for sinle-ended circuits..4 Block diara of the fully differential iplantation of the attenuationpredistortion technique....5 Attenuation-predistortion linearization for fully-differential circuits....6 ow-frequency odel for the fully-differential attenuation-predistortion schee Non-linear odel for fully-differential attenuation-predistortion cancellation Folded-cascode OTA (ipleents G in the ain and auxiliary paths)....9 (a) Error aplifier circuit in the MFB loop and () sall-sinal equivalent circuit Fully-differential nd -order lowpass filter diara and desin paraeters Block diara of the proposed autoatic linearity tunin schee Siulated A aplitude at the input of the ain OTA (PD in Fi..) efore and after adustent of resistor c to its optiu value. (The voltae at PD is ideally equal to x = k in ) Sensitivity of IM (in dbc) to coponent isatches calculated with equation (.5): (a) MHz sinal frequency, () MHz sinal frequency...

10 x FIGUE Pae.4 Siulations showin sensitivity to variation and isatch of critical coponents: (a) IM vs. chane in c (Fi..5) at 5MHz, () IM vs. (in Fi..5) with % transconductance isatch etween ain OTA and auxiliary OTA at 5MHz....5 Measured linearity with. p-p input swin fro two tones, each. p-p (-6dB) on-chip after accountin for off-chip losses at the input: (a) reference OTA, () copensated OTA Measured IM vs. input peak-peak voltae for reference OTA and copensated OTA otained usin two tones havin khz separation around 5MHz Measured IM dependence of the copensated OTA on phase shift otained with two test tones havin khz separation around 5MHz. (The least sinificant it of the diital control code chanes the value of phase shift resistor c y ~%) Filter easureents: (a) transfer function with ~4dB total losses (input loss and output uffer attenuation). () IM with. p-p input swin fro two tones, each. p-p (-6dB) on-chip after accountin for off-chip input losses Measured filter IM vs. frequency with two test tones havin khz separation Measured IM vs. input peak-peak voltae for the linearized filter otained with two test tones havin khz separation around 5MHz Measured in-and intercept point curves for the filter: (a) IIP [two tones, Δf = khz around 5MHz], () IIP [two tones, Δf = khz around MHz] Measured out-of-and intercept point curves for the filter: (a) IIP [f = 75MHz, f = 75MHz, f IM = MHz], () IIP [f = 75MHz, f = 75.MHz, f IM = khz] Die icroraph of the OTAs and filter in.μ MOS technoloy. (eference OTA area:., linearized OTA area:.9 ) Sinle-ended equivalent lock diara of a andpass iquad... 45

11 xi FIGUE Pae.5 BP filter siulations with different s values for excess phase copensation: (a) frequency responses, () quality factor and center frequency; where s = sa = sb ( B A ) lass E power aplifier lass D power aplifier oltae and current wavefors of class D power aplifier Soft switchin in class D power aplifier Step down atchin network Step up atchin network Proposed current wavefors in soft switched class D power aplifier Power aplifier driver circuit lass D PA chip icroraph PB of class D power aplifier PB trace odel Output power versus supply voltae Power aplifier efficiency versus supply voltae Frequency response of power aplifier Power aplifier efficiency at different frequencies Power aplifier output for FSK odulated sinal Doherty aplifier concept Envelop eliination and restoration inear aplification usin non linear aplifier (outphasin technique)... 77

12 xii FIGUE Pae 4.4 Envelope feedack artesian feedack Feedforward linearization Second and fourth order approxiations of the asolute value function Power aplifier linearization usin envelope sinal Third order inter-odulation versus input aplitude for different control schees Fifth order inter-odulation versus input aplitude for different control schees Third order inter-odulation versus input aplitude with iproved control schee Fifth order inter-odulation versus input aplitude with iproved control schee Efficiency enhanceent throuh dynaic ias of the power aplifier Power aplifier scheatic Envelope detector scheatic Dynaic ias aplifiers: (a) Gain stae of preaplifier (G a ), () Gain stae of power aplifier (G ) Two stae op-ap scheatic Frequency response of the operational aplifier Power aplifier chip icroraph Gain of the reference power aplifier Gain of the power aplifier with dynaic ias only at the output stae Gain of the proposed dynaically iased power aplifier...

13 xiii FIGUE Pae 4. Efficiency of the proposed dynaic ias aplifier and the reference aplifier Power consuption of the proposed dynaic ias aplifier and the reference aplifier Third order inter-odulation of the proposed and the reference aplifiers Fifth order inter-odulation of the proposed and the reference aplifiers... 6

14 xiv IST OF TABES TABE Pae. Measured ain paraeters of the reference folded-cascode OTA oparison of OTA linearity and noise easureents OTA coparison with prior works oparison of wideand G - lowpass filters Siulated coparison: OTA linearization without power consuption increase Transistor paraeters PA circuit coponent values... 67

15 HAPTE I INTODUTION. Motivation Internet, sart phones, and loal positionin syste (GPS) naviation have ecoe an essential part of our daily lives. Advances in counication technoloies enaled the interation of ultiple features to a sinle device, for exaple oile phones are used to transfer videos as well data over the internet and they can e used as GPS naviation devices eside their ain use of transittin voice sinals. Moreover, any new applications that utilize wireless andwidth have recently eered such as satellite counications which is ein used to provide iportant services to reote locations. These advances in wireless systes led to a very crowded wireless spectru. The aount of data required to e transitted over the wireless connections has increased sinificantly while the availale andwidth is very liited. New techniques ust e used in order to allow hih data rate transission over the availale andwidth and to extract the weak sinal received in the presence of stron interference. ow noise receivers are necessary to distinuish the received sinal fro the noise level. On the other hand, hih linearity receiver is required to iniize the effect of the interferin sinals over the desired sinal. This dissertation follows the style of IEEE Journal of Solid-State ircuits.

16 ow power operation is also desired for oile transceivers. In soe applications, such as sensor networks or iplantale edical sensors, power consuption is a crucial factor when desinin the transceiver uildin locks. The oal of this research is to develop new circuits and techniques to uild hih linearity receivers and hih efficiency transitters. While the noise contriution of the first lock in wireless receiver is the ost critical copared to the rest of the receiver, the nonlinearity of ase-and locks in wireless receivers is the doinant source of nonlinearity in the whole receiver. On the transitter side, the power aplifier efficiency is one of the aor factors that deterine the whole transitter power consuption. New circuit techniques has een proposed for the followin ase-and and F locks ) Hih linearity ase-and filter usin attenuation-predistortion linearization technique for the use in wide-and receivers. ) Hih efficiency class D power aplifier for low output power applications. ) Hih efficiency class A power aplifiers with dynaic ias control for hih linearity transitters in applications that involve envelope odulated sinal transission.. Dissertation Oranization hapter II discusses the developent of new architectural technique for the linearization of operational transconductance aplifiers (OTA) that is used as a part of OTA- filters. Since there is an increasin deand of hiher data rate and consequently

17 wider channel andwidth, the hih frequency effects associated with the proposed techniques is analyzed and frequency copensation schee is proposed. Tradeoff associated with the proposed techniques, effect of process-voltae-teperature (PT) variations is also provided in details. Measureent result of a standalone operational transconductance aplifier is presented and copared to a reference transconductance aplifier faricated on the sae chip that doesn t utilize the proposed linearization technique. esults of second order low pass filter that is uild usin the proposed OTA is also iven. Desin of hih efficiency switchin power aplifiers is addressed in hapter III with a description of the advantaes and the disadvantaes of different power aplifier classes. Efficiency analysis of class D power aplifier is provided and optiization of class D efficiency for low power applications is iven. The hih efficiency operation is verified with the easureent results of a 4 MHz class D power aplifier. hapter I presents a study of class A power aplifier dynaic iasin and its effect on the aplifier linearity. Hih efficiency and hih linearity operation of class A power aplifier usin dynaic iasin is proposed. inearity enhanceent usin dynaic ias is analyzed and easureent results for dynaically iased class A aplifier is provided. onclusions are suarized in hapter and possile areas of future work are also presented.

18 4 HAPTE II ATTENUATION-PEDISTOTION INEAIZATION OF MOS OTAS FO OTA- FITE APPIATIONS*. Introduction Operational transconductance aplifiers (OTAs) are essential eleents of transconductance-capacitor (G -) filters []-[], ΔΣ odulators [4], yrators, varialeain aplifiers, and neative-resistance eleents. opared to their active- counterparts, G - filters enale low-power operation and tunin of the filter characteristics at hiher frequencies, ut are less linear. Tunale active- filters are suitale for low-frequency applications (e.. <MHz in [5]); however, extendin their use to hiher frequencies would require sinificantly ore power. On the other hand, OTA-ased filters in wireless receivers and continuous-tie (T) ΔΣ analo-to-diital converters (ADs) increasinly andate ood linearity at hiher frequencies. These applications typically require hihly linear OTAs with third-order inter-odulation (IM) distortion etter than -6dB. Further advances in hih-frequency G - filters with SNDs over 5dB are also desirale for channel selectionequalization in ulti-gps portale data counication devices [], and for possile application in next eneration analo-to-inforation receivers with dynaic rane > 9dB in MHz andwidth [6]. * IEEE. hapter II is in part reprinted, with perission, fro Attenuation-predistortion linearization of MOS OTAs with diital correction of process variations in OTA- filter applications, M. Moarak, M. Onaao, J. Silva-Martinez, and E. Sánchez-Sinencio, IEEE J. Solid-State ircuits, vol. 45, no., pp. 5-67, Fe.. For ore inforation o to

19 5 iale hih-frequency G - filter solutions were presented in [] and [7] with - db frequencies at 75MHz and 84MHz, respectively. The topoloy reported in [] has low noise, liited linearity, and a pseudo-differential realization prone to low power supply reection ratio (PS). The filter in [7] achieves hih linearity with relatively low power ut hiher noise. Trade-offs etween linearity, noise, power, and operatin frequency are coon and have een incorporated into fiures of erit (FOMs) such as in [8] and [9]. The filter cutoff frequency tunin rane can also e incorporated into a FOM [], which aids in the coparison of G - filters for applications in which reconfiuraility is iportant; e.. wide tunin capaility such as the 5: rane in [] is eneficial in ulti-standard receivers. ecent works also address alternative filter structures such as the source-follower-ased approach [] and perforance iproveent of typical OTA topoloies []. A popular linearization approach is to cross-couple two transconductors, theoretically cancellin certain haronics at specific ias conditions over a liited frequency rane. Non-linearity cancellation with two devices in parallel has een successfully extended to narrow-and F transconductors in []. A typical crosscoupled OTA contains two paths; each havin different transconductance and the sae aount of haronic distortion as illustrated y the lock diara in Fi... When cross-coupled, the equal haronics cancel under ideal conditions and the effective transconductance is the difference etween the two paths. The frequency dependence of this approach has een analyzed with olterra series in [4], in which the analytical expressions are correlated with easureent results. Process-voltae-teperature (PT)

20 6 variations, hih-frequency effects, and device odelin inaccuracies will create unforeseen isatches etween the two aplifiers. Therefore, precision tunin of ias currentsvoltaes is typically required. Sinal attenuation can e also used to linearize the aplifier in the expense of ain reduction. Attenuation and cross-couplin has een coined for the low-noise aplifier in [5], in which distortion cancellation is restricted to third-order non-linearities with feedforward path and precise off-chip input attenuation. Accurate odelin of frequency-dependent distortion characteristics on the MOSFET device level is presented in [6]. y =a +a x+a x +... x + y t =(a - )+(a - )x y = + x+ x ross oupled aplifiers (a = ) Fi... Block diara of cross coupled aplifiers. For a source coupled differential pair iased y a current source I D, the differential output current is expressed in ters of the differential input voltae v d as I o v d I D v d 4, where β = μ ox W, μ is the electron oility, ox is the ate oxide per unit area, W is the transistor width, and is the transistor lenth. The ias

21 7 current of the differential pair can e adusted dynaically in order to linearize the OTA [7]. If the ias current I D is adusted such that I D = I D +(β4)v d, then the output current is linearly proportional to the input differential voltae v d and it is iven y I o v d I D. However, in deep suicron technoloies, other third order nonlinearities arise fro short channel effects which were nelected in the previous analysis and thus finite third order nonlinearities will not e cancelled y this technique. The proposed ethodoloy is an architectural solution that achieves up to db IM iproveent over an identical non-linearized OTA desin at frequencies as hih as 5MHz. It can e eneralized to fully-differential topoloies which offer hiher PS and coon-ode reection ratio (M). Since the axiu frequency is ainly liited y process parasitics and OTA perforance, the approach shows proise of exceedin 5MHz andwidth in future nanoscale MOS processes. oust linearization over a wide frequency rane deands a echanis to correct for hihfrequency effects and PT variations, for which a diital proraaility schee is proposed.. Attenuation-Predistortion inearization Methodoloy Sinal attenuation at the OTA input [4] reduces the effective transconductance and decreases the SN. Alternatively, distortion cancellation y eans of cross-coupled differential pairs results in increased power consuption and noise proportional to the transistor paraeters in the additional path. Since the extra differential pair norally has less transconductance than the ain pair, the effective transconductance is reduced y

22 8-5%. However, oth transistor pairs should have the sae third-order non-linearity, which translates into different transistor sizes and ias currents for each pair. As a result, the cross-couplin technique is sensitive to PT variations and restricted to narrow frequency ranes. Another coon ethod to linearize a transistor havin transconductance is to add a deeneration resistor sd at the source [4], which akes the third-order haronic distortion proportional to the factor (+ sd ). Nonetheless, lare deeneration resistance results in hiher input-referred noise, lower transconductance, and less voltae headroo. The effective transconductance ( sd ) and the input-referred noise (v nsd) with resistive source deeneration are iven y sd sd, v nsd 4KT sd, (.) where the noise coefficient γ was approxiated as. For exaple, usin a deeneration factor sd = will ideally result in IM iproveent of approxiately 9dB, an input-referred noise power increase y a factor of 4, and a decrease of the transconductance to one third of its oriinal value. But ased on siulations of the OTA fro this work with sd =, the expected IM iproveent would e 5.dB with an associated noise power increase of ore than 9 ties. The proposed attenuation-predistortion [8] ethod is independent of OTA topoloy and involves cancellation of all distortion coponents except those fro secondary effects at hih frequencies. It can e used in conunction with other circuitlevel linearization techniques internal to the OTA, such as source deeneration or crosscouplin.

23 9.. Sinle-Ended ircuits The proposed linearization schee is illustrated in Fi.. where the non-linear syste is linearized y sutractin the haronics created in an identical syste. Fi.. depicts the sinle-ended architecture that contains an auxiliary ranch with an OTA havin identical diensions, D ias, and A coon-ode conditions as in the ain path to enerate the distortion coponents required for cancellation. x Phase Delay x + x-d - Nonlinear syste x+d-d x - + x Nonlinear Syste + Delay x+d Fi... Block diara of the proposed attenuation-predistortion technique. An iportant advantae of identical paths is roustness to PT variations ecause of optial device atchin otainale fro proper layout. In this schee, it is avoided to ase the distortion cancellation on ranches with different transconductor device diensions or ias conditions, which would derade atchin accuracy. But even with iniized isatches, non-linearities are particularly frequency-dependent at hih frequencies and reain sensitive to PT variations as estalished in Section.5.

24 Hence, the proposed linearization ethod involves variale resistors to tune perforance and counteract hih-frequency deradation as well as PT variations. Either a resistive or capacitive divider can for the attenuator at the input of the auxiliary path; however, resistors add ore noise. D D D D D4 D5 phase shifter i diitally proraale resistor ladder in phase shifter x dif ain path i out G i aux = G in + i non-lin { in } x = in + i non-lin { in } x dif = in - i non-lin { in } G i out G in + i non-lin { in } - i non-lin { in } auxiliary path o * i non-lin { } represents the distortion coponents of the current enerated y G with input voltae aplitude in G i aux =G Fi... Attenuation-predistortion linearization schee for sinle-ended circuits. Distortion cancellation in the sinle-ended case requires G =, which is ascertained y the followin analysis. For a certain input voltae aplitude, the output current can e divided into a linear part i lin { } = G and a non-linear part i non-lin { } = , where,, are Taylor series coefficients of the transconductance. The differential input of the ain OTA is: dif = in [ in + i non-lin { in }G ] = in i non-lin { in }G. Under ideal conditions, the distortion

25 enerated in the auxiliary path, -i non-lin { in }, cancels out the distortion in the ain voltae-to-current conversion. In practice, distortion caused y non-linearities at the output of the auxiliary OTA and hih-frequency effects introduces soe finite uncancelled distortion. apacitor o represents the luped output capacitance of the auxiliary OTA, input capacitance of the ain OTA, and layout parasitics. esistor c of the phase shifter and equivalent input capacitance i provide st -order frequency copensation, creatin a pole to equalize the phase shift etween the ain and auxiliary paths. opensation is necessary at hih frequencies ecause parasitic capacitance o at the neative input terinal of the ain OTA creates a pole with resistor in the auxiliary path... Fully-Differential ircuits A conceptual diara of the proposed linearization approach for a fullydifferential transconductor (G ) and the correspondin circuit diara are displayed in Fi..4 and Fi..5 respectively. In the fully-differential case, attenuation factors at the input of the transconductors are chosen such that it can e realized with floatin-ate devices as descried in Section.4.. As discussed in [4], [9] and [], the inherent input attenuation with floatinate staes enhances the OTA linearity. The distortion cancellation principle is the sae as in the sinle-ended case, ut different conditions ust e satisfied for fullydifferential ipleentation, which are explained in Sections.. and.4. with reards to the attenuation ratios.

26 x Phase Delay + - Nonlinear syste x-d+d x x Nonlinear Syste + Delay Fi..4. Block diara of the fully differential iplantation of the attenuationpredistortion technique. phase shifter D D D D D4 D5 diitally proraale resistor ladder in+ phase shifter i aux = G in + i non-lin { in } x = in + G x i non-lin { in } dif = in - i non-lin { in } G in- G auxiliary path i aux = G (di. pro.) phase shifter o x dif 4 ain path p G i out G in + i non-lin { in } - i non-lin { in } i out i out * i non-lin { } represents the distortion coponents of the current enerated y G with input voltae aplitude Fi..5. Attenuation-predistortion linearization for fully-differential circuits.

27 By selectin an input attenuation ratio of and voltae ain of in the auxiliary ranch (G = ), the sinal aplitude x is equal to in plus three ties the distortion coponents caused y the non-linear current i non-lin { in } fro the transconductor with input aplitude of in. In the ain path, the effective differential OTA input is: dif = in x = in [ in + i non-lin { in }G ] = in i non-lin { in }G. Thus, the differential sinal contains the attenuated input sinal and the inverse of the distortion enerated y the identical G in the auxiliary ranch for distortion cancellation durin the voltae-to-current conversion in the ain path. Ideally, the distortion coponents are canceled y the equal and opposite ters fro the predistortion of the differential input sinal except for neliile hiher-order coponents. o in Fi..5 represents the equivalent differential capacitance of all parasitic capacitances at the output of the auxiliary OTA and p is the differential equivalent of the parasitic capacitances at the input of the ain OTA. Expressions for optiu distortion cancellation at hih frequencies are provided in Section.. inear phase shifter networks are chosen for the frequency copensation ipleentation in order not to affect the cancellation schee. esistors and c are tuned with 6-it resolution to copensate for isatchespt variations. The phase shifter lock is utilized to equalize the delay fro the input to suin nodes and 4 in Fi..5. Furtherore, the phase shifter enales optiization of the non-linearity cancellation ased on hih-frequency effects.

28 4.. Scalin of Attenuation atios Dependin on application-specific requireents, the desin paraeters in the attenuation-predistortion linearization approach can e selected to adust the voltae swins and the effective transconductance. Fi..6 shows the fully-differential attenuation-predistortion linearization schee, where frequency copensation and parasitic capacitors have een oitted for siplicity. in+ k -k auxiliary path ink G dif G x i out k -k k Fi..6. ow-frequency odel for the fully-differential attenuation-predistortion schee. The followin analysis assues floatin-ates as a practical attenuator ipleentation choice under the constraint that factors k and (-k ) are related as elaorated upon in Section.4., ut less restrictive types of attenuators could also e

29 5 used. As entioned efore, the output current i o of an OTA due to an input voltae can e odeled as havin a linear and a non-linear part: i o = G + i non-lin { }. Inorin hih-frequency and secondary effects, the followin relation can e written: i out G i k k k G in k { k k k G } nonlin in G i nonlin { k in }, (.) where: i non-lin {k in } (-k ) << (k -(-k )k G ) in is assued in the approxiation. To cancel the distortion, the followin conditions should hold: i) The auxiliary and ain OTAs should have the sae effective input voltae aplitudes such that an identical distortion is created at their respective outputs. ii) The ain in the auxiliary path ust ensure that the distortion throuh this sinal path reaches the output of the ain OTA with a ain of -. iii) The internal sinal swins should e ounded, i.e.: kg (.) Applyin conditions i) and ii), cancellation of the non-linear ters in (.) requires: ( k k ) G, k (.4) onsequentially, the effective transconductance with linearization is iven y k k k GG k G k G Geff (.5) ondition iii) depends on the application and is not always necessary. ancellation of distortion with the proposed technique requires weakly non-linear operation in the auxiliary ranch, which is ensured y liitin the sinal swin with this condition. The exaple that is presented in Fi..5 was derived with k G =,

30 6 ensurin that the sinal swin at the output of the auxiliary OTA is the sae as at its input. This choice was ade to aintain the sae axiu input voltae swin as the initial OTA without saturatin the OTA in the linearization path. If the specified input sinal is k G ties elow the OTA saturation level, then k can e increased accordinly to otain k G > and hiher effective transconductance ased on (.5). But, this choice is only perissile if a reduction of the axiu input swin y k G can e tolerated, which would iply a reduction in the dynaic rane. Typically, choosin k G = is advantaeous to aintain the sae axiu input voltae swin as the oriinal OTA after linearization. Selection of k = and k = results in the hihest effective transconductance that can e achieved in (.5) ased on the aove conditions while also satisfyin the attenuation factor relationships in the floatin-ate devices (Section.4.) with identical sinal swins at the input and output of the auxiliary OTA (k G = ). Hence, G = under the stated conditions.. olterra Series Analysis The precedin expressions are valid at low frequencies and ive insiht into the conditions to cancel total distortion when secondary effects are neliile. olterra series analysis [] is used to find the optiu copensation resistor value for linearization at hih frequencies. Eployin a rd -order odel of transconductor nonlinearity, the siplified odel of the proposed attenuation-predistortion linearization technique is shown in Fi..7. In this analysis, represents the linear transconductance and the third-order coponent. esistor ( c ) copensates for

31 7 hih-frequency linearity deradation y equalizin the delays in the ain and auxiliary paths. k (-k ) in+ ink i out i i + - i + i k (-k ) i out o k i + i p o Fi..7. Non-linear odel for fully-differential attenuation-predistortion cancellation. The differential voltae i (t) at the input of the ain OTA is iven y ) ( )] ( [ ) ( ) ( c k k t c k k t k t k t o p in c p in in i, (.6) k k k k k c k k k k p c o p c o c p o p p c p c where :.

32 8 Followin the sae analysis as in Section.. ut takin the parasitic capacitances p and o into account, the conditions for distortion cancellation at low frequencies are: k k k p p, (.7) With the aove provisions, the output current of the ain OTA after aleraic siplifications is: ) ( ) ( ) ( )] ( [ ) ( ) ( c k k t k c k t k c k k k t t t t i o c p in c p in o c p in i i out (.8) Assuin weakly non-linear operation ased on condition iii) in Section.. and that the sinal can e expressed as a su of sinusoids with noncoensurate frequencies, the haronic input ethod can e applied to calculate the olterra series coefficients [] and theoretically deonstrate the non-linearity cancellation with the proposed schee. Takin a sinle input t in e t ) ( and sustitutin into (.8) to express the linear transfer function H : c k k k H o c p (.9) Selectin t t t in e e e t ) ( and akin the appropriate sustitutions for calculation of the third-order transfer function (H ) yields the followin equality after

33 9 expansion and oission of all ters that do not contain the exp(ω t + ω t + ω t) factor relevant to H : ),, ( c k k c k k c k k c k k k H c p o c o c o c p (.) The aplitude of the third haronic distortion (HD) current due to a sinusoidal input sinal in sin( t) is iven y ),, ( 4 c k k c k k k H i c p in o c p in in o (.) Eliination of HD requires that i o =, hence 9 c k c k k c o c (.) The cuic root in (.) can e approxiated with x x for x <<. Thus, HD to cancel k k c k c k k o c c o c (.)

34 For a two-tone input sinal of the for in sin( t)+ in sin( t), the IM current can e deterined with olterra series accordin to the followin equation: 4 4 ),, ( 4 c k k c k k c k k k H i c in in p o c o c in in p in in IM (.4) Siplifyin i IM for two interodulation tones that are close toether (ω ω ω ω ) yields: 4 4 IM o c c in in p o c o c p in in IM i for k k c k k c k k c k k k i (.5) In the discussed exaple case with k =, the condition to cancel IM with the phase shifter lock in Fi..5 is c =(4)*(+6 o ). To ensure hih linearity with variations of parasitic capacitances, the proraale rane of c is selected ased on process corner siulations as descried in Section.5.

35 .4 ircuit-evel onsiderations.4.fully-differential OTA with Floatin-Gate FETs Fi..8 displays the scheatic of the OTAs ipleented on the.μ MOS test chip with a. supply, and its coon-ode feedack (MFB) circuit. dd I I FG + o- G G - o+ + FG M c FG M c - FG I ctr ctr o- MFB o+ c + FG - FG G pt ref Error Aplifier Floatin-Gate Devices: equivalent load seen at i+ i- +- Fi..8. Folded-cascode OTA (ipleents G in the ain and auxiliary paths). Attenuators k, (-k ), and k are realized with floatin-ate devices for attenuation-predistortion linearization of this fully-differential topoloy. The ates (G) of the standard NMOS transistors in the OTA core are not resistively iased and are only connected to two conventional etal-insulator-etal (MIM) capacitors. Fi..8 also

36 visualizes the equivalent capacitive load seen at the + and - inputs, where pt represents the effective ate-to-round (A) capacitance fro transistor parasitic capacitances. With this confiuration, the ate voltaes are: G+- = ( FG total ) +- + ( FG total ) +-, where total FG + FG when pt is neliile. It follows that the attenuation factors in Fi..6 are: FG total = k and FG total = ( total - FG ) total = - k. The accuracy of the k and (-k ) factors predoinantly depends on the atchin of the MIM capacitors FG and FG, which can e achieved within.-% usin proper layout techniques. As assessed in Section.5, such a atchin accuracy is ore than sufficient with the %-step proraaility of resistor for ain isatch copensation in oth paths. In the layout, all nodes G at the floatin ates in Fi..8 are connected to the top etal layer usin standard poly-etal contacts and etal-etal vias. Durin farication, this connection ensures that any chare stored on the floatin ates flows to the sustrate ecause all connections to the top etal are still oined prior to their separation durin the last etchin step. Thus, no chare is stored on the floatin ates when the sustrate contacts are also connected to the top etal layer [], allowin ate dischare into the sustrate efore the last etchin operation. After etchin, the top etal extensions of the ates without trapped chare are floatin, leavin only the connections to the two MIM capacitors. The floatin-ate device desin expressions for k and (-k ) aove are assuin asence of excess chare on the floatin ates, which is a satisfied condition without extra farication steps as a consequence of the ate and sustrate connections to the top etal. A special prorain technique for non-zero chare on the floatin

37 ates was not utilized in this work, ut a ore sophisticated floatin-ate device ipleentation as presented in [9] could e explored, which proises additional potential for copensation of inherent transistor threshold voltae offsets in the OTA s input differential pair. The phase shifter in Fi..5 creates an extra pole within the linearized architecture that the reference OTA does not have. This phase delay is rouhly the sae as the delay fro the pole fored y and o in the auxiliary path. In low-loss (hih-q) desins, the additional pole can affect the ain of interators and the frequency response of iquad sections if ( o ) is not sinificantly larer than the operatin frequency. A load copensation schee is discussed in Section.7 for such situations. Identical standalone OTAs are included on the sae die to otain reference linearity easureents. The reference OTA also has a floatin-ate input attenuation of for fair perforance coparison. In this way, the linearity enefit fro the input attenuation is isolated fro the architectural linearization proposed in Fi..5, and oth OTAs have the sae effective transconductance (G in this case), ut the linearization results in douled power consuption. Since attenuation and feedack linearization techniques have known linearity and effective transconductance trade-offs, the circuitlevel coparison is focused on the predistortion linearization schee relative to a coensurate OTA with equal input attenuation factor. This aseline OTA in Fi..8 was iased with I =.95A and I =.85A, havin an effective transconductance of 5μA. The linearization does not require any desin chanes in this core OTA, ut redesin of the OTA is an option if it is required to eet the sae power udet after

38 4 linearization, which is possile as lon as OTA andwidth reduction can e tolerated. Such a linearization under power constraint is disclosed in Section oon-mode Feedack Desin Suppression of undesired coon-ode sinals and noise is vital for linearity at hih frequencies. The MFB circuit should have hih ain to accurately control the coon-ode output voltae while aintainin a lare andwidth to reect coonode noise in the and of interest. The MFB aplifier is shown in Fi..9, where ctr is the control voltae applied to the OTA in Fi..8. dd d d d d c ctr z ref c s ctr s z ref s I s s o o s (a) () Fi..9. (a) Error aplifier circuit in the MFB loop and () sall-sinal equivalent circuit. Nelectin the effect of the output resistance o and capacitance o of the current source I in Fi..9, the transfer function of the error aplifier is:

39 5 ctr c s s (.6) z d z d s s n s n where : ( n n z z d d s s ( z ( d ) d s ( ) ) ( z d )) The zeros of this transfer function are iven y 4 s z, z (.7) s zd and the pole locations in the transfer function are approxiately: p p ( z d d s s ( d ( s ) ) d ( d d ( ( s ) ( z z ) ( ) d d )) ) (.8) The pole p is inversely proportional to the copensation resistor z. Another pole in the MFB loop is fored at the output of the OTA: p (r o o ) -, where r o is the output resistance of the OTA and o is the load capacitance. Assuin that the MFB ain-andwidth (GBW) is larer than the two doinant poles p and p, the MFB ain-andwidth product can approxiated as GBW A p p A p (.9) ( ( ) ) z s d where A is the MFB loop ain. The effect of the two zeros on the GBW was assued to e neliile for siplicity; however their effect on the PM cannot e nelected and should e taken into account. A sall z is desired to achieve hih MFB andwidth.

40 6 However, the two zeros ( z, z ) tend to o to infinity as z approaches zero, which will have an adverse effect on phase arin. If 4, the two zeros can e approxiated as s z, z (.) zd s zd Hence, the phase arin can e estiated as follows: s z d PM tan zd A p (.) s d Thus, the addition of the copensation resistor z results in two zeros in the transfer function of the error aplifier, which helps to insure staility of the MFB loop. The siulated A response of the MFB loop has a 5.9dB low-frequency ain and a 44.9MHz unity-ain frequency with 4.5 phase arin..4. Proof-of-oncept Filter ealization A nd -order G - iquad filter was desined with attenuation-predistortionlinearized OTAs to verify that the proposed ethodoloy is suitale for filters with G - interator loops. Fi.. shows the filter scheatic and specifications. The lowpass output of the iquad was easured usin another OTA as uffer to drive the 5Ω input ipedance of the spectru analyzer. The priary otivation for diital correction (Section.5) to enhance linearity perforance with severe process variation is copatiility with diitally-controlled receiver caliration approaches that involve the aseand filter.

41 7 in+ o+ in- uf+ G G G G 4 G o- uf- MFB MFB MFB MFB MFB 5 Ω (off-chip) Fi... Fully-differential nd -order lowpass filter diara and desin paraeters. Practical ipleentation details for receivers with diital perforance onitorin and caliration of analo locks are descried in []-[5]. They incorporate accurate diital onitorin and IQ isatch correction in the diital sinal processor (DSP) as well as a few analo oservales that ive soe insihts into the operatin conditions, such as outputs fro received sinal strenth indicators or D control voltaes of locks. The possiility exists to enerate and apply test tones at the input of an analo lock and extract perforance indicators fro the output spectru in the DSP, which contains distortion coponents. onversely, caliration could also e perfored y onitorin the it error rate (BE) in the DSP fro processin a special test sequence or custoary pilot syols at the einnin of receptions. Since linearity deradation ipacts the BE, such a caliration could e coputationally ore efficient

42 8 than calculatin and analyzin the fast Fourier transfor in the DSP. eardless of the specific diital caliration alorith, the diitally-controlled correction capaility of the proposed linearization schee can potentially enale filter linearity tunin in interated receiver applications without the need for extra DAs. An alternative autoatic caliration that does not involve an on-chip DSP ut dedicated analo and sipler diital loic circuitry is displayed in Fi... in+ c k (-k ) auxiliary path x+ k G PD G k x- c (-k ) i out x+ x- in+ in- PD PD 4 PD oparison of o_d, diital control oparison of o_d, diital control ode for c ode for in- k Fi... Block diara of the proposed autoatic linearity tunin schee. Fro the conditions for optiu distortion cancellation descried in Section.., the ain of the auxiliary path ust e equal to k G, which is unity in the discussed desin exaple. This can e ensured y easurin the sinal level at the input and output of the auxiliary OTA with power or peak detectors (PD, PD ), and controllin the diital code of resistor until the ain is unity. The siplest control

43 9 alorith would e to cycle throuh the codes that deterine the value of until the difference in the D output voltaes of PD and PD is iniized, which can e perfored diitally y detectin the tolin instance at the output of a sinle coparator. At hiher frequencies, the parasitic pole in the auxiliary path starts to affect the distortion cancellation, causin the sinal level at the output of the auxiliary OTA to decrease with increasin frequency. Hence, the differential input sinal to the ain OTA at PD increases as a result, which is shown in Fi... Fi... Siulated A aplitude at the input of the ain OTA (PD in Fi..) efore and after adustent of resistor c to its optiu value. (The voltae at PD is ideally equal to x = k in ).

44 By easurin this sinal that is ideally equal to k in with PD, the value of the phase shift resistor c can e adusted until the outputs of PD and PD 4 are equal. This coparison can e copleted with the sae loic as for PD PD, ut it has to e done with an input sinal at the axiu frequency at which hih linearity is desired. The autoatic tunin has not een ipleented on the circuit level, ut siulations with different values of c showed that aplitude detection within 4.6% is required to detect c chanes within 5% at 5MHz, which is sufficient for IM hiher than 7dBc (Section.5). In differential ain easureents, PT errors in the detectors are cancelled except for the errors fro unavoidale isatches etween the two detectors. Errors fro isatches are less than 5% at.4ghz [6], and ore accurate aplitude detection is achievale at lower frequencies. In [7] for exaple, differential on-chip aplitude easureents were conducted up to.4 GHz usin detectors with a die area of. and neliile loadin of the sinal path ( in < 5fF)..5 opensation for PT ariations and Frequency-Effects Since the frequency copensation is ased on equalization of phase shifts fro tie constants in the ain and auxiliary paths, the optiu linearity point is suected to PT variations. esistors and c in Fi..5 can e adusted diitally to ensure hih linearity. When ipleentin the attenuation ratios with atched capacitors, the variation of the resistors and transconductance isatch etween the auxiliary and ain paths ecoe the ain sources of IM deradation. Fi..

45 illustrates the technique s sensitivity to % variation of c and G ased on expression for IM in (.5). (a) () Fi... Sensitivity of IM (in dbc) to coponent isatches calculated with equation (.5): (a) MHz sinal frequency, () MHz sinal frequency. In theory, the IM (in dbc) without paraeter variation is infinite. After introducin a nuerical resolution constraint, the peak IM is liited to around 95dBc. Fi.. (a) reveals that G -isatch results in ore deradation than c variation at low frequencies, ut at hih frequencies variation of c ecoes equally sinificant as

46 evident fro Fi.. (). In eneral, less than ±% isatch of G and ±5% variation of c are required for theoretical IM hiher than 7dBc. Under consideration of the trend towards increasin intra-die variaility in odern MOS processes, proraaility of and c is necessary to uarantee G ain and c values within these liits. The deterination of the appropriate increental resistor step size is elaorated next. To otain a practical assessent of the distortion cancellation sensitivity, the copensation resistor value and transconductance isatch in the two paths were varied in circuit siulations usin Spectre. The resultin IM is plotted vs. deviation fro the noinal desin paraeters in Fi..4, showin an IM etter than 7dBc for ±7.5% c -variation and IM etter than 7dBc for ±.% -variation in the presence of % G -isatch. The reference OTA has IM of 5dBc. It is iperative for effective distortion cancellation to ipleent the resistor ladders with % steps, enalin diital correction of relatively sall intra-die isatches. To account for lare asolute variations of paraeters, the adequate resistor tunin rane should e selected ased on siulations under anticipated worst-case conditions. In this work, siulations with process-corner odels and teperatures ranin fro -4 to were conducted. Based on these siulation results, a conservative rane fro ~ to.kω (approxiately % - % of the noinal value) and 6-it resolution were chosen for the proraale resistors c and (Fi..5) in this prototype desin.

47 IM [dbc] IM [dbc] c [Ω] (a) 8 [kω] () Fi..4. Siulations showin sensitivity to variation and isatch of critical coponents: (a) IM vs. chane in c (Fi..5) at 5MHz, () IM vs. (in Fi..5) with % transconductance isatch etween ain OTA and auxiliary OTA at 5MHz..6 Measureent esults.6. OTA Tale. suarizes the characterization results for the OTA. Two. p-p (- 6dB) tones with khz frequency separation and a coined voltae swin of. p-p were applied durin IM easureents. The results in Fi..5 deonstrate IM enhanceent fro 58.5dB to 74.dB at 5MHz coupled with a rise in inputreferred noise fro.n Hz to.8n Hz and twice the power dissipation, while other perforance paraeters are not affected sinificantly. The linearization decreased the SN in MHz BW fro 74.5dB to 7.dB, ut allowed to iprove the IM y 5.7dB.

48 4 Tale. Measured ain paraeters of the reference folded-cascode OTA. Paraeter Measureent Transconductance (G ) 5MHz (in =. p-p) Noise (input-referred) Power with MFB 5MHz Supply voltae 5 μa -55. db. n Hz.6 W 48.9 db. 58.5dB 74.dB Uncopensated OTA IM (input:. (a) opensated OTA IM (input:. () Fi..5. Measured linearity with. p-p input swin fro two tones, each. p-p (-6dB) on-chip after accountin for off-chip losses at the input: (a) reference OTA, () copensated OTA.

49 IM [db] 5 Dependin on the frequency and switch settins, IM enhanceent up to db was achieved with the copensation resistor ladders havin 6-it resolution. If ore linearity iproveent is required, the resolution of the resistor ladders ( and c ) in Fi..5 can e increased y addin ore control its or usin a MOS in triode reion as one of the eleents to otain a series resistance that is closer to the optiu value for distortion cancellation. The IM fro the two-tone tests of the reference and linearized OTAs around 5MHz is plotted versus input peak-to-peak voltae in Fi..6. This coparison deonstrates that the IM enhanceent fro the linearization schee requires weakly non-linear operation. - opensated OTA eference OTA IM [db] in_peak-peak p-p [] [] Fi..6. Measured IM vs. input peak-peak voltae for reference OTA and copensated OTA otained usin two tones havin khz separation around 5MHz.

50 6 Even thouh the linearization effectiveness decreases with increasin input sinal swin, the IM iproveent is still db with.8 p-p differential sinal swin for this desin with. supply. Since the distortion cancellation exhiits the hihest sensitivity to phase shifts at hih frequencies, the control code of the phase shift resistor c in Fi..5 has een chaned fro its optiu value. The resultin effect on the IM of the linearized OTA at 5MHz is plotted in Fi..7, which validates that variale phase copensation is in fact required for optiu linearity perforance. Two resistor ladder settins satisfy that the IM attenuation is ore than 74dB, hence the selected % step for the least sinificant diital it in this desin was appropriate. Toether with the plot otained y sweepin resistor c in siulations (Fi..4a), the easureents indicate that the aount of IM iproveent predoinantly depends on the step size of the proraale resistor ladder, which proises even etter distortion cancellation with finer resolution. Tale. includes noise and IM easureent results at various frequencies, deonstratin the effectiveness of the roadand linearization schee with the associated input-referred noise. Perforance trade-offs can e assessed with the fiure of erit fro [8]: FOM = NSN + lo(fmhz), where NSN = SN (db) + lo[( IM N IM )( BW BW N )( P N P dis )] fro [9], the SN is interated over MHz BW, IM is noralized with IM N = %, andwidth is noralized with BW N = Hz, and power consuption is noralized with P N = W.

51 IM [db] 7 IM [db] Diital code for for the the proraale phase phase shift shift resistor resistor (c) ( c ) Fi..7. Measured IM dependence of the copensated OTA on phase shift otained with two test tones havin khz separation around 5MHz. (The least sinificant it of the diital control code chanes the value of phase shift resistor c y ~%). Tale. oparison of OTA linearity and noise easureents. OTA type eference (input att. = ) inearized (att. = & copensation ) Inputreferre d noise. n Hz.8 n Hz Power consuptio n IM (in =. p-p ) 5 MHz.6 W -55. db 5. W -77. db * See Tale. for details. 5 MHz -6. db db 5 MHz db -74. db Noralize d FOM * (at 5 MHz)

52 8 Experiental results are copared with previously reported architectures in Tale.. The OTA linearized with input attenuation-predistortion shows a copetitive perforance with respect to the state of the art. Hih linearity at hih frequencies is realized in this desin exaple, showin the potential of the technique. Tale. OTA coparison with prior works. []* []* [4] [] [7]* This work IM db -7 db -6 db db IIP -.5 db db 7.6 db f 75 MHz MHz MHz 4 MHz 84 MHz 5 MHz Input voltae -. p-p. p-p.9 p-p -. p-p Power transconductor Input-referred noise 4.5 W. W 4 W 9.5 W.6 W 5. W 7.8 n Hz 7.5 n Hz 7. n Hz. n Hz 5.7 n Hz.8 n Hz Supply voltae Technoloy 65 n MOS.8 μ MOS.5 μ MOS.8 μ MOS.8 μ MOS. μ MOS FOM (db)** Noralized FOM *** * Powertransconductor calculated fro filter power. Individual OTA characterization results not reported in full. ** FOM (db) = lo( f MHz ) + NSN fro [8] ; NSN = SN (db) + lo[( IM N IM )( BW BW N )( P N P dis )] fro [9]. ( SN interated over MHz BW, noralization: IM N = %, BW N = Hz, P N = W ) ( IM in FOM for [] and [7] was calculated with: IM (db) = x [ Pin (db) - IIP (db) ]. ) *** Noralized FOM anitude relative to []: Noralized FOM = ^(FOM (db)) ( ^(FOM (db)) of [] )

53 9.6. Second Order ow Pass Filter Fi..8 shows the filter frequency response for the proof-of-concept iquad desin in Fi.., and its linearity perforance is plotted aainst frequency in Fi..9. MHz 94.7MHz 69.7dB Frequency response of nd - order PF (a) IM of the PF with copensated OTAs (input:. () Fi..8. Filter easureents: (a) transfer function with ~4dB total losses (input loss and output uffer attenuation). () IM with. p-p input swin fro two tones, each. p-p (-6dB) on-chip after accountin for off-chip input losses. The IM of the filter is up to 8dB worse than that of the standalone OTA. However, the easured filter IM includes approxiately -db deradation due to the non-linearity of the output uffer. By adustin the resistor ladders with diital controls that are coon for all OTAs, the filter achieves IM -7dB up to 5MHz for a

54 IM [db] 4. p-p two-tone input. At MHz, the IM is -66.dB, deonstratin the effectiveness of the roadand linearization due to copensation with the phase shifter Frequency [MHz] Fi..9. Measured filter IM vs. frequency with two test tones havin khz separation. Fi.. visualizes the easured IM with increasin input voltae up to. peak-peak differential swin, which follows the expected trend. At 5MHz, an IM of approxiately -db occurs with an input sinal of.75 p-p. Fi.. illustrates the in-and IIP (4.dB) and IIP (.7dB) curves easured with two tones separated y khz around 5MHz and MHz, respectively. In roadand receiver applications with liited filterin in the F front-end, the presence of nuerous out-of-and interference sinals results in inter-odulation coponents within the desired sinal and. Thus, hih out-of-and linearity is desirale in addition to the aseand filter attenuation in order to iniize in-and distortion. This is one of the ain otivations to eploy OTAs with hih linearity at hih frequencies even for aseand filters with low cutoff frequencies.

55 Input-referred power [db] Input-referred power [db] IM [db] 4 IM [db] in_peak-peak p-p [] [] Fi... Measured IM vs. input peak-peak voltae for the linearized filter otained with two test tones havin khz separation around 5MHz Pin 4 Pin IM IM Pin [db] Pin [db] (a) () Fi... Measured in-and intercept point curves for the filter: (a) IIP [two tones, Δf = khz around 5MHz], () IIP [two tones, Δf = khz around MHz].

56 Input-referred power [db] Input-referred power [db] 4 The out-of-and IIP plot in Fi..a confirs that the linearization schee s effectiveness is preserved eyond the cutoff frequency. The sliht deradation of the out-of-and IIP to.4db is ost likely due to the different phase shifts experienced y the 75MHz and 75MHz test tones fro the input to node in the auxiliary path (Fi..5). The diital control code for the phase shift resistor c of the OTAs in the filter was set to optiize linearity in the 95MHz andwidth, hence the linearity deradation due to the frequency difference of the out-of-and tones. The out-of-and IIP (Fi..) is.4db, which is.db lower than the in-and IIP due to suoptiu phase shifts at 75MHz. Despite of that, the use of OTAs with hih out-of-and linearity helps to reduce in-and distortion fro out-of-and interferers in roadand scenarios. The filter area on the die (Fi..) is ~.5 includin the output uffer Pin IM Pin IM Pin [db] Pin [db] (a) () Fi... Measured out-of-and intercept point curves for the filter: (a) IIP [f = 75MHz, f = 75MHz, f IM = MHz], () IIP [f = 75MHz, f = 75.MHz, f IM = khz].

57 4 Fi... Die icroraph of the OTAs and filter in.μ MOS technoloy. (eference OTA area:., linearized OTA area:.9 ). Tale.4 suarizes its key perforance paraeters in contrast to other wideand lowpass filters. The 54.5dB dynaic rane interated over the 95MHz noise andwidth is copetitive with prior works havin siilar power consuption per pole, ost of which were ipleented under less voltae headroo constraints than with the. supply in this desin. The proposed linearization is independent of OTA topoloy, ut the proof-of-concept desin is coprised of a restrictive fully-differential OTA core in order to deonstrate the concept with a conventional topoloy. The last two coluns in Tale.4 indicate that the proposed linearization allows alost siilar filter linearity perforance (in-and IIP = 4.dB with. supply) y eans of fully-differential OTAs as with the pseudo-differential OTAs in [], in which an in-and IIP of 6.9dB was recently achieved with.8 supply. Apart fro linearity considerations, the optiizations involvin power consuption, input-referred noise, power supply noise reection, and M depend on the application-specific constraints. Accordin to

58 44 the FOM coparison with the reference OTA in Tale., the proposed linearization ethods iproves OTA linearity with favorale power and noise trade-offs. Furtherore, the ost sinificant dynaic rane iproveent with the proposed technique can e achieved in andpass desins, in which the noise is interated over a narrow passand and the linearity iproveent sinificantly reduces the power of the in-and distortion. Tale.4 oparison of wideand G - lowpass filters. [] [7] [8] [9] [] [] [] This work Filter order f c (ax.) 75 MHz 84 MHz MHz MHz MHz 5 MHz MHz MHz Sinal swin -. p-p. p-p.88 p-p.8 p-p.5 p-p -.75 p-p inearity with ax. in p-p In-and IIP db (.5 db) HD, HD5: < -45dB 7dB (db) THD: MHz THD: MHz THD: MHz THD: < 7MHz In-and IIP Out-of-and IIP Out-of-and IIP -8 db (5 db) 5 db (8 db) -.9 db (6.9 db) 9 db ( db) IM: -db 5MHz. db (4. db).7 db (.7 db) -.6 db (.4 db) 7.4 db (.4 db) Power 6 W.6 W W 48 W W W 7 W.8 W Power per pole Input-referred noise Dynaic rane Supply voltae 7. W.5 W 5 W W W W 4 W.4 W 7.8 n Hz 5.7 n Hz** n Hz 5.4 n Hz 44 db* 4. db*** 45 db 58 db - 5 db db*** Technoloy 65 n MOS.8 μ MOS.5 μ MOS.5 μ MOS.5 μ MOS.5 μ MOS.8 μ MOS. μ MOS * eported spurious-free dynaic rane. ** alculated fro 9.μ MS in khz BW. *** alculated fro ax. p-p, f c, and inputreferred noise density. **** IM of -db easured close to f c ensures THD < -4dB.

59 45.7 Excess Phase opensation Fi..4 shows the lock diara of a andpass (BP) iquad. The inset in the fiure displays a odel for an OTA in interator confiuration, where r o represents the OTA output resistance, o represents the output capacitance, and G(ω) represents the transconductance that chanes with frequency due to internal parasitic poles. inearization introduces an additional pole ω c that could influence the filter response at hih frequencies. This pole can e cancelled y addin resistor s = (ω c ) in series with the load capacitor [] to counteract the ipact of excess phase on the quality factor ased on the expression iven in []. i+ i- OTA- Interator with Excess Phase opensation G (ω) r o o ½ s s ½ o+ o- G A sa in G B G BP sb G 4 Fi..4. Sinle-ended equivalent lock diara of a andpass iquad. The linearized OTAs descried in Section.4. were eployed in a BP filter (Fi..4) with f o = MHz, G = G 4 = G, and G = G = G for siplicity

60 46 (iplyin ω c = ω c = ω c ). Series resistors sa and sb with A and B copensate for the phase shift fro the linearization y creatin zeros ω za and ω zb : ω za = ( sa A ) = ω zb =( sb B ) = ω z = ω c. A sall BW error reains after copensation due to the difference etween ω z and ω c of G ecause ω za ( sa, A ) and ω zb ( sb, B ) are optiized to cancel ω c and ω c of G and G, respectively. Thus, the pole ω c is only partially cancelled since G G. Nevertheless, the effect is sall in the typical case (ω << ω c ). This BP filter achieves siulated IM of -7.dB evaluated after an additional output uffer (G). Fi..5 contains siulated plots of the frequency responses for different values of s fro this exaple BP filter desin. The plots show how the adustent of s = sa = sb ( B A ) durin the desin allows tunin of the quality factor to ~4 with s = 7Ω in this case, while f o does not chane sinificantly. fo [MHz] Q s [Ω] (a) () Fi..5. BP filter siulations with different s values for excess phase copensation: (a) frequency responses, () quality factor and center frequency; where s = sa = sb ( B A ).

61 47.8 inearization without Power Budet Increase Attenuation-predistortion linearization offers the eans to iprove the linearity of a iven OTA while preservin its A characteristics without desin chanes in the OTA core, which is achieved at the expense of increased power, noise, and layout area. Another option is to redesin the two OTAs in the linearization schee usin half of the power in order to eet the sae power udet as the oriinal OTA. But, that approach is associated with a reduction of the OTA andwidth as delineated in this appendix. To accoplish linearization with equal power udet, the currents I and I in Fi..8 can e reduced y 5%, which requires increasin the W ratios of the transistors in the core (M c ) to otain the sae transconductance as efore. Thus, the saturation voltae DSAT of M c ecoes approxiately half of the initial value. Furtherore, the ratio of transconductance to parasitic capacitance (i.e. f T ) of oth OTAs in the linearization schee reduces due to the ias current decrease and width increase for M c. Gain vs. frequency siulations of the linearized OTA (5% power reduction in each path) and the reference OTA revealed that the linearization with equal power reduces the effective db andwidth fro.49ghz to.9ghz with 5Ω load. Tale.5 suarizes the key results fro siulatin the linearized OTA in coparison to the reference OTA with identical total power. Hih linearity throuh distortion cancelation (IM -77dB) is achievale, ut liited to lower frequencies. Despite of this, the results indicate that hiher FOM can e achieved with low-frequency linearization copared to the linearization with douled power consuption.

62 48 Tale.5 Siulated coparison: OTA linearization without power consuption increase. OTA type DSAT of input diff. pair (M c) f d with 5Ω load Inputreferred noise Power IM ( in =. p-p) Noralized FOM * (at f ax) eference (input att. = ) 9.49 GHz 9.7 n Hz.6 W -5. db at f ax = 5MHz (-5. db at MHz) 57. inearized (att. = & copensation) 54.9 GHz 4. n Hz.6 W -77. db at f ax = MHz 9. * See Tale. for details.

63 49 HAPTE III HIGH EFFIIENY ASS D POWE AMPIFIE FO OW POWE APPIATIONS. Introduction The deand of hih perforance wireless personal area network has led to the developent of various standards such as Bluetooth [4] and UWB [5]. These standards enale the transission of hih data rate with adequate power consuption. Other applications such as sensor networks require low data rates and loner attery life. These requireents have led to the developent of low power standards such as ZIGBEE [6] and MIS [7], where the data rate are elow Mp and counication rane is liited to aout - with the transitted power ein less than db. lassical fors of iplantale edical devices used anetic couplin to counicate with external equipents. However, they require very close proxiity of the readin device and they are prone to interferences fro other radiatin sources. Medical iplant counication service (MIS) standard was developed to allow wireless connection etween iplantale edical chips and external equipent [8] for a distance of two eters or ore [9]-[4]. To prolon the attery lifetie, MIS transceiver should e desined with the ai to iniize the power consuption. Since the sensitivity requireent of the iplanted receiver is relaxed y the standard, the receiver power consuption can e iniized. On the other hand, the axiu allowed transitter power of MIS standard should e liited to -db [4]. To enale

64 5 the use of hih efficiency transitter, constant envelope odulation schee is adopted y MIS syste level desiners. onstant envelope odulation allows the use of switchin power aplifiers which exhiit hih efficiency. Analysis and desin of hih efficiency power aplifier (PA) have een presented for hih output power applications [4]-[44]. However, the rowin deand on low output power transitters ake it necessary to develop new desin techniques for hih efficiency power aplifier. In this proect the desin and analysis of hih efficiency power aplifiers for low output power applications will e presented and verified with experiental results.. Hih Efficiency Power Aplifier Architectures The ost coon types of switchin power aplifiers are class D PA and lass E PA. The ain difference etween class D and lass E is that the lass E PA uses haronic shapin network to achieve zero voltae switchin (ZS) and thus it typically has hiher efficiency than class D PA. In the followin sections, an overview of oth power aplifier classes are iven with the advantaes of each type in different applications... lass E PA osses in switched ode power aplifier can e cateorized into conduction losses due to finite switch resistance, and switchin losses due to parasitic capacitor charin and discharin. To iniize conduction losses the switch on resistance should e iniized, however usin lare transistor to reduce the on resistance will

65 5 result larer parasitic capacitor and thus hiher switchin losses. lass E power aplifiers shown in Fi.. deonstrate hih efficiency at hih output power level since it uses soft switchin and thus eliinates the switchin losses [45]. The conditions to iniize the switchin losses can e suarized as ) oltae reaches zero efore the switch turns on. ) urrent flowin in the switch reaches zero efore the switches turns off. ) The slope of the voltae at turn on is zero, which will help to insure hih efficiency operation even if the switchin is shifted fro its optiu point. F p in iven y [45] Fi... lass E power aplifier. Usin these conditions, the value of the inductor, capacitors, and resistance are Q f 8 ON 4 P f 4 out.4 f Q.8, (.)

66 5 where ON is the transistor on voltae, and Q is the quality factor of the output tank. The derivation of (.) is iven in [46], in which it was assued that Q is lare enouh such that the current flowin into output load resistance can e represented y the fundaental coponent only. Nelectin the transistor on voltae ON, the load resistance can e calculated fro (.) to e 96Ω for a supply voltae of and output power of - db. In this case the value of the inductance should satisfy the hih Q condition, >> πf. For MIS standard, the frequency of operation is around 4 MHz, and the inductance at this frequency should e chosen such that >> 64.5 nh. It is clear that the value of the inductor is too hih and it will result very sall value of the capacitor. Hence, lower Q is desired in order to otain ore reasonale values of the circuit eleents. Exact analysis for class E power aplifier with any value of Q is iven in [47]. In eneral Q should not e too low in order to have low haronic content at the output. For Q =, the values of the circuit eleents is iven y [47].4 f, (.).4 f.48 P out.4 f At 4 MHz, the circuit eleent values are =66Ω, =5.4nH, =.PF, and =.8PF, for output power of -db and supply voltae of. Usin these values, the efficiency of ideal lass E PA is reater than 9 %. However, the hih inductance value requires the use of off-chip inductors and packae parasitics should e included in the siulation. By addin a parasitic capacitor of PF at the drain of the

67 5 transistor, the efficiency decreases to less than %. Even after addin a resonatin inductor to cancel the effect of the parasitic capacitance, the efficiency increases to aout 46%. To achieve hiher efficiency, the parasitic capacitor should e eliinated at haronic frequencies. Althouh class E power aplifier shows superior efficiency, it is very sensitive to parasitics and the coponents values are not practical at low output power levels... lass D PA In class D switchin PA [48], the voltae at the drain of the transistors takes the shape of a square wave that is filtered usin the output tank. Fi.. shows class D power aplifier scheatic and the associated voltae and current wavefors are depicted in Fi... The efficiency of class D power aplifier is ideally %, however due to finite on resistance of the switches and the switchin losses associated with charin and discharin of parasitic capacitors, the efficiency is typically around 7-9% for class D operation. Assuin that the quality factor of the output filter is hih enouh, the output current can e assued to have only the fundaental coponent and other haronic coponents can e nelected. Since half of the load current flows into the NMOS switch, while the other half flows into PMOS switch, the losses associated with the finite transistor on resistance can e written as P 4 I, (.) op N P where I op, N, and P are the peak value of the output current and the on resistance of NMOS and PMOS respectively.

68 54 in I o p Fi... lass D power aplifier. D i o t t i M t i M t Fi... oltae and current wavefors of class D power aplifier. The switchin losses due to charin and discharin of p is iven y P ddp f, (.4)

69 55 where dd is the supply voltae and f is the operatin frequency. Since the voltae at the drain of the transistors is a square wave with a peak value of dd, the fundaental coponent of this square wave is dd π. The peak value of the output current is iven y I op dd (.5) Hence the efficiency of class D power aplifier is P P P o.5 o P.5I op op N P p f.5i.5i N op P I op p f (.6) To enhance the efficiency, the on resistance of transistor should e iniized. Since the output power is P o, for low output power applications the value dd of the resistance should e hih. Thus, the losses due to finite on resistance are lower for low output power since the ratio ( N + P ) ecoe saller. However the ipact of the switchin losses increases as the output power ecoes saller. Techniques to iprove the switchin losses in class D power aplifier are discussed in the followin section.. Zero oltae Switchin in lass D PA The efficiency of class D power aplifier can e iproved y usin soft switchin to reduce the switchin losses [49]. The key idea is to switch off NMOS and PMOS devices at earlier tie (Duty cycle <5%) to allow the output current to dischare the parasitic capacitance as depicted in Fi..4. In soft switched class D PA, the chare

70 56 on the parasitic capacitance is turned into useful output current and thus the efficiency is iproved. In [49] the input voltae is assued to e a sine wave and the aplitude of the sine wave is selected to achieve the required delayed switch turn off. ds s,n s,p I o tie Fi..4. Soft switchin in class D power aplifier. However, at low output levels the output current is very sall near the switchin point such that it will not e enouh to dischare the parasitic capacitance. To solve this prole, the current at the switchin point should e hih enouh to dischare the parasitic capacitance. educin the quality factor of the selective network will allow hiher haronics to flow and the current I o will e closer to square wavefor. The extra haronics of the current I o can e filtered usin addin an extra parallel

71 57 tank added to the circuit, ut this will increase cost of passive coponents needed. In the proposed solution, the atchin network will e used as a filter of these extra haronics since it is a step-up atchin network. For hih power application, the load ipedance should e sall to et the desired output power. The value of the load resistance is P. Since the dd o antenna ipedance is typically chosen to e 5Ω, atchin network should e used. For hih power application the required is typically less than 5Ω and step down atchin network is used. On the other hand for low power application is hiher than 5Ω and a step up atchin network is used. The step down atchin network is shown in Fi..5. s s Fi..5. Step down atchin network. The equivalent resistance s and capacitor s are iven y s s Q Q (.7) The inductance in the step down atchin network is used to resonate the capacitor and thus the input ipedance equals s at the operatin frequency. The step up atchin network shown in Fi..6 acts as a low pass filter and can e used to filter the

72 58 hiher haronics of the aplifier. The equivalent resistance p and inductance p of the atchin network can e written as p p Q Q (.8) p P Fi..6. Step up atchin network. The capacitor is chosen to resonate with the inductance p at the frequency of operation, thus the input ipedance of the atchin network is purely resistive. Since the step up atchin network acts as a low pass filter, the quality factor of the output tank can e reduced to allow ore current haronics as shown in Fi..7. ery low Q will result square current wavefor and thus the current at the switchin ede will e hih enouh to achieve zero voltae switchin. The square current wavefors will result in hiher I rs which in turn will increase the conduction losses in the MOS switches. The optiu current wavefor is therefore soewhere in etween the traditional sine wave and the square wave. In the followin analysis, the first and the third order haronics will e considered and optiized for the est efficiency.

73 59 The voltae at the drain of the transistors is a square wave with a finite fall and rise ties. For siplicity, the rise and fall of the drain voltae is assued to e of equal duration (ΔT) and a linear function of tie, with the tie oriin chosen in the iddle of the risin period. Selectin Network Matchin Network PA Driver p I + - I ds s,n s,p I tie Fi..7. Proposed current wavefors in soft switched class D power aplifier.

74 6 The drain voltae can e represented y Fourier series x x x where T n n dt t n t v T a dt t v T a T t n a a t v dd T n dd T n n ) sin( ) sinc( ) sinc( )sin ( 8 ) (, sin ) ( 4,,.. (.9) Takin into account the finite Q of the inductors, the adittance at the input of the atchin network is iven y, Y r S S Y, (.) where r is the resistance in series with the inductor due to its finite quality factor. At the fundaental frequency, the input ipedance of the atchin network is purely resistive and it is iven y.8. However at the haronic frequencies, the ipedance at the input of the atchin network is, Q Q where nq nq Q Q nq n Q nq Q Q n Q n nq n n n Z S S S Z n (.)

75 6 The capacitor resonate with the inductor at the operatin frequency (ω = ω ), hence the voltae at the capacitor at the haronics of ω is ) ( ) ( n in Q nq n nq Z Q n Z Z r n n Z, (.) where r is the resistance of the inductor. The current throuh the is iven y,5,.. ) ( ) sinc( sin sin ) sinc( n dd dd Q nq n T n t n n r t T i (.) The power loss in the resistor r is then iven y,5,.. ) ( ) ( sinc ) ( sinc n dd dd r Q nq n r T n n r r T P (.4) The atchin circuit acts as a low pass filter and thus the output current is ainly fundaental current at ) ( ) sinc( ) ( ) sinc(, Q T Q T r i dd dd fund (.5) Hence the power loss in the resistor r is iven y ) ( ) ( sinc Q r T P dd r (.6) Each transistor rs current is half the rs current of the resistor r, and oth transistors will e ON for only (T ΔT), thus the power loss due to finite transistor resistance is

76 6,5,..,5,..,5,.. ) ( ) ( sinc ) ( ) ( sinc ) ( ) ( sinc ) ( sinc ) ( ) ( sinc ) ( sinc n p N n dd p N dd P N tr n P n dd P dd P n N n dd N dd N Q nq n r r T n n r r r T P P P Q nq n r T n n r r T P Q nq n r T n n r r T P, (.7) where P N and P P are the losses due to NMOS switch and PMOS switch respectively, and α n = -ΔTT+sin(nω ΔT)nπ. Usin (.) and inorin the haronics hiher than the third order, the current throuh the inductor can e approxiated as ) ( ) sinc(, ) sinc( ) cos( ) sin( dd dd r Q Q T I r T I t I t I i (.8) To achieve zero voltae switchin, the chare on the parasitic cap should e converted to output current durin a tie of ΔT in which oth transistors are off. Hence, sin ) cos( ) sin( T I dt t I t I dt i Q T T T T T T T T r dd (.9) The duration T should e chosen to allow enouh tie to dischare parasitic capacitor, however hiher values of T will affect the operation of the aplifier. hoosin T to e T then 9 7 )sin sinc( sin Q f T T X T T I s dd (.)

77 6 As entioned efore hiher values of the third haronic current coponent result less switchin losses, however it will lead to hih conduction losses due to finite resistance of switches. Assuin the third haronic current coponent is less than the value iven in (.) it will not e enouh to achieve full zero voltae switchin, the reainin chare on the parasitic capacitor and the associated switchin losses are )sin sinc( 9.5 sin.5.5 dd s dd s dd s dd sw dd Q Q X T T f T T I f f Q P I Q (.) Hence the total loss in class D power aplifier is iven y the suation of all power losses,5,.. ) sinc( sin 9.5 ) ( ) ( sinc ) ( ) (.5 ) ( sinc ) (.5 ) ( sinc dd s dd dd n P N n dd P N dd loss Q X Q X T T f Q r T Q X nq nx r r Q X n T n Q X r r Q X T P (.) The inductor and capacitor are chosen to atch the antenna ipedance to the required ipedance for certain output power. Since the inductor will deterine the and pass filter andwidth and haronic contents, the inductance value should e chosen to et the iniu losses. The condition to iniize the power losses can e otained y differentiatin the power loss with respect to the inductance value

78 ) ( ) sinc( sin ) ( ) ( ) ( sinc ) sinc( sin ) ( )) (.5 6( ) ( 9 ) ( sinc ) ( sinc Q T T r r X X P Q X T T Q X r r T Q X T T Q X r r Q X Q X Q T Q T X P P N loss dd P N dd dd P N dd dd loss (.) The size of the switches should e chosen lare enouh to decrease their on resistance, however lare switch size will result hiher input capacitance and the power consuption of the pre-driver will increase due to hiher switchin losses. Since the switch resistance is inversely proportional to the transistor width, while the switch capacitance is directly proportional to the width, the transistor size should e optiized to iniize the power losses. The transistor on resistance and input capacitance can e written as W K W K r s r on, (.4) where K r and K c are supply and technoloy dependent constants. After addin the losses due to the input capacitance of the switches, the power losses take the for

79 65 s dd p cp s dd n cn dd s dd dd n p rp n rn n dd p rp n rn dd loss f W K f W K Q X Q X T T f Q r T Q X nq nx W K W K Q X n T n Q X W K W K Q X T P,5, ) sinc( sin 9.5 ) ( ) ( sinc ) ( ) (.5 ) ( sinc ) (.5 ) ( sinc (.5) The optiu transistor size is otained y differentiatin the power losses with respect to W n and W p ) 9( ) ( sinc ) ( sinc ) 9( ) ( sinc ) ( sinc Q X T T f K K W W P Q X T T f K K W W P s cp rp p p loss s cn rn n n loss (.6) Usin (.), the optiu transistor width can e written as ) 8 ( sin ) ( sinc ) 8 ( sin ) ( sinc cp rp cn rn rp s cp rp s cp rp p cn rn cp rp rn s cn rn s cn rn n K K K K K f K T K f K T K W K K K K K f K T K f K T K W (.7).4 ircuit evel Ipleentation lass D switchin power aplifier has een ipleented for MIS standard at 4 MHz with output power of -db as specified y the standard. The power aplifier and its driver that provides the appropriate control for oth switch types are discussed next in the followin sections.

80 66.4. lass D PA ircuit The power aplifier is faricated in MOS 9n technoloy. The technoloy paraeters can e extracted fro siulation and they are listed in Tale.. Tale. Transistor paraeters. Paraeter K rn K cn alue.5 - Ω F K rp.4 - Ω K cp.8-9 F Usin the procedure outlined in section., the transistor sizes and passive coponent values are iven in Tale. for output power of -db at 4 MHz. Siulations were done to otain the optiu coponent values and they are also shown in Tale..4. PA Driver ircuit Power aplifier driver should convert the input sine wave to the square wave necessary to drive the switchin aplifier. Power aplifier driver is ipleented as a

81 67 series of inverters followed y delay control for the NMOS and PMOS switches as shown in Fi..8. Tale. PA circuit coponent values. Paraeter alculation (ΔT =T) alculation (ΔT =T) Siulation 7.6 nh. nh 4 nh 9 PF PF 6.6 PF 45.7 nh 45.4 nh 4 nh.9 PF.9 PF.5 PF W n n W p p Driver PMOS ontrol K n <K p PA NMOS ontrol K p <K n Fi..8. Power aplifier driver circuit.

82 68 The PMOS switch has a MOS driver which consists of a sall NMOS transistor and a lare PMOS transistor. When PMOS switch is off, its ate voltae is at dd. Durin the transient fro off-state to on-state of PMOS switch, the sall NMOS transistor in its driver slowly dischares the switch ate to the round potential. On the other hand, NMOS switch driver has lare NMOS transistor size and thus it will switch to the off-state efore the PMOS switches to on-state such that there is enouh tie for the ZS to take place. When NMOS is switched fro off-state to on-state, the sall PMOS transistor in its driver will slowly chare the switch ate and thus ZS will e achieved..5 Measureent esults The power aplifier was faricated in UM 9 n process; the power aplifier occupies 4μ of chip area as shown in Fi..9. lass D PA Fi..9. lass D PA chip icroraph.

83 69 The output tank and atchin networks are off-chip as shown in Fi... PA input PA output hip PA output tank and atchin network Fi... PB of class D power aplifier. In order to asor the trace inductance, its value has een taken into account when desinin the atchin network. The PB trace connectin the passive coponents is uch shorter than the wavelenth at 4 MHz, hence it can e odeled usin one inductor and two capacitors as shown in Fi... For a standard F-4 PB with trace width of 6il, the inductance per inch is approxiately.9 nh and capacitance per inch is aout.9 PF.

84 7 Fi... PB trace odel. The siulated and easured output power of the class D power aplifier are shown in Fi.. for different supply voltaes. The correspondin power aplifier efficiency is displayed in Fi... Since the value of the parasitic capacitance at the output of the power aplifier iht e larer than its estiated value of PF, the easured power efficiency is less than the values otained fro siulation. In addition, hiher values of on resistance due to process variations, inaccuracies in the PB trace parasitics values, or output passive coponent values also lead to lower efficiency.

85 7 Measureent Siulation. Pout (A) dd (v) Fi... Output power versus supply voltae. Measureent Siulation % dd (v) Fi... Power aplifier efficiency versus supply voltae.

86 7 The easured frequency response of the aplifier is copared to the siulated response as illustrated in Fi..4. The power aplifier efficiency at different frequencies is shown in Fi..5. It is clear that there is a sliht shift in the frequency response due to passive coponent variations. Measureent Siulation..8 Pout (W) f (MHz) Fi..4. Frequency response of power aplifier. The power aplifier response to FSK odulated sinal with frequency separation of Δf= KHz is shown in Fi..6.

87 7 Measureent Siulation Pout (W) f (MHz) Fi..5. Power aplifier efficiency at different frequencies. Fi..6. Power aplifier output for FSK odulated sinal.

88 74 HAPTE I HIGH EFFIIENY ASS A POWE AMPIFIE WITH DYNAMI BIAS ONTO 4. Introduction The deand for hiher data rates over wireless channels has increased sinificantly over the last few years. To enale transission of lare aount of data, the state of art counication systes require efficient utilization of the availale andwidth. Traditional low power counication systes eploys constant envelope sinals to allow the use of hih efficiency switchin power aplifiers. The inearity of such switchin-type aplifiers is typically very poor thus it is only suitale for low data rate applications in which constant envelope sinal can e used. Envelope odulated sinals are widely used nowadays as they allow the transission of hiher inforation rate when copared to constant envelope sinals over the sae channel andwidth [5]. While constant envelope sinal perit the use of the hihly efficient switchin power aplifiers, variale envelope sinals andate the use of less efficient ut ore linear power aplifier classes. Since odulated sinal has averae power which is typically 8- db less than the peak power [5], the use of constant D current and supply voltae to ias the power aplifier results poor efficiency at lower power levels which will lead to lower attery life in oile transceiver systes. The efficiency of conventional class A power aplifier can e written as [5]

89 75 P op o op, (4.) P I D dd where op is the peak value of output voltae, is the load resistance, dd is the supply voltae and I D = dd is the D current ias. The axiu efficiency is 5% which occur when op = dd and I D = dd. Since the axiu output voltae swin is liited y the supply voltae and D current, the D current I D and the voltae supply dd ust e lare enouh to achieve hih sinal swin at sinal peak power level. However, the hih D current will derade the efficiency at the lower power levels. There are two techniques to uild hihly linear PA that has an acceptale efficiency especially at low output power levels. The first technique relies on enhancin the efficiency of linear aplifiers as illustrated in Doherty aplifiers [5], while the second technique is ased on linearization of non-linear aplifier. The asic idea ehind the Doherty aplifiers is to have two aplifiers, the ain aplifier and an auxiliary aplifier as shown in Fi. 4.. The ain power aplifier is iased to operate at hihest efficiency at the averae output power and thus it has a D current less than the required current at the axiu output power. When the input power is sall enouh the ain PA operates in the linear ode and the auxiliary PA is turned off. As the input power increases the first PA operates in the ain-copression reion and the auxiliary aplifier turns on such that it overcoes the ain copression of the ain aplifier. D dd

90 76 Pout Main PA oination in + out Main PA Aux. PA Aux. PA Pin Fi. 4.. Doherty aplifier concept. On the other hand, the hih efficiency switchin power aplifier can e linearized usin either outphasin or envelop eliination and restoration [48] and [5]. Fi. 4. displays Khan envelop eliination and restoration technique in which switchin aplifier is used to achieve hih efficiency. The output sinal of the switchin PA is proportional to the supply voltae, thus y varyin the supply voltae the required aplitude odulation is achieved. In outphasin topoloy, the linear aplification is otained y separatin the input sinal into two constant envelop sinals with proper phase delay which can e aplified usin switchin PA and then coined aain at the output as depicted in Fi. 4.. The output in this case is iven y out = K cos(δφ) cos(ω t), where Δφ is the phase shift etween the input sinals of the power aplifiers. If the phase delay etween the inputs of the two power aplifiers Δφ is ade proportional to the arccosine of the input sinal aplitude, the output will e linearly

91 77 proportional to the input sinal aplitude. However, it is still very difficult to ipleent low loss and hih isolation power coiner at the output of two PA s [54]. in Envelop Detector inear Driver iiter out Switchin PA Fi. 4.. Envelop eliination and restoration. Φ iiter in Env Detector Switchin PA's out iiter Fi. 4.. inear aplification usin non linear aplifier (outphasin technique). In applications where hih linearity is required lass A power aplifier is typically used as it offers the est linearity aon other power aplifier classes. In applications where very hih linearity is required, the linearity of class A power

92 78 aplifier can e further iproved usin one of the followin techniques: Predistortion (analo diital), feedack, feedforward, and adaptive ias. The Predistortion technique can e ipleented in the analo or the diital doain. Analo Predistortion usually takes the for of attenuator at low sinal level and no-attenuation at hiher sinal levels to copensate for the PA ain reduction at hih sinal levels. In the diital predistortion, DSP is used to copensate for the aplifier non-linearities y easurin the aplitude of the incoin sinal and then apply the appropriate predistorted sinal to the aplifier. It is also possile to dynaically chane the correctin sinal if the PA characteristics chanes with tie. Feedack techniques can e cateorized into direct feedack and indirect feedack. Direct feedack refers to the conventional feedack technique y takin a part of the output sinal and feed it ack to the input. However, the ain prole is the delay etween the input and the output sinal which will affect the linearity iproveent and the staility of the syste. The indirect feedack techniques include envelope feedack, artesian loop and polar loops. The envelope feedack forces the output envelope of the PA to follow the input envelope as shown in Fi The envelope feedack however is not ale to linearize the PA if it is operatin in the ain copression reion. The artesian feedack (Fi. 4.5) and polar loop uses the ase-and sinal inforation availale in a coplete transitter to linearize the PA. The feedforward concept is displayed in Fi The asic idea is to extract the non-linear distortion at the output of the power aplifier and then sutract it fro the output of the power aplifier to have a

93 79 linear output sinal. Delays are added to copensate for the delays in the ain PA and error aplifier. in PA out Atten. Peak Detector + - Peak Detector Fi Envelope feedack. I Q Sin(t) PA inearized output os(t) Atten. Sin(t) os(t) Fi artesian feedack.

94 8 Main PA Delay out in Att. Delay + - Error Ap. Fi Feedforward linearization. The prole of ain-copression in PA can e alleviated y adustin the ias of the PA to have hiher ain. The effect of dynaic ias on the power aplifier linearity is discussed in the followin section. The efficiency of class A power aplifier is poor at low output power levels. lass A PA efficiency can e iproved y dynaic adustent of the D current and the supply voltae with the variation of the sinal envelope. For a fixed supply voltae, the optiu value of the D current level for the hihest possile efficiency is I D = op. In this case the efficiency is iven y [5] op (4.) dd hanin the supply voltae dynaically will also iprove the efficiency as descried in [55] [56], in which discrete levels of supply voltae are used. Hih

95 8 efficiency D-D converters can also e used to control dd in a continuous fashion [57]. As descried in [55] the dynaically adustent of the ias current enhances the linearity of the aplifier since it can e used to achieve flat ain at low and hih power levels. The linearity of envelop odulated sinal is typically easured usin error vector anitude (EM), which derades if the sinal experience different ain at different power levels [58]. To achieve the axiu efficiency, the optiu D current at a iven output power level is proportional to the output voltae level (I D = op ). However, if the ias current is ade linearly proportional to the output voltae level, the linearity of the aplifier will derade as the resultin ain of the aplifier will not e constant at different input power levels. In this proect, the current of the power aplifier is dynaically adusted with linear dependence on the input voltae. The ain of the preaplifier is adusted accordinly to otain constant overall ain and consequently ood linearity. The relationship etween the dynaic ias ehavior and the linearity of the power aplifier is presented and techniques to iprove the linearity further are proposed. 4. Dynaic Bias of lass A Power Aplifier The output voltae aplitude o of the power aplifier can e expressed in ters of its nonlinear coefficients and input voltae aplitude i as o = a i +.75a i [48]. Hence, the ain of the power aplifier is G = a +.75 a i. For neative values of a, the third order non-linearity of power aplifier will result in a ain

96 8 reduction as the input power increases. By usin dynaic ias circuit, the D ias current and consequently the aplifier ain should increase as the input power increases to copensate for this effect and thus result etter linearity [59]-[6]. To achieve the axiu efficiency at lower output power, the D current at low output power should e reduced to the optiu value of op. Since the ain of the aplifier is a function of the D current, lower current will lead to lower ain at low input power levels. In the proposed aplifier, the ain of preaplifier is increased to copensate for this ain reduction at low output power levels. At hih output power levels the ias current of power aplifier is increased resultin hiher ain. On other hand, the third order aplifier non-linearity causes a ain reduction as the input power increases. Hence the ain of the preaplifier should e adusted takin into account the ain expansion due to hiher D ias current of power aplifier and the ain reduction due to nonlinear ehavior of the aplifier. For a sall variation in the D ate-source voltae of MOS transistor, the D current can e written as I D = I D + Δ GS. Hence, the ate-source voltae GS should e ade linearly proportional to sinal aplitude in order to achieve the required linear D current dependence on the output voltae. This can e easily done y usin a linear envelope detector to control the ate-source voltae of the transistor. To enhance the aplifier staility, the envelope detector is placed at the input of the aplifier. onstant ain can e translated as a linear relation etween input and output sinal. Thus the inter-odulation distortion should e inial for an aplifier that exhiit constant ain at the fundaental frequency coponent. The followin analysis

97 8 will focus on the relationship etween the ain at the fundaental and the third order inter-odulation coponents and the effects of the dynaic ias current on distortion. 4.. Dynaic Bias Effect on Aplifier inearity The current of MOS transistor can e approxiated usin Taylor series as i, (4.) i i i where, and are Taylor series coefficients. The transconductance of MOS transistor is proportional to the current flowin throuh it and consequently the ate-source voltae GS. For a sall variation of ate to source voltae Δ GS, the transconductance of the transistor can e approxiated as s, (4.4) where is the transconductance correspondin to the ate-source D voltae of GS, and is the first order Taylor series coefficient. Equation (4.4) represents first order Taylor series expansion of transconductance as a function of the ate-source voltae GS. Siilarly the followin expression can e written for, and s s, (4.5) For a fixed transistor ias, the output current due to two tone input voltae is coposed of the fundaental coponents, inter-odulation coponents and haronic coponents. The even order inter-odulation and haronic coponents are widely separated fro F sinal and can e easily filtered usin low Q and-pass filter. epresentin the two tone input in the for

98 84 v i A ( ) t A cos( ) t A cos tcos t cos (4.6) Inorin the even-order inter-odulation and haronic coponents, the output current can e written as i A A cos tcost 8A cos tcos t 9A A cos A cos cos tcost tcost cos tcost tcost A (4.7) The ters that contain third order haronic coponent ω will e reoved y the filterin action of the output tank and can e inored. The third order nonlinearity produced an additional ter at the fundaental frequency ω that cause ain copression for neative and inter-odulation coponents at frequencies (ω +Δω) and (ω -Δω). As entioned efore, the current can e increased to counteract the ain reduction caused y third order non-linearity. The followin analysis reveals that the dynaic adustent of the ias current will also help to reduce third order interodulation coponents. For envelope odulated sinal, the input voltae can e represented as i A( t)cos t, (4.8) where A(t) is the tie varyin envelope. In the case of two tone input, the envelope is siply iven y A os(δωt). If the dynaic ias control circuit produces a ias

99 85 voltae that is proportional to the envelope of the input voltae, the D ias current and correspondin can e approxiate usin first order Taylor series as I D I D I D GS GS I D I D K K e e A( t) A( t) (4.9) The asolute value function y= x is syetric around x= and hence it can e approxiated as a series of even order ters. Since the asolute value function is not differentiale at x=, Taylor series expansion are not valid around x=. Several optiization ethods have een proposed for non differentiale functions that include nuerical aloriths that overcoe the prole of non-continuous derivative and approxiation of the non differentiale function to a continuously differentiale function. However, the first derivative of the asolute value function chanes fro - for x< to for x>. Hence the conventional series approxiation that is ased on the derivative can t e used, instead the coefficients of the function series approxiation is chosen to iniize the error etween the approxiation and the oriinal function. Writin the asolute value function y= x usin only constant ter and second order ter yields y x (4.) x For an input sinal liited to E<x<E, the coefficients α and α is chosen to iniize the ean square error etween approxiation and oriinal function. S E E x x dx (4.)

100 86 To iniize the error, derivative relative to α and α should e ade equal to zero S S, E E, E 5, 6 6E 5 5 4E E (4.) Equation (4.) reveals that the coefficients α and α are function of the axiu envelope sinal aplitude. For a two tone input, the output of ideal envelope detector is iven y en K e A.5A cos( t) K K e K.975A K cos t e e e A cos( t), (4.) where K e is the ain of the envelope detector. In the siple case of two tone input, the spectru of the rectified envelope A cos(δωt) can e otained usin Fourier series t.7a.85a cos t... A cos (4.4) oparin the approxiation in (4.) to the exact solution iven y (4.4) confirs that (4.) represents an acceptale approxiation of the envelope detector output. Since the effect of the fourth order ter will result in second order haronic which has een nelected in (4.), the exact value of the second haronic in (4.4) is slihtly different. Usin (4.9) and (4.) is written in ters of the envelope aplitude K K A ( ), (4.5) e e t

101 87 Usin (4.) and inorin the even-order inter-odulation, the output can current can e expressed as i K K A ( t) A( t)cos t A ( t)cos t K A( t)cos t ( 4) K A ( t)cos t e e e e, (4.6) where even order inter-odulation and hiher order haronics have een nelected in the approxiation. In case of two-tone input, A(t) = A os(δωt), the output current takes the for i K e A cost cos t ( 4) K e 8 A cos t cos t K e (9 4) K e A ( 4) K A cost cos t A cost cos t e (4.7) The condition to cancel third order inter-odulation coponents is.6 Ke ( 4) Ke (4.8) A Usin (4.8), (4.7) reduces to K A cos t t i e cos (4.9) Equation (4.9) reveals that the output consists of the fundaental coponent only and the third order inter-odulation has een eliinated. The precedin analysis has een done takin into account only second order representation of the envelope detector output, a ore accurate analysis can e perfored usin hiher order representation (Fi. 4.7). The third order non-linear coefficient will exhiit variation as GS tracks the input envelope K K A ( ), (4.) e e t

102 88 In addition, ore accurate representation of the asolute value function can e written takin into account up to the fourth order non-linearity y x (4.) 4 x 4x Miniizin the error function as efore, the coefficients α, α, and α 4 are E E 5 E E 4 5E 5,, 4 8 8E 8E 4 5 E 4 7 E 4 5 A A 4 9 A 6 (4.) Usin (4.) and (4.9), can e written as 4 K K A ( t) K A ( ), (4.) e e 4 e t Fi Second and fourth order approxiations of the asolute value function.

103 89 The effect of the dynaic ias on iven y (4.) is nelected in the followin analysis and siulation results will e provided to confir the validity of this assuption. epeatin the analysis for the output current with a two tone input sinal, and usin (4.6) and (4.), the output current for a two tone input sinal is expressed as i Ke A cost cost ( 4) Ke 8 A cos tcost 5 5 K A cos tcost 4 A A A costcost ( 4) K 5 K A A cost cost 9 4 K 4 4 e e A 5 A cos e K e 5t cost 4 e 4 (4.4) The condition to cancel the third order haronic in this case is iven y ( 4) K e K 56 5 e 5 A K 4 e A (4.5) Usin the condition aove, the output current reduces to fundaental coponent and a fifth order inter-odulation product. In order to avoid havin this fifth order interodulation product, GS control should e adusted such that GS 4 K A( t) K A ( ), (4.6) GS e e4 t epeatin the analysis reveals that K e and K e4 can e chosen to eliinate the third and fifth order inter-odulation products. To verify the previous analysis, a power aplifier with envelope linearization has een desined and siulated. Fi. 4.8 shows sinle stae power aplifier scheatic in which envelope sinal is used to linearize the

104 9 aplifier. Fi. 4.9 depict the third order inter-odulation of the aplifier without linearization, with GS = GS +K e A(t), and with GS = GS +K e A (t). F in M Envelope detector Fi Power aplifier linearization usin envelope sinal. GS = GS +KA (t) GS = GS +K A(t) GS = GS IM (dbc) in () Fi Third order inter-odulation versus input aplitude for different control schees.

105 9 As predicted y (4.8), the case in which GS is controlled y the envelope A(t) has a ood IM perforance only at a specific input aplitude. On the other hand if GS is ade dependent on the square of the envelope sinal, the IM is iproved for the whole input aplitude rane. Fi. 4. shows IM5 correspondin to different adaptive ias techniques. The fifth order inter-odulation is not uch different than reference aplifier when GS is ade proportional to the square of the envelope sinal A (t), which confirs the validity of the assuption that the variation in can e nelected. However, for the case of GS = GS + A(t), IM5 is deraded which can e explained y (4.4). GS = GS +KA (t) GS = GS +K A(t) GS = GS IM5 (dbc) in () Fi. 4.. Fifth order inter-odulation versus input aplitude for different control schees.

106 9 As entioned in (4.6) if k A 4 (t) is added to the adaptive transistor ias GS, The third and fifth order inter-odulation is iproved as depicted in Fi. 4. and Fi. 4.. The third order inter-odulation is iproved over wider input rane when copared to the previous case in which GS is only dependent on sinal envelope. GS = GS +K A(t) +K A 4 (t) GS = GS +K A(t) GS = GS IM (dbc) in () Fi. 4.. Third order inter-odulation versus input aplitude with iproved control schee.

107 9 GS = GS +K A(t) +K A 4 (t) GS = GS +K A(t) GS = GS IM5 (dbc) in () Fi. 4.. Fifth order inter-odulation versus input aplitude with iproved control schee. 4.. Efficiency Iproveent Usin Dynaic Bias As entioned efore, for the est efficiency the D current should e op. Hence the est efficiency is achieved when GS = GS + K e A(t), where K e is chosen such that I D is linearly proportional to the output voltae aplitude. Section 4.. shows that K e can e chosen to cancel the effect of third order non-linearity and since third order non-linear coefficient a is typically sall, the required K e is typically sall. In other words, the ias current should e slihtly increased to counteract the ain reduction caused y non-linearities. However, the required K e for ood efficiency is uch hiher, which will e translated into hiher ain variations and hiher third order

108 94 inter-odulation and thus poor error vector anitude (EM). The proposed solution to overcoe this prole is to adust the ain of the preaplifier to have a flat ain and to reduce the inter-odulation coponents. As shown in Fi. 4., the ias of the preaplifier is also ade dependent on the sinal envelope. in PA Driver PA Gate Bias Gate Bias Envelope detector G a G Fi. 4.. Efficiency enhanceent throuh dynaic ias of power aplifier. Assuin that the envelope detector has a ain of unity, the ate-source voltae, D current, and transconductance of the preaplifier can e written as I a GS a D a I a GS a D a I a GS a D a a GS a GS a GS I G a D a a A( t) I a D a G G a a A( t) A( t) (4.7) Siilarly, the ate-source voltae, D current, and transconductance of the ain aplifier are iven y

109 95 ) ( ) ( ) ( A t G A t G I I I I I A t G GS D D GS D D D GS GS GS GS (4.8) Inorin the even order distortion and usin the asolute value second order approxiation iven y (4.), the output voltae of the pre-aplifier oa takes the for t t A G t A t G a a a a a a oa )cos ( 4) ( )cos ( (4.9) The output voltae of the power aplifier o is iven y in a in a in a in a in a in a in a oa oa o (4.) As entioned efore, for the est efficiency, the current should e hihly dependent on the input envelope, which will lead to a stron non-linear ehavior. In order to iniize third order inter-odulation caused y the dynaic ias, a should e approxiately constant for any input level. In fact, a sall second order dependence on the input aplitude will help to copensate for the third order nonlinearity of the transistor. Usin (4.7) and (4.8), a can e approxiated as ) ( ) ( 4 t A G G t A G G G G G G a a a a a a a a a a a (4.) Followin the analysis iven in section 4.., the third order inter-odulation is iniized when ain dependence on the square of the sinal envelope is eliinated.

110 96 a a a G G G a a G A ( t) G a a G a for sall (4.) The forth order dependence on the envelope in (4.) will create unwanted fifth order inter-odulation products. In order to overcoe transistor intrinsic non-linearities, the value of G should e chosen slihtly different than the value iven in (4.) to create a sall aount of third order distortion that cancels third order distortion due to. To overcoe the unwanted fifth order inter-odulation products, the ias voltae of 4 the ain power aplifier should take the for G A( t) G A ( ). GS GS a a4 t 4. Power Aplifier ircuit Ipleentation To verify the proposed efficiency enhanceent technique, a test chip was faricated in UM 9n. The power aplifier is desined to drive a 5Ω load, with axiu output power of aout db usin a supply voltae of.. The D current at the axiu output power is iven y op A. Usin the proposed technique, the current is ade linearly proportional to the input envelope. The coplete PA diara is depicted in Fi. 4.4 where F chokes were replaced y tanks which help to filter the even order inter-odulation as well as sinal haronics. ouplin caps c and c and ias resistors and act as a hih pass filter for the F sinal, and as a low pass sinal for the ias voltae. Since the ias voltae is proportional to the sinal envelope, it can e approxiated as a series that contains even order ters. Hence the ias voltae consists of the even order haronics of the envelope

111 97 and the cutoff of the ias network should e larer than axiu haronic order needed to linearize the aplifier. Since the previous analysis shows that fourth order series represents a ood approxiation of ias voltae dependence on input envelope, the cut off frequency should e larer than 4 ties the envelope andwidth. The constrain on the ias network cutoff can e written as f env,c, 4 f (4.) oa c o c c in M M Envelope detector G a G Fi Power aplifier scheatic. 4.. Envelope Detector Desin The envelope detector circuit shown in Fi. 4.5 is used to extract the sinal envelope fro the F sinal. The transistor M acts as a diode which is connected to the envelope detector cap. esistor and capacitor constitute D decouplin circuit to enale adustent of D ias for proper operation of the envelope circuit. A replica of the envelope detection ranch is used toether with an operational aplifier in order to

112 98 eliinate non-linear effects caused y M variale ate-source voltae [6]. Since the envelope sinal is usually liited to one or several eahertz rane, the ias current of the envelope detector can e ade very sall. The ias currents I and I are chosen to e μa, while achievin,.6a. The envelope detector capacitor is chosen to e 5 PF. The operational aplifier desin used in the envelope detector and the ain locks in Fi. 4.4 is discussed in the followin section. in M M env I I + - o Fi Envelope detector scheatic. 4.. Operational Aplifier Desin The ias voltae of the power aplifier increases as the input voltae increases, hence the ain lock G in Fi. 4.4 should e positive. On the other hand, the preaplifier ias should decrease as the input sinal increases and thus G a should e a neative ain lock. Since the linearity of these ain locks are very iportant, feedack invertin and non-invertin aplifiers shown in Fi. 4.6 are used.

113 99 The sae operational aplifier is used in the envelope detector as well as dynaic ias control circuits. In order to achieve hih efficiency, the power consuption of the op-ap should e iniized while the ain of the op-ap should e hih enouh to achieve ood linearity. a a env - a + + env - (a) () Fi Dynaic ias aplifiers: (a) Gain stae of preaplifier (G a ). () Gain stae of power aplifier (G ). The two stae op-ap visualized in Fi. 4.7 offer hih ain and low power consuption for low GBW. The ias transistors M 5 and M 6 are iased at μa and 5μA respectively. Miller copensation capacitor c is used to achieve ood phase arin, and the resistor c is used to eliinate riht hand plane zero as explained in [6]. The operational aplifier D ain is around 5 db and GBW is aout 85MHz with phase arin of 85 as shown in Fi. 4.8.

114 M 5 M 6 i- i+ o M M c c M M 4 M 7 Fi. 4.7.Two stae op-ap scheatic. Fi Frequency response of the operational aplifier.

115 4.4 Experiental esults The test chip was faricated in UM 9n and it occupies aout.5 of active area. hip icroraph is shown in Fi The power aplifier ain and linearity is easured at 4 MHz. Dynaic ias ircuit PA & Pre- Aplifier Fi Power aplifier chip icroraph. esistors a and in Fi. 4.6 are ade variale with 4 it control accuracy to set the ain of the dynaic ias of oth the pre-aplifier and the ain power aplifier. By switchin the ain of the pre-aplifier dynaic ias control circuit to zero, the reference power aplifier can e characterized without the proposed efficiency enhanceent technique. The ias current of ain power aplifier in this case does increase slihtly as the input power increases to copensate for the ain copression caused y third order transistor non-linearities as explained in section 4... The ain of