An Efficient Multilevel-Synthesis Approach and its Application to a 27-Level Inverter

Transcription

1 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA An fficient MultileelSynthesis Approach and its Application to a 27Leel Inerter P. Satish Kuar, Meber IANG, G. Sridhar, and h. Lokeshwar Reddy Abstract In this paper, an efficient ultileel wae for synthesis technique is proposed and applied to a 27leel inerter. The basic principle of the proposed schee is that the continuous i. output oltae leels can be synthesized by the addition or subtraction of the instantaneous oltaes enerated fro different oltae leels. This synthesis technique can be realized by an array of switchin deices coposin fullbride inerter odules and proper ixin of each transforer terinal oltae. The ost different aspect, copared to the conentional approach, in the synthesis of the ultileel output waefor is the utilization of a cobination of transforers rather than the accuulation of capacitor oltae sources. A 27leel inerter consists of three fullbride odules and their correspondin transforers. Quasisinusoidal oltae waes can be enerated fro a suitable selection of the turn s ratio of the transforer. The alidity of the proposed schee is erified by the siulation. Keywords Multileel inerter, synthesis, cascaded connection, Total Haronic Distortion. I. INTRODUTION H Multileel inerters hae eered as a new kind of Tpowerconersion systes. General ultileel inerters hae an arraneent of power switchin deices and capacitor oltae sources. By the control of the switchin deices, they can synthesize stepped output oltaes with low haronic distortions. The principal otiation for ultileel topoloies is the increase of power, the reduction of oltae stress on the power switchin deices, and the eneration of hihquality output oltaes and sinusoidal currents. The ultileel inerter synthesizes a 27leel output oltae with considerably i. Reduced haronic coponents. ii. opared to the onentional approaches, considerin the sae outputoltae leel of a 27leel inerter; it can sae on the nuber of the ain switches and diodes up to 77% without considerin the power ratin of the deices. Manuscript receied July 11, 2013; reised Auust 16, P. Satish Kuar is workin as Assistant Professor with the Departent of lectrical nineerin, Uniersity ollee of nineerin, Osania Uniersity, Hyderabad, Andhra Pradesh, INDIA, (eail: satish_8020@yahoo.co.in). G. Sridhar is with the Departent of lectrical and lectronics nineerin, Jyothishathi Institute of Technoloy & Science, Karinaar, Andhra Pradesh, INDIA. h. Lokeshwar Reddy is with the Departent of lectrical and lectronics nineerin, VR ollee of nineerin, Hyderabad, Andhra Pradesh, INDIA. iii. In addition, the ate aps and their independent oltae sources are proportionally reduced to the nuber of the used switches. In the iewpoint of the latter, three presentable topoloies can be considered for ultileel inerters: diode claped (or neutral claped), flyin capacitors (or capacitor claped), and cascaded Hbride cells with separate dc sources. Theoretically, they can synthesize an infinite outputoltae leel. By increasin the nuber of leels in the inerter, the output oltaes hae ore steps eneratin a staircase waefor, which has a reduced haronic distortion. Howeer, a lare nuber of leels increase the nuber of switchin deices, ate ap, Diodes and other passie eleents. Moreoer, it causes control coplexity and introduces oltaeibalance probles. onsequently, these ultileelinerter schees are not suitable for increasin the outputoltae leels because of their lare nuber of switchin deices. To increase the nuber of the output oltae leels in order to obtain hihquality output oltae waefors by eans of ultileelinerter schees, the aboe probles should be soled in adance. In this paper, an efficient ultileelwaefor synthesis technique is suested and a new ultileelinerter topoloy and its control schee are presented. It consists of three fullbride inerter odules and their correspondin three transforers, which hae a series connected secondary windin. II. BASI PRINIPL OF TH PROPOSD MULTILVL SYNTHSIS onentional ultileel inerters include an array of switchin deices and capacitor oltae sources, the output of which enerate oltaes with stepped waefors. The coutation of the switches perits the addition of the capacitor oltaes, which reach hih oltae at the output, while the switchin deices withstand only reduced oltaes. Fi. 1(a) shows a basic concept of the eneral ultileelwaefor synthesis ethod with different nubers of leels, for which an ideal switch with seeral positions represents the action of the switchin deices. A twoleel inerter enerates an output oltae with two alues with respect to the neatie terinal of the capacitor, while the threeleel inerter enerates three oltaes. Fi. 1(b) shows a basic principle of the proposed ultileelwaefor synthesis ethod. onsiderin the array of indiidual oltae Sources hain different alues, the continuousoutputoltae leels can be synthesized by the WS 2013

2 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA selection of suitable switchin cobinations. In the proposed ultileel schee, this can be realized by an array of switchin deices coposin full bride inerter odules and proper ixin of each transforer terinal oltae. The ost different aspect, copared to the conentional approach, in the synthesis of the ultileel output waefor is the utilization of a cobination of transforers rather than the accuulation of capacitor oltae sources. deterines the aplitude of output oltae. Fi. 2(b) shows a cascaded connection of the secondary turn s ratio of the transforers to obtain a lare nuber of outputoltae leels. In the leel selection of the output oltae, it should be noted that the focuses are both the result of the outputoltae cobination of the inerter and the deterination of the turn s ratio of the transforer, which can synthesize a continuousoutputoltae leel with an interal ratio. Because each fullbride inerter odule can enerate three leels, the required turn s ratio of the secondary windin, which can enerate a continuousoutputoltae leel with an Interal ratio, can be selected as k 1 ak a.3, k 1,2,3... (1) Here, k eans the rank of the stacked transforers in series, and a is deterined by the turns ratio of the transforer. Fi. 1. Basic concept of the eneral and proposed ultileel waefor synthesis a) General approach; b) proposed ethod III. PROPOSD MULTILVL INVRTR Fi. 2(a) shows a sinlephase fullbride inerter connected with a transforer. The output oltae V o appears as av dc, 0, and av dc accordin to the ON OFF conditions of switchin deices, where a is the secondary turns ratio of the transforer. Therefore, the output oltae can be deterined by the dc input oltae and the turns ratio of the transforer. Because a eneral Inerter syste has a constant dc input source, it is desirable that the turns ratio of the transforer Fi. 2. Basic concept of the proposed ultileel waefor synthesis; (a)sinle phase full bride inerter odule; (b) ascaded connection of the secondary windin of the transforer WS 2013

3 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA TABL I AH TURNS RATIO OF TH SONDARY WINDING OF TH TRANSFORMR IN TH SRIS ONNTION Transforer Rank Turnratio 1 α 1 a 2 α 2 3a 3 α 3 9a 4 α 4 27a 5 α 5 81a K α k 3 k1 When the input oltae is V ab, therefore, its alue deterines the difference between output leels. Table I illustrates the secondary turns ratio of the transforer. The possible nuber of outputoltae leels when it eploys n nuber of transforers is written as n Vn 3, n 1,2,3... (2) Where n is the nuber of cascaded transforers. The switchin functions of sinlephase fullbride inerter shown in Fi. 2(a) are suarized as Fi. 3. quialent circuit of the proposed ultileel inerter eployin cascaded three transforers with a series connected secondary windin S FB =1: Q2, Q3 = ON S FB =0: Q1, Q3 (or Q2, Q4) = ON S FB = 1: Q1, Q4 = ON. (3) With the switchin functions as defined in eq. (3), the oerall output oltae (V o ) of the proposed inerter is expressed as V0 S FB. an. Vdc (4) n n1 Fro the result of eq.(4), it can be found that three transforers hain a seriesconnected secondary windin can synthesize a 27leel output oltae and an 81leel output oltae with four transforers. If the nuber of transforer is boundless, the outputoltae leels are infinite, which is siilar to the analo one. Howeer, a lare nuber of transforers can be a cause of cost increase and anufacturin probles. Therefore, It should be selected considerin the aplitude of input oltae, the THD of output oltae, and the syste price. The equialent circuit of the proposed ultileel inerter eployin three transforers with a seriesconnected secondary windin is shown in Fi. 3. In this fiure, the output oltae by the switchin function can be rewritten as Vo S wherea FBn 1. a. V n a, a 2 dc (9S 3a, a FB3 3 3S FB2 9a, and, S S FBn FB1 ). av. dc. {1,0, 1}...(5) Fi. 4. xpected output oltae leels and each terinal oltae of the transforer Fi. 4 shows the expected outputoltae leels and each terinal oltae of the transforer. It is ery useful to understand the ultileel synthesizin procedure. Table II lists the switchin functions accordin to each outputoltae leel in the case of positie output oltae. For a neatie case, they can be easily obtained by ultiplyin 1 to Table II. WS 2013

4 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA In the case of SFB3, which is the switchin function of the lowest inerter odule, it takes a nauht when a desired output leel is equialent or lower than a fourth leel in Table II. In contrast, it takes a unity when a wanted outputoltae leel is hiher than the fourth leel. The switchin function SFB3 can be expressed by usin eq. (6). For the sake of conenience, we just deal with the positie portion ien in Table II. Here, all ariables are considered as an inteer. If ( 4) then S FB3 = 0 If ( > 4) then S FB3 = (6) Here, eans the nuber of outputoltae leels. The switchin function SFB2 of the iddle inerter is deterined as ( 1) if 0, %3 then S FB ( 1) if 1,... 3%3 then S 2 FB ( 1) if 2, (7) 3%3 then S FB Where % is a odulus operator. The switchin function SFB1 of the upper inerter is deterined by 1 can be perfored by a quarter portion of one period. As the possible axiu nuber of output leels for the positie portion is 13, except for zero, the aplitude of the quarter sine wae is diided into 13, with the sae heiht. Then, t 1 t 13 are deterined. Fi. 5(b) shows the ethod to deterine the duration of a correspondin outputoltae leel. The outputoltae leel is deterined by an aerae alue between points A and B, which are selected by coparison with the reference oltae. if (%3) = 0 then S FB1 = 0 if (%3) = 1 then S FB1 = 1 if (%3) = 2 then S FB1 = 1..(8) TABL II SWITHING FUNTIONS AORDING TO OUTPUT VOLTAG LVL Output leel () S FB3 S FB 2 S FB Fi. 5(a) shows the coand oltae of the inerter and its outputoltae waefor. Because it has a syetric confiuration, the selection of the output leel and its correspondin duration, which define the switchin functions, Fi. 5. Reference and output oltae of the proposed ultileel inerter a) Reference and output oltaes for ¼ cycles; b)deterination of correspondin duration The outputoltae leel is selected between one leel lower and the upper one copared to a desired output leel. The aintainin tie (T ) of the output oltae V dc is ien by this fiure as T p1 T p. In order to deterine those durations, the output oltae is noralized by 13aVdc; then, each leel s duration is ien as 1 1 ( )13 sin 1 avdc T, 1,2,3,......(9) Vp Where V p is the peak alue of the noralized coand sine oltae, and eans the nuber of the outputoltae leel. In eq. (9), is calculated up to the nuber that arcsine is not exceedin unity. It is proportional to the aplitude of the output coand oltae, and it has a axiu alue of 13. A control block diara of the proposed ultileel inerter is shown in Fi. 6. It basically depends on the traditional proportional and interation (PI) control. The reference oltae V ref is enerated by the feedback of the output oltae ia the PI controller. It is used to deterine and calculate the output oltae leel and its correspondin duration. WS 2013

5 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA AN FFIINT TWNTY SVN LVL MULTILVL INVRTR Discrete, Ts = 5e005 s powerui Out1 Out2 Out3 Scope 2 Q1 Q3 Out4 pulse for FB 1 Voltae Measureent 1 Scope 5 FULL BRIDG Q2 Q4 1: a1 Scope Out1 Scope 1 Out2 Out3 Q1 3 Out4 FULL BRIDG 2 pulse for FB 2 LOAD 1 2 Voltae Measureent Q2 Q4 1: a2 Voltae Measureent 2 sinal THD Out1 Out2 Scope 3 TOTAL HARMONI DISTORTION Fi. 6. ontrol block diara of the proposed ultileel inerter IV. SIMULATION RSULTS AND ANALYSIS The alidity of the proposed synthesis approach is erified by the siulation usin MATLAB/siulation. The outputoltae waefor has a 27leel output oltae waefor by the cobination of the seriesconnected transforers 1: a, 1: 3a, and 1: 9a in sequence. The siulation diara of 27leel ultileel inerter is shown in Fi. 7. The ate sinals applied to the switches of proposed inerter are shown in Fi. 8. As shown in Fi. 9 the outputoltae waefor with Rload is ery siilar to a sinusoidal one, owin to a lare nuber of outputoltae leels. In addition, the output oltae will turn into a ore sinusoidal wae if the output load current increases, since the inductance coponents of cascaded transforers are operated as a hihperforance filter; it will be proed fro Fi. 9 and Fi. 10. The Fi. 11 and Fi. 12 shows the fast Fourier transfor (FFT) results of the output oltae with a Rload and an inductie load respectiely. Fro these results, it is clear that the proposed ultileel inerter in hiher load conditions can enerate a ore sinusoidal output oltae than those cases of a lower or a noload condition. The ost outstandin adantae of the proposed ultileelinerter schees is the reduced ain switchin deices and diodes. Forty switchin deices can be saed without considerin the current ratin of the used switchin deices. In addition; the ate ap is proportional to the nuber of the switchin deices. The proposed ultileel approach is suitable for constant oltae and constant frequency (VF) applications such as uninterruptible power supply (UPS) and photooltaic inerter systes because of the property of the transforer used. Howeer, this ethod is not desirable for the otor dries eployin ariablefrequency (VF) control ethod because of the transforer saturation. FULL BRIDG 3 Q1 Q2 Q3 Q : a3 Out3 Out4 pulse for FB 3 Voltae Measureent 3 Fi. 7. Siulation diara for an fficient 27 Leel Multileel Inerter with LLoad Display Scope 4 Tie (s) Fi. 8. Gate sinals applied to IGBTs WS 2013

6 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA Tie (s) Tie (s) Frequency(kHz) Fi. 9. Waefors of the proposed 27leel inerter with Rload Frequency(kHz) Fi. 10. Waefors of the 27leel inerter with inductie load Fi. 11. FFT Analysis for Resistie load Fi. 12. FFT Analysis for Inductie load WS 2013

7 Proceedins of the World onress on nineerin and oputer Science 2013 Vol I WS 2013, 2325 October, 2013, San Francisco, USA V. ONLUSIONS The basic principle of the suested ultileelinerter schee is that the continuousoutputoltae leels can be synthesized by the addition or subtraction of the instantaneous oltaes enerated fro different oltae leels. In the proposed ultileel inerter, this can be realized by an array of switchin deices coposin fullbride inerter odules and proper ixin of each transforer terinal oltae. The ost different aspect, copared to the conentional ultileel approaches, in the synthesizin of the ultileel output leels is the utilization of a oltae cobination of transforers rather than the accuulation of capacitor oltae sources. In addition, the ate aps and their independent oltae sources are proportionally reduced to the nuber of the used switches. The Validity of the proposed ultileelsynthesis schee is erified throuh siulation results for a 27leel inerter. RFRNS [1] J. Rodriuez, J. S. Lai, and F. Z. Pen, Multileel inerters: A surey of topoloies, controls, and applications, I Trans. Ind. lectron., ol. 49,no. 4, pp , Au [2] J. S. Lai and F. Z. Pen, Multileel conerters A new breed of power conerters, I Trans. Ind. Appl., ol. 32, no. 3, pp , May/Jun [3] Hochraf, R. Lasseter, D. Dian, and T. A. Lipo, oparison of ultileel inerters for static ar copensation, in Proc. I Industry Applications Society (IAS) onf., Dener, O, 1994, pp [4] M. Manjreker and G. Venkataraanan, Adanced topoloies and odulation strateies for ultileel inerters, in Proc. I Power lectronics Specialists onf. (PS), Baeno, Italy, 1996, pp [5] Newton and M. Suner, Multileel conerters a real solution to ediu/hiholtae dries?, Power n. J., ol. 12, no. 1, pp , Feb [6] S. Shu, G. Sinha, M. D. Manjrekar, and T. A. Lipo, Multileel power conersion An oeriew of topoloies and odulation strateies, in Proc. Optiisation lectrical and lectronic quipents, Braso, Roania, 1998, pp [7] Nabae, I. Takahashi, and H. Akai, A neutralpoint claped PWM inerter, I Trans. Ind. Appl., ol. IA 17, no. 5, pp , Sep./Oct [8] T. A. Meynard and H. Foch, Multileel conersion: Hih oltae coppers and oltaesource inerters, in Proc. I Power lectronics Specialists onf. (PS), Toledo, Spain, 1992, pp [9] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, A non conentional power conerter for plasa stabilization, in Proc. I Power lectronics Specialists onf. (PS), Kyoto, Japan, 1988, pp P. Satish Kuar was born in Karinaar, Andhra Pradesh, INDIA in He obtained the B.Tech. deree in lectrical and lectronics nineerin fro JNTU ollee of nineerin, Kakinada, INDIA in He obtained M.Tech deree in Power lectronics in 2003 and Ph.D. in 2011 fro JNTUH, Hyderabad. He has ore than 17 years of teachin experience and at present he is an Assistant Professor in the Departent of lectrical nineerin, Uniersity ollee of nineerin, Osania Uniersity, Hyderabad, INDIA. His research interests include Power lectronics, Special Machines, Dries and Multileel inerters and uidin seen research scholars. He presented any research papers in arious national and international conferences and published any papers in arious international journals. He is the ditorial Board eber of any international journals. At present he is actiely enain in two Research Projects in the area of ultileel inerters funded by Uniersity Grants oission (UG), New Delhi, and Science and nineerin Research Board (SRB), New Delhi. India. G. Sridhar obtained the B.Tech. deree in electrical enineerin fro Uniersity of Madras, INDIA in 2000 and M.Tech. deree in power systes with ephasis on hih oltae enineerin in 2005 fro JNTU ollee of enineerin, Kakinada. He is pursin Ph.D. deree in the area of ultileel inerters. He has 13years teachin experience. He is workin as Associate Professor in the Departent of lectrical and lectronics nineerin, Jyothishathi Institute of Science and Technoloy, Karinaar. His research interests include Power lectronics and Multileel inerters. h. Lokeshwar Reddy was born in Khaa, Andhra Pradesh, INDIA in He obtained the B.Tech. deree in electrical enineerin fro KITS Waranal, A.P., INDIA in 1999 and M.Tech. deree in Hih Voltae nineerin in 2001 JNTU ollee of enineerin, Kakinada. He is pursin Ph.D. deree in the area of ultileel inerters. He has 12 years teachin experience. He is workin as Associate Professor in the Departent of lectrical and lectronics nineerin, VR ollee of nineerin, Hyderabad. He presented any research papers in arious national and international conferences and journals. His research interests include Power lectronics Dries and Multileel inerters. WS 2013