A Cascaded Hybrid Inverter with Improved DC-Link Voltage Control for Grid Connected Systems

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1 A Cascaded Hybrid Inerter with Improed DCLink Voltage Control for Grid Connected ystems T.Wanjekeche, A.A.Jimoh and D.V. Nicolae Department of Electrical Engineering Tshwane Uniersity of Technology Abstract This paper presents inestigation of a new Phase shifted PWM technique with improed harmonic suppression. A noel balance circuit for DC link oltage balance of two three leel legs connected back to back is designed and tested. Combined with the indiidual oltage control, a complete oltage controller is deeloped for a cascaded nine leel hybrid model with two cells. Robustness of the proposed algorithm under arying operating conditions and modulation indices is erified by simulation. Index Terms DC link oltage balance, Hybrid Cascaded inerter, Grid connected systems, PWM inerter, power quality I. INTRODUCTION In recent decades the electric power systems has suffered significant power quality problems caused by the proliferation of non linear loads, such as arc furnace lighting loads adjustable ac dries etc., which causes a large amount of characteristic harmonics, low power factor and significantly deteriorates the power quality of the distribution system [3]. The increasing restrictie regulations on power quality hae significantly stimulated the deelopment of power quality mitigation equipments. For high power grid connected systems, the classical two leel or three leel conerters topology are insufficient due to the rating limitations imposed by the power semiconductors [4,5]. Hence considerable attention has been focused on multileel inerter topologies, which significantly improes the output waeform spectrum of the inerter. This important multileel technology has found widespread application in medium and high oltage electric dries, renewable energy grid interface, power conditioning, and power quality application [6] [8]. For diode clamped multileel inerter, if a higher output oltage is required one of the iable methods is to increase the number of inerter oltage leels. For NPC inerter oltage can only be increased up to fie leels beyond which DC oltage balancing becomes impossible. For single Phase H Bridge inerter, an increase in the number leels leads to increase in the number of separate DC sources. The proposed hybrid model is deeloped by combining the NPC and H bridge topologies [9] and thus reducing the number of separate DC sources. Past research on the model has concentrated on realizing control technique for DC capacitor oltage balance for an output oltage of up to 5leels and it has been indicated that is too complicated to balance capacitor oltage for a diode clamped conerter with more than fie leels. This paper proposes a more accurate and faster external balancing circuit for compensating oltage imbalance in one cell of hybrid inerter model, combined with aerage oltage control, a complete oltage controller is deeloped for a single phase cascaded nine leel hybrid model. II. PHAE HIFTED PWM CONTROL TRATEGY FOR A 9LEVEL CACADED HYBRID MODEL Fig. shows the schematic diagram of the NPC/Hbridge model, which consist of two legs connected to a common bus. The symbol p and n denotes the positie and negatie rail of the model. Each phase leg is modulated in complementary manner by a carrier/reference comparison circuit. Phase disposition (PD) PWM technique is used as it has superior harmonic suppression in line to line oltage []. The figure illustrates the process of generating three leel PWM output at legs a and b. The three leel PWM output from leg a can be obtained by subtracting p from n to output oltage V a as shown in figure 2. The two legs are modulated with 8 degrees opposed reference defined as: g a ( t) = V dc M cos( ω s t) g ( t) = V M cos( ω t π ) b dc s Equation () is alid under the assumption that; V = V 2 = V i.e the capacitors are balanced. Based on the aboe PWM technique, an improed phase shifted PWM control strategy is proposed in this paper. To aoid the complexity of negatie and positie legs, the paper uses the principle of decomposition where the whole system is considered as a four 3leel legs and each leg is treated independently giing three leel output () /2/$3. 22 IEEE 95

2 p n V V dc V Fig. 2. Control signal and output waeform of leg V cr g a(t) V cr t V cr2 g b(t) Fig. chematic diagram of one cell of NPC/Hbridge inerter model and its PWM switching technique V cr Each two of the four legs are connected back to back and they share the same oltage source V dc. Thus, you need to decompose a 9 leel operation to 4x3 leel sub operations. PD modulation is used for achieing three leel output [7]. Fieleel oltage is achieed using two carriers on two threeleel legs under PD modulation as shown in fig. 3. By using the same carriers phase shifted by constant alue of π/4, a 9 leel output is achieed as shown in fig. 4. It should be emphasized that for any number of leels, the two carriers are phase shifted by constant alue of π/4. A detailed explanation using double Fourier transform on how a phase shift of π/4 was chosen can be found in []. g a (t) Fig.3. PWM scheme and output oltage waeform for one cell of the hybrid inerter p n Fig. 4. PWM scheme and output oltage waeform for a 9leel hybrid cascaded 95

3 III. CONVERTER CONTROL A. Feedback Control Technique Fig. 5 shows a cascaded 9leel hybrid inerter model inerter connected to the grid, since the flow of power is always from the dc source to the grid. The system consists of 2 DC capacitors, 2 inerter cells, LCL filters and the grid. From fig. 5, controller architecture for a nine leel cascaded NPC/Hbridge inerter based grid connected systems is designed as shown in fig.6. The control strategies to be tested are; the grid synchronization using the Phase Locked Loop (PLL); the current reference scheme; the oltage balance technique for lower and upper dc capacitors, indiidual oltage balance among indiidual cells and robustness of the dc oltage balance technique under changing loads and changing dc sources. DC capacitor oltage for multileel conerter with little success in conerters with higher leels (more than fie), [2] [4]. Under normal operation, the aerage DC capacitor oltage of an NPC conerter can be controlled by slightly shifting sinusoidal modulating wae of Phase shifted hybrid PWM technique. Thus V of upper capacitor is equal to of lower capacitor. This implies charging current Idc is symmetrical and current drawn from the neutral point oer modulation cycle is zero and neutral potential is constant. But during transient operation or when there is phase to phase imbalance in the output switching pattern, a none zero neutral current is present, and this means that the charging and discharge of capacitors C2 and C is not identical. Fig. 6 which clearly shows that if the two dc link capacitors has the same alue, the currents ic and ic2 can be described by equation (2). In order to produce reference oltage alue (Vdc/2), the locally aeraged currents should as shown in equation (3) The phase angles are detected from the grid oltage V sa to perform PLL. As a result sine and cosine terms which are synchronized with the grid oltage are achieed. The obtained current is used as grid reference current for d channel. For the grid current control, there are two main control loops, i sd for the actie power control and i sq for the reactie power control. The tuning of the compensator is made for only one loop assuming that both of them hae the same dynamics. By tracking current signal using current reference generated by the phase oltage of the grid, grid oltage and current are in phase. The aim is to ensure maximum power injection to the grid at unit power factor. Vdc i cm C (NP) C2 i c V i c2 i Fig. 6 Current path in capacitors (3) i i = i c cm 2 i, i = i c2 cm 2 (2) i i = i = C c cm 2 i i = i = C c2 cm 2 V dc V dc V 2 ) T s V 2 ) T s (3) Fig. 5. chematic diagram of the proposed grid interface system based on 2 cells cascaded hybrid inerter model B. Balancing of the DC Capacitor Voltage A lot of research of research has been done on balancing of Where Ts is the sampling or switching period and i cm is the common current through both capacitors. If the total dclink oltage is constant, for example, imposed by the power supply, the current is zero. imilarly, if the oltage is not absolutely 952

4 . I dc V V dc V dc V Voltage balance circuit Cell N L I dc2 V 2 V an V V dc2 V dc2 V 2 Voltage balance circuit Cell 2 N L 2 V 2 V dc2 V dref 2 V = V dc( a) 2 dci i = 2 V dc Controller K I K P V dc2 Controller K K P P K I K I I saref i K x K P V dc(a) Controller cosθ x x I sa /V dc /V dc2 Current Controller Current control loop i I NPC/H bridge cell NPC/H bridge cell 2 V sa PLL sinθ Fig.7.Control structure of cascaded 9 leel hybrid topology constant but controlled by a proper control loop or external balance circuit as proposed below, the aerage current is still zero. Consequently subtracting the second equation from first one in equation (3), the reference alue for the locally aeraged NP current is defined by; V V io C 2 T = (4) This paper proposes a oltage balancing circuit to correct the deiation (V) in the capacitor oltages as shown in equation (4). The balance circuit shown in fig. 8 is chosen because it regulates the indiidual capacitor oltage independently without interfering with other oltage control techniques such as indiidual oltage control per cell (Vdc and (Vdc2). Fig. 7 shows a system configuration for a nine leel hybrid inerter model equipped with proposed oltage balance circuit per indiidual capacitor oltage. C. imulation Analysis of a Cascaded 9 leel Hybrid Inerter model To check the alidity of the designed small signal model, MATLAB simulation was carried out. For the LCL filter Table I is as gien below. The selection of the type of inductors and capacitors is a compromise between performance, size and cost and the equations describing the operation of oltage and current control loops has been already deeloped [5]. Therefore for the sake of space, they will not be detailed in this paper, thus the system controller parameters are gien in Table II for the sake of completeness 953

5 D. imulation Results and Discussions The alidity and robustness of the proposed control scheme was tested by carrying out seeral simulations under arious enironmental conditions. For the oltage balance circuit, Figure 9 and shows the upper and lower DC link capacitor oltages without the balance circuit first at M =.8, then M is reduced to.5 and (c) is the capacitor oltages with the balance circuit at both M=.5 and.8. The model is switched with a steady state load of 2 KW at t =.7 sec. This clearly illustrates that one capacitor is charging and another one is discharging this leads to deiation in oltage and hence neutral current which results in distortion of output oltage. It can be seen that the proposed oltage balance works well in the modulation index range of.8 to V Fig. 8. Voltage Balance circuit for upper (V ) and lower DC link capacitor (V 2) per hybrid cell TABLE I YTEM COMPONENT PARAMETER ymbol Parameter Value V s_x AC source oltage (grid 6 V,5 Hz oltage) L f Inerter side inductance.45 mh R f intern resistance of L f2, inerter mω side inductance C f Filter capacitance 9.4 µf L f2 Grid side inductance.5 mh R f2 intern resistance of L f2, grid mω side inductance Rd Damping resistor in series with.6 Ω C(not shown) C =C 2 DC link capacitors.42 F TABLE II YTEM CONTROLLER PARAMETER ymbol Parameter Value T sample ampling period 33 µ K P_In_Vx Voltage control gain (proportional 4 gain) K P_In_Vx Voltage control gain (Integral element) K i I_In_Ix Current control gain (Proportional.5 gain) K i I_In_Ix Current control (Integral element) 2 m a Amplitude Modulation V 954

6 5 4 V 8 Vdc` Fig. 9 Capacitor oltages at normal operating condition without oltage balance for M=.8 without oltage balance for M=.5 (c) with oltage balance circuit at both M=.5 and.8 (c) 5 4 Vdc Vdc2 3 To inestigate the robustness of the proposed DClink capacitor balance technique, different resistances at the upper and lower capacitors are used. The resistie load of the upper capacitors changes from 5 Ω to Ω while the lower one changes from 5 Ω to 5 Ω at t = 2sec. fig., and (c) shows the DC link oltage of the upper and the lower DC link oltage, indiidual cell DC oltage and the two DC link oltages for the two cells respectiely with the conentional control scheme, i.e. without the DC link oltage balancing algorithm. Note from fig. 7 there many ripples in the total DC link oltage for the cells Vdc in and also both Vdc and Vdc2 in (c) due to the distortion in the oltage ector which comes from the unbalance of the upper and lower oltages. The upper DC link oltage reaches 65 V from the normal rating of 5 V. This high oltage can cause serious damage on the deices when the oltage ratings of the DC link capacitors or switches are less than 65 V (c) Fig.. Response of the DC link oltages when two different load resistances are connected at t = 2sec. to the upper and lower DC link capacitances (5 Ω to Ω) and lower (5 Ω to 5 Ω). Upper and lower DC link oltages One cell total DC link oltage (c) Two cells total DC link oltages, without oltage balance algorithm The simulation results with the proposed DC link oltages balancing algorithm are shown in fig., and (c). The lower and upper oltages are balanced well without ripples just as fig. (c) and the total DC link oltage is without oltage distortion. well without ripples just as fig. (c) and the total DC link oltage is without oltage distortion V 4 3 V

7 Powered by TCPDF ( 8 6 Vdc problem to achiee in multileel conerters unless a complex technique is adopted. In addition, the robustness of the DC balance technique clearly shows that control scheme applied on this model is a preferred choice for obtaining a sinusoidal oltage output with a arying DC source (photooltaic cells) Vdc Vdc (c) Fig.. Response of the DC link oltages when two different load resistances are connected at t = 2sec. to the upper and lower DC link capacitances (5 Ω to Ω) and lower (5 Ω to 5 Ω). Upper and lower DC link oltages One cell total DC link oltage (c) Two cells total DC link oltages, with oltage balance algorithm. IV. CONCLUION The article has deeloped an improed topology that can be used to achiee a nine leel NPC/HBridge PWM inerter. It has been clearly shown that fie leel NPC/H Bridge inerter that has been proposed by many researchers gies a higher THD which is not acceptable in most high and medium power application unless a filter is used. And since there is limited research on cascaded this important hybrid model, the paper has deeloped a noel phase shifted PWM control technique that was tested on a two cell cascaded hybrid inerter model. In the proposed control technique it has been shown that by properly phase shifting both the modulating wae and the carrier, a nine leel oltage output can be achieed with a suppressed harmonic content as compared to the conentional PWM approach. Finally with the proposed simple DCbalance control algorithm, it has been shown that the technique can easily be applied to control DC capacitor oltage for output oltage leels of more than fie which has been a REFERENCE [] T. Benslimane, Open witch Faults Detection and Localization Algorithm for Three Phase hunt Actie Power Filter based on Two Leel Voltage ource Inerter, Electronics and Electrical Engineering Conf. No. 2(74), pp. 2 24, 27 [2] L.G. Franquelo, J.Rodriquez, J.I. Leon,. Kouro, R. Portillo and M.A.M. Prats, The Age of Multileel Conerters Arries, IEEE Industrial Electronics Magazine, pp. 2839, June 28 [3] R. Gupta, A. Ghosh and A. Joshi, witching Characteristics of Cascaded Multileel Inerter Controlled ystems IEEE Trans. Ind. Electr., ol.55, no.3, pp , 28 [4]. Kouro, J. Rebolledo and J. Rodriquez, Reduced switching frequency modulation algorithm for high power multileel inerters, IEEE Trans. Ind. Electr., ol.54, no.5, pp , Oct., 27 [5] D.G. Holmes and B.P. McGrath, Opportunities for harmonic cancellation with carrier based PWM for two leel and multileel cascaded inerters, IEEE Trans. Ind. Appl., ol. 37, no. 2, pp [6] F. Z. Peng, J.. Lai, J. W. McKeeer, J. VanCoeering, A Multileel Voltageource Inerter with eparate DC ources for tatic Var Generation, IEEE Transactions on Industry Applications, ol. 32, no. 5, pp. 338, ept. 996 [7] J. Rodriguez, J.. Lai and F. Z. Peng, Multileel Inerters: urey of Topologies, Controls, and Applications, IEEE Transactions on Industry Applications, ol. 49, no. 4, pp , Aug. 22. [8] J.. Lai, F. Z. Peng, Multileel Conerters A New Breed of Power Conerters, IEEE Transactions on Industry Applications, ol. 32, no. 3, pp. 5957, May 996 [9] C.M.Wu, W.H. Lau and H.Chung, A fieleel neutralpointclamped Hbridge PWM inerter with superior harmonics suppression: A theoretical analysis, IAC 99, proceedings of the 999 IEEE international symposium, ol. 5, pp.982, 999 [] D. G. Holmes, A general analytical method for determining the theoretical harmonic components of carrier based PWM strategies, in Conf. Rec. IEEEIndustrial Application ociety Annual Meeting, pp , 998. [] T. Wanjekeche, D.V. Nicolae and A.A. Jimoh, A Cascaded NPC/Hbridge inerter with simplified control strategy and minimum component count, IEEE Africon, pp. 6.eptember, 29. [2] Peng F Z, A generalized multileel inerter topology with self oltage balancing, IEEE Trans. on Industry Applications, ol. 2, pp. 668,2 [3] Y. Chen, B. Mwinyiwiwa, Z.Wolanski, and B. T. Ooi, Regulating and equalizing dc capacitance oltages in multileel TATCOM, IEEE Trans. Power Del., ol. 2, no. 2, pp. 9 97, Apr [4] M. Marchesoni, and P. Tenca, Diodeclamped multileel conerters: a practicable way to balance DClink oltages, IEEE Transactions on Industrial Electronics, ol. 49, no.4, pp , August 22. T. Wanjekeche, Design and analysis of sinusoidal pulse with modulation techniques for oltage source inerter in UP application, M. Eng thesis, Harbin Institute of Technology, China,