11 LEVEL SWITCHED-CAPACITOR INVERTER TOPOLOGY USING SERIES/PARALLEL CONVERSION

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1 11 LEVEL SWITCHED-CAPACITOR INVERTER TOPOLOGY USING SERIES/PARALLEL CONVERSION 1 P.Yaswanthanatha reddy 2 CH.Sreenivasulu reddy 1 MTECH (power electronics), PBR VITS (KAVALI), pratapreddy.venkat@gmail.com 2 M.TECH, Associate professor & H.O.D EEE DEPT PBR VITS (KAVALI), csr.reddy@yahoo.co.in Abstract--In this paper a novel boost switchedcapacitor inverter is proposed. The circuit topology was introduced. The modulation method, the determination method of the capacitance, and the loss calculation of the inverter proposed. In this paper, an SC inverter whose structure is simpler than the conventional SC inverter is proposed. It consists of a Marx inverter structure and an H-bridge. The proposed inverter can output larger voltage than the input voltage by switching the capacitors in series and in parallel. The maximum output voltage is determined by the number of the capacitors. The proposed inverter does not have any inductors can be smaller than a conventional two-stage unit which consists of a boost converter and an inverter bridge, which make the system large. The structure of the inverter is simpler than the conventional switched-capacitor inverters. THD of the output waveform of the inverter is reduced compared to the conventional single phase full bridge inverter as the conventional multilevel inverter. In this paper, 11 level circuit configuration, the theoretical operation, and the simulation results with MATLAB / SIMULINK. Index Terms Charge pump, multicarrier PWM, multilevel inverter, switched capacitor (SC). I. INTRODUCTION Recently, electrical energy systems, electric vehicles (EVs), and dispersed generation (DG) systems, etc., are focused because of the global environmental issues. The power electronics, converters and inverters, is a key technology in these systems. The EVs and the grid connected DG systems need an inverter to convert dc to ac. Boost converters or transformers are widely used in these systems when the input voltage is smaller than the output voltage. However, a transformer or an inductor in the boost converter makes the system large, because the transformer and the inductor must have large and heavy magnetic cores to sustain the high power. As a provision against the issue, a charge pump, which does not have any inductors, is applied to such systems. A charge pump outputs the larger voltage than the input voltage with switched capacitors [6]. When the several capacitors and the input voltage sources connected in parallel, the capacitors are charged. When the capacitors are switched by the switching devices between the capacitors, several capacitors are connected in series and discharged. The voltages of the capacitors are added to the output voltage of the charge pump. However, a charge pump has many switching devices which make the system more complicated. A switched-capacitor (SC) inverter outputs multilevel voltage with switched capacitors [7], [8]. An SC inverter is similar to a charge pump in the topology. The SC inverter can output larger voltage than the input voltage in similar way to the charge pump. However, the SC inverter also has many switching devices which make the system more complicated. On the other hand, a Marx inverter, which is reduced the number of the switching devices compared to the SC inverter, was proposed [9]. It is considered that the Marx inverter is one of the SC inverters because of its operation principle. In this paper, a SC inverter whose structure is simpler than the conventional SC inverter is proposed. It consists of a Marx inverter structure and an H-bridge. The proposed inverter can output larger voltage than the input voltage by switched capacitors in series and in parallel. The proposed inverter does not have any inductors which make the system large. The output harmonics of the proposed inverter are reduced by the multilevel output. In section II, the circuit topology is introduced and the driving method is explained. In section III, simulation results with MATLAB/SIMULINK are explained. II. CIRCUIT TOPOLOGY IJPRES 7

2 Fig. 1 shows a circuit topology of the proposed inverter, where S ak, S bk, S ck (k = 1, 2...2n 2) are the switching devices which switch the capacitors C k (k = 1, 2,..., 2n 1) in series and in parallel. Switches S 1 S 4 are in the inverter bridge. A voltage source V in is the input voltage source. A low-pass filter is composed of an inductor L and a capacitor C. Fig. 3. Modulation method of the proposed inverter S ak, S bk, S ck (where k=1,2,3,4) are switched with respective gate source voltages alternately to make the capacitors in parallel and series connection to form the 11 level output by using Table I. TABLE I LIST OF THE ON-STATE SWITCHES ON EACH STATE Relationship between and e k e s On state switches Ideal bus voltage Fig.1. Circuit topology of the switched-capacitor inverter using series/parallel conversion. There are many modulation methods to drive a multilevel inverter: the space vector modulation [3], [12-14] the multicarrier pulse width modulation (PWM) [3], [15], the hybrid modulation, the selective harmonic elimination and the nearest level control. In this paper, the multicarrier PWM method is applied to the proposed inverter. es>e1 S1,s4,sa1,sa2,sa3,sa4 5Vin e1 es>e2 S1,s4,sa1,sa2,sb3,sc3,sb4,sc4 4Vin e2 es>e3 S1,s4,sa1,sa2,sb3,sc3,sb4,sc4 3Vin e3 es>e4 S1,s4,sa1,sb2,sc2,sb3,sc3,sb4,sc4 2Vin e4 es>e5 S1,s4,sb1,sc1,sb2,sc2,sb3,sc3,sb4,sc4 Vin e5 es>e6 S2,s4,sb1,sc1,sb2,sc2,sb3,sc3,sb4,sc4 0 e6 es>e7 S2,s3,sb1,sc1,sb2,sc2,sb3,sc3,sb4,sc4 -Vin e7 es>e8 S2,s3,sb1,sc1,sb2,sc2,sb3,sc3,sa4-2Vin e8 es>e9 S2,s3,sb1,sc1,sb2,sc2,sa3,sa4-3Vin e9 es>e10 S2,s3,sb1,sc1,sa2,sa3,sa4-4Vin e10 es S2,s3,sa1,sa2,sa3,sa4-5Vin Fig. 2. proposed inverter (n = 4) Fig. 2 shows the current flow in the proposed inverter (n = 4) and Fig. 3 shows the modulation method of the proposed inverter (n = 4). The switches S1 and S2 are driven by the gate-source voltage. While the switches S1 and S2 are switched alternately. Table I shows the list of the on-state switches when the proposed inverter (n =4) is driven by the modulation method shown in Fig. 3. The ideal bus voltage v bus in Table I means the bus voltage on each state when V C1 = V C3 = V C4 = V C5 = V in is assumed. As the conventional SC inverter, the proposed inverter has a full bridge which is connected to the high voltage. IJPRES 8

Therefore, the device stress of the switches S 1 S 4 in the full bridge is higher than the other switches as the conventional SC inverter. The proposed inverter (n = 4) outputs a 11-level voltage.

3 Therefore, the device stress of the switches S 1 S 4 in the full bridge is higher than the other switches as the conventional SC inverter. The proposed inverter (n = 4) outputs a 11-level voltage. Because the driving waveform v GSa1, v GSa2, v GSa3 and v GSa4 change alternately, capacitors C1, C3, C4 and C5 are equally discharged. Assuming that the number of the capacitors is 2n 1, the proposed inverter can outputs 4n 1 levels voltage waveform. The modulation index M is defined as the following equation because the amplitude of the output voltage waveform is inversely proportional to the double amplitude of the carrier waveform M = A /2A (1) In (3), A ref is the amplitude of the reference waveform and A c is the amplitude of the carrier waveform. The proposed inverter requires 16 switching devices for the 11-level. On the other hand, the conventional SC inverter requires 20 switching devices for the 7-level, and 28 switching devices for the 11-level. The conventional cascaded H-bridge (CHB) inverter requires 12 switching devices for the 7-level, and 20 switching devices for the 11-level, when all the dc voltage sources take the same voltage. Therefore, the proposed inverter has less number of switching devices than the conventional multilevel inverters. III. SIMULATION RESULTS Simulation was performed under the two conditions. One was for a low power inverter under the same condition with the circuit experiments. The other one was for a high power inverter. The low power inverter simulation was performed with MATLAB/SIMULINK ver. R2009a under the following conditions. The MOSFET models whose internal resistance Ron = 0.54 [Ω] and the snubber resistance Rs = 105 [Ω] were used as the switching devices. The input voltage Vin = 8.00 [V], the output resistance R = 50.0 [Ω], a filter capacitance C, and a filter inductance L were C = [μf] and L = 1.13 [mh], the modulation index M = 3.00, the switching frequency f = 40.0 [khz], and the reference waveform frequency fref = 1.00 [khz]. From (8), the capacitance C1 and C3 are calculated to C1 = C3 = 143 [μf], which have ESRs rc1 = rc3 = 800 [mω]. Fig. 5 shows the simulated voltage waveforms of the proposed inverter (n = 2) designed for low power at 5.76 [W]. The voltages of the capacitors VCk are changed between 6.73 [V] and 7.51 [V]. Therefore, the voltage of the step in the bus voltage waveform decreases to about 90% as shown at t = to 8.40 [ms] in Fig. 5(a). It is caused by the 10% voltage drop at the capacitors Ck. This is accorded with the theoretical calculation. The theoretical amplitude of the output waveform is MVin = 24 [V]. (2) From Fig. 5(b) and (26), it is confirmed that the amplitude of the output waveform in the simulation is smaller than the theoretical amplitude. It is also caused by the voltage reduction of the capacitors Ck. The high power inverter simulation was performed under the following conditions. The IGBT/Diode models whose internal resistance Ron = 65.0 [mω] and the snubber resistance Rs = 105 [Ω] were used as the switching devices. Vin = 100 [V], R = 10.0 [Ω], C = 2.25 [μf], L = 225 [μh], M = 3.00, f = 40.0 [khz] and fref = 1.00 [khz]. From (8), C1 and C3 are calculated to C1 = C3 = 712 [μf]. These capacitors ESRs rc1 and rc3 are 100 [mω]. Fig. 6 shows the simulated voltage waveforms of the proposed inverter (n = 2) designed for high power at 4.50 [kw]. The voltages of the capacitors VCk are changed between 87.0 [V] and 97.2 [V]. Therefore, the voltage of the step in the bus voltage waveform decreases to about 90% as shown at t = to 8.40 [ms] in Fig. 6(a), which is the same to the simulation result in low power models. The theoretical amplitude of the output waveform is MVin = 300 [V]. (3) Fig. 5 Simulated voltage waveforms of the proposed inverter (n = 4) designed for low power at 5.76 [W], switching frequency f = 40 [khz] and reference waveform frequency fref = 1 [khz]. (a) Bus voltage waveform vbus and (b) the output voltage waveform vout. IJPRES 9

From Fig. 6(b) and (27), it is confirmed that the amplitude of the output waveform in the simulation is smaller than the theoretical amplitude.

Simulated current waveforms of the capacitor ic1 in the proposed inverter (n = 4).(a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.50 [kw]. Fig 6.

(a) Bus voltage waveform vbus and (b) the output voltage waveform vout. Fig. 7 shows the simulated current waveforms of the capacitor C1 in the proposed inverter (n = 2).

5 [A], respectively. On the other hand, the absolute values of the peak currents in the simulation results are 0.605 [A] and 52.3 [A], respectively.

4 From Fig. 6(b) and (27), it is confirmed that the amplitude of the output waveform in the simulation is smaller than the theoretical amplitude. As the result of the simulation in low power models, the voltage reduction of the capacitors Ck appears on the bus voltage waveform. (b) Fig 7. Simulated current waveforms of the capacitor ic1 in the proposed inverter (n = 4).(a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.50 [kw]. Fig 6. Simulated voltage waveforms of the proposed inverter (n = 4) designed for high power at 4.50 [kw], switching frequency f = 40 [khz] and reference waveform frequency fref = 1 [khz]. (a) Bus voltage waveform vbus and (b) the output voltage waveform vout. Fig. 7 shows the simulated current waveforms of the capacitor C1 in the proposed inverter (n = 2). From the (9) and the voltage of the capacitor C1, the absolute value of the peak current of the capacitor C1 under the conditions of the low power and the high power simulations are [A] and 56.5 [A], respectively. On the other hand, the absolute values of the peak currents in the simulation results are [A] and 52.3 [A], respectively. The differences between the theoretical currents and the simulation results are caused by the nonlinear characteristic of the switching device models in MATLAB/SIMULINK. Fig. 8 shows the simulated spectra of the bus voltage waveform, which are normalized with the fundamental component. In both spectra of the bus voltage waveforms of the low power and the high power proposed inverters, the magnitude at 40 [khz] is larger than the other frequency components. This is caused by the switching frequency f = 40 [khz]. The calculated total harmonic distortions (THDs) of the 5.76 [W] inverter and of the 4.50 [kw] inverter are 18.9% and 18.7%. On the other hand, the THD of the conventional voltage source single phase full bridge inverter is 64.3% under the same condition of the low power simulation. The THDs of the proposed inverters are reduced compared to the conventional single phase full bridge inverter. Fig. 9 shows the simulated output voltage waveforms with an inductive load under the same condition of the low power inverter simulation. The load inductance LR = 4.89 [mh] and the load resistance R = 40.0 [Ω] are connected in series as the inductive load. The power factor of the inductive load cos φ = From Fig. 9, it is confirmed that the proposed inverter can be applied to the inductive load. (a) (a) IJPRES 10

electric, hybrid electric, and fuel cell vehicular power systems, IEEE Trans. Power Electron., vol. 21, no. 3, pp. 567 577, May 2006. [3] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R.

Simulated spectra of the bus voltage waveform of the proposed inverters (n = 2) normalized with the fundamental component. (a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.

5 electric, hybrid electric, and fuel cell vehicular power systems, IEEE Trans. Power Electron., vol. 21, no. 3, pp , May [3] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, The age of multilevel converters arrives, IEEE Ind. Electron. Mag., vol. 2, no. 2, pp , Jun (b) Fig. 8. Simulated spectra of the bus voltage waveform of the proposed inverters (n = 2) normalized with the fundamental component. (a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.50 [kw]. [4] Y. Hinago and H. Koizumi, A single phase multilevel inverter using switched series/parallel DC voltage sources, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp , Aug [5] S. Chandrasekaran and L. U. Gokdere, Integrated magnetics for interleaved DC DC boost converter for fuel cell powered vehicles, in Proc. IEEE Power Electron. Spec. Conf., Jun. 2004, pp [6] Y. Hinago and H. Koizumi, A switchedcapacitor inverter using series/ parallel conversion, in Proc. IEEE Int. Symp. Circuits Syst., May/Jun. 2010, pp Fig 9. Simulated bus voltage waveforms vbus and the voltage waveforms of the load resistance vr of the proposed inverter (n = 4) designed for low power at 5.76 [W] with an inductive load. IV. CONCLUSION In this paper, a novel switched capacitor inverter was proposed. The circuit topology was introduced. The modulation method and the calculation of the capacitances were shown. The circuit operation of the proposed inverter was confirmed by the simulation results and the experimental results. The proposed inverter structure becomes simpler than the conventional switched capacitor inverters. The proposed inverter can output larger voltage than the input voltage by switched capacitors in series and in parallel. THD of the output waveform of the proposed inverter is reduced compared to the conventional single phase inverter as the same with the conventional multilevel inverter. V. REFERENCES [1] H. Liu, L. M. Tolbert, S. Khomfoi, B. Ozpineci, and Z. Du, Hybrid cascaded multilevel inverter with PWM control method, in Proc. IEEE Power Electron. Spec. Conf., Jun. 2008, pp [2] A. Emadi, S. S. Williamson, and A. Khaligh, Power electronics intensive solutions for advanced [7] J. A. Starzyk, Y. Jan, and F. Qiu, A dc dc charge pump design based on voltage doublers, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp , Mar [8] M. R. Hoque, T. Ahmad, T. R. McNutt, H. A. Mantooth, and M. M. Mojarradi, A technique to increase the efficiency of high-voltage charge pumps, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 5, pp , May [9] O. C.Mak and A. Ioinovici, Switched-capacitor inverter with high power density and enhanced regulation capability, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 4, pp , Apr [10] B. Axelrod, Y. Berkovich, and A. Ioinovici, A cascade boost switched capacitor- converter-two level inverter with an optimized multilevel output waveform, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12, pp , Dec [11] J. I. Rodriguez and S. B. Leeb, A multilevel inverter topology for inductively coupled power transfer, IEEE Trans. Power Electron., vol. 21, no. 6, pp , Nov [12] X. Kou, K. A. Corzine, and Y. L. Familiant, A unique fault-tolerant design for flying capacitor IJPRES 11

multilevel inverter, IEEE Trans. Power Electron., vol. 19, no. 4, pp. 979 987, Jul. 2004. [13] S. Lu, K. A. Corzine, and M.

Vazquez, A. J. Watson, L. G. Franquelo, P. W. Wheeler, and J. M. Carrasco, Feed-forward space vector modulation for singlephase multilevel cascaded converters with any dc voltage ratio, IEEE Trans.

6 multilevel inverter, IEEE Trans. Power Electron., vol. 19, no. 4, pp , Jul [13] S. Lu, K. A. Corzine, and M. Ferdowsi, A unique ultra capacitor direct integration scheme in multilevel motor drives for large vehicle propulsion, IEEE Trans. Veh. Technol., vol. 56, no. 4, pp , Jul [14] J. I. Leon, S. Vazquez, A. J. Watson, L. G. Franquelo, P. W. Wheeler, and J. M. Carrasco, Feed-forward space vector modulation for singlephase multilevel cascaded converters with any dc voltage ratio, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp , Feb [15] B. P. McGrath and D. G. Holmes, Multicarrier PWM strategies for multilevel inverters, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp , Aug P. yaswanthaantha reddy received B.Tech degree in mekapati rajmohan reddy science and technology degree in Electrical and Electronics Engineering from Jawaharlal Nehru Technological University, Hyderabad, India in 2010, and Currentl he is presuming M.Tech (power electronics) in Department of Electrical and Electronics Engineering, PBR vishvodaya Institute of Engineering and Technology, kavali, India. CH.Srinivasulureddy recieved his B.Tech in dept.of eee in 2002 from PBRVITS Kavali(Nellore Dist) A.P. & M.tech (Power systems)from JNTU,Hyderabad.He started his career as assistant professor in the dept. Of EEE in PBRVITS, Kavali. Presently he is working as Head of the dept. Of EEE and guiding the students in developing their ideas practically in the field of powersystems. IJPRES 12

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