INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)
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1 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET) Proceedings of the 2 nd International Conference on Current Trends in Engineering and Management ICCTEM ISSN (Print) ISSN (Online) Volume 5, Issue 8, August (2014), pp IAEME: Journal Impact Factor (2014): (Calculated by GISI) IJEET I A E M E PWM CONTROL STRATEGIES FOR MULTILEVEL INVERTERS BASED ON CARRIER REDISTRIBUTION TECHNIQUE S. Nagaraja Rao 1, D.V. Ashok Kumar 2, Ch.Sai Babu 3 1 Research Scholar, JNTUK,Kakinada (A.P), India 2 Professor, Dept.of EEE, SDIT, Nandyal (A.P), India 3 Professor, Dept.of EEE, JNTUK, Kakinada (A.P), India ABSTRACT This paper proposes three Pulse width modulated (PWM) methods based on Carrier Redistribution Techniques that utilize the (CFD) control freedom degree of vertical offsets among carriers. They are named as Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) and Phase Disposition (PD). Ingeneral Pulse width modulated (PWM) techniques of a voltage source inverter need a reference signal and carrier signal to generate the required modulating signals for the desired output. Modifications in Modulating techniques can be considered in two ways, namely Modified reference and Modified carrier. The existing multilevel carrier-based pulse width modulation strategies have no special provisions to offer quality output, besides lower order harmonics are introduced in the spectrum, especially at low switching frequencies. This paper proposes a novel multilevel PWM strategy to corner the advantages of low frequency switching and reduced total harmonic distortion (THD) based on Carrier Redistribution Technique. This paper also presents the most relevant control and modulation methods by a new reference/carrier based PWM scheme for three phase Diode Clamped Multilevel Inverter and comparing the performance of the proposed scheme with that of the existing control schemes. Finally, the simulation results are included to verify the effectiveness of the proposed multilevel inverter configuration using various PWM Techniques and validate the proposed theory. Keywords: Diode Clamped MLI, Pulse width modulation, APOD, POD, PD, Total Harmonic Distortion. I. INTRODUCTION The voltage source inverters produce an output voltage or current with levels either 0 or ±Vdc. They are known as the two-level inverter. To produce a quality output voltage or a current 119
2 wave form with less amount of ripple content, they require high switching frequency. In high- power and high-voltage applications these two level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of device ratings. These limitations can be overcome using multilevel inverters. The multilevel inverters have drawn tremendous interest in power industry. It may be easier to produce a high-power, high-voltage inverter with multi level structure because of the way in which the voltage stresses are controlled in the structure. The unique structure of multilevel voltage source inverters allows them to reach high voltages with low harmonics without use of transformers or series connected synchronized-switching devices. As the number of voltage levels increases, the harmonic content of the output voltage wave form decreases significantly. In general multilevel inverter can be viewed as voltage synthesizers, in which the high output voltage is synthesized from many discrete smaller voltage levels. The main advantages of this approach are summarized as follows: They can generate output voltages with extremely low distortion and lower (dv/dt). They can operate with a lower switching frequency. Their efficiency is high (>98%) because of the minimum switching frequency. They are suitable for medium to high power applications. The selection of the best multilevel topology for each application is often not clear and is subject to various engineering tradeoffs. Multilevel inversion is a power conversion strategy in which the output voltage is obtained in steps thus bringing the output closer to a sine wave and reduces the total harmonic distortion (THD). In general MLI s are three types they are named as diode clamped, flying capacitor and cascaded inverters. In this paper diode clamped MLI is considered based on their own advantages [1]. This paper presents a PWM control strategies for a seven level inverter Diode Clamped inverter based on carrier redistribution technique. Simulation results are included to verify the operating principle of the proposed multilevel inverters. II. SYSTEM CONFIGURATION Fig.1: Multilevel concept for (a) two level (b) three level and (c) n- level Multilevel inverter structures have been developed to overcome shortcomings in solid-state switching device ratings so they can be applied to higher voltage systems. The multilevel voltage source inverters [2] unique structure allows them to reach high voltages with low harmonics without the use of transformers. The general function of the multilevel inverter is to synthesize a desired ac voltage from several levels of dc voltages as shown in Fig.1. Table.1 compares the power component requirement per phase leg among the three multilevel voltage source inverters mentioned above. The table shows that the number of main switches and main diodes needed by the inverters to achieve the number of voltage levels. 120
3 Table.1: Component requirements per phase of m-level multilevel inverters Devices Diode clamped Flying Capacitor Cascaded H- MLI MLI Bridge MLI Main switching Devices 2(m-1) 2(m-1) 2(m-1) Main diodes 2(m-1) 0 2(m-1) Clamping diodes (m-1)* (m-2) (m-1)*(m-2) 0 Dc Balancing Capacitors m-1 m-1 (m-1)/2 Balancing Capacitors 0 2(m-1) 0 III. 7-LEVEL DIODE CLAMPED INVERTER Fig. 2: Configuration of Three-phase Diode Clamped Seven Level Inverter (DC7LI) Fig. 2 shows a seven-level diode-clamped inverter in which the dc bus consists of six capacitors, C1, C2, C3, C 4, C 5 and C6. For dc-bus voltage V dc, the voltage across each capacitor is V dc and each device voltage stress will be limited to one capacitor voltage level through clamping diodes. To explain how the staircase voltage is synthesized, the neutral point n is considered as the output phase voltage reference point. There are seven switch combinations to synthesize seven level output as shown in Table2. Table.2: Switching sequence for single phase 7 level diode clamped inverter Output voltage S1 S2 S3 S4 S5 S6 S1 1 S2 1 S3 1 S4 1 S5 1 S Vdc Vdc Vdc Vdc vdc vdc
4 IV. PWM CONTROL TECHNIQUES FOR MLI s Pulse Width Modulation (PWM) techniques for two level inverters have been studied extensively during the past decades. Many different PWM methods have been developed to achieve the following aims; wide linear modulation range, reduced switching loss, lesser total harmonic distortion in the spectrum of switching waveform, easy implementation, less memory space and computation time on implementing in digital processors for the proposed work. A number of modulation strategies are used in multilevel power conversion applications. They can generally be classified into modulating signals and carrier redistribution signal. 4.1 Modulating Signal Modulating signals can be classified into Sinusoidal PWM (SPWM), Third Harmonic injection PWM (THPWM) and Modified Space Vector PWM (MSVPWM). These modulation techniques are extensively studied and compared for the performance parameters with seven level inverters Sinusoidal PWM Fig. 3: Sinusoidal modulating signal control technique Sinusoidal PWM is the most widely accepted PWM technique, where a triangular wave is compared with a sinusoidal reference known as the modulating signal, shown in Fig Third Harmonic injection PWM A method to improve the gain of the pulse width modulator in a multilevel inverter is to inject a third harmonic. This technique is derived from conventional sinusoidal PWM with the addition of a 17% third harmonic component to the sine reference waveform as shown in Fig.4. Fig. 4: Third Harmonic Injection modulating signal control technique Modified Space Vector PWM In the SPWM scheme for two-level inverters, each reference phase voltage is compared with the triangular carrier and the individual pole voltages are generated, independent of each other [5, 6]. To obtain the maximum possible peak amplitude of the fundamental phase voltage, in linear 122
5 modulation, a common mode voltage, Voffset1, is added to the reference phase voltages [9, 1], where the magnitude of Voffset1 is given by ( Vmax + V V min) offset 1 = Equation - (1) 2 In (1), Vmax is the maximum magnitude of the three sampled reference phase voltages, while Vmin is the minimum magnitude of the three sampled reference phase voltages, in a sampling interval. The addition of the common mode voltage, Voffset1, results in the active inverter switching vectors being centered in a sampling interval, making the SPWM technique equivalent to the modified reference PWM technique [9].The modulating signal of modified space vector is shown in fig. 5. Fig. 5: Modified Space vector modulating signal control technique 4.2 Multicarrier PWM Techniques The implementation of the various carrier PWM techniques is possible for multi-level inverters. This paper uses multi-level triangular waves generation as derived in [5]. It can be a useful solution for pulse generation for this topology. This technique in [13] is called carrier redistribution (CR) technique. This technique is derived from the triangular carrier and has individually the lowest switching frequency among the multi-level PWM methods [14] Alterative Phase Opposition Disposition (APOD) This technique requires each of the (m 1) carrier waveforms, for an m-level phase waveform, to be phase displaced from each other by alternately as shown in Figures 6,7, and 8 for various modulating signals. The most significant harmonics are centered as sidebands around the carrier frequency fc and therefore no harmonics occur at fc. Fig.6: Sinusoidal reference with triangular carriers for a 3-phase seven-level PWM scheme using APOD 123
6 Fig.7: Third Harmonic Injection reference with triangular carriers for a 3-phase seven-level PWM scheme using APOD Fig.8: Modified Space vector reference with triangular carriers for a 3-phase seven-level PWM scheme using APOD Phase Opposition Disposition (POD) The carrier waveforms are all in phase above and below the zero reference value however, there is phase shift between the ones above and below zero respectively as shown in Figures 9, 10 and 11 for various modulating signals. The significant harmonics, once again, are located around the carrier frequency fc for both the phase and line voltage waveforms. Fig.9: Sinusoidal reference with triangular carriers for a 3-phase seven-level PWM scheme using POD Fig.10: Third Harmonic Injection reference with triangular carriers for a 3-phase seven-level PWM scheme using POD 124
7 Fig.11: Modified Space vector reference with triangular carriers for a 3-phase seven-level PWM scheme using POD Phase Disposition (PD) In this technique all the carrier waveforms are in same phase. Fig.11, 12 and 13 demonstrates the various modulating signals for a seven-level inverter. Fig.12: Sinusoidal reference with triangular carriers for a 3-phase seven-level PWM scheme using PD Fig.13: Third Harmonic Injection reference with triangular carriers for a 3-phase seven-level PWM scheme using PD Fig.14: Modified Space vector reference with triangular carriers for a 3-phase seven-level PWM scheme using PD 125
8 V. SIMULATION RESULTS A detailed circuit simulation was conducted to verify the operating principles of the three phase seven level Diode clamped using SPWM, THPWM and Modified SVPWM strategies based on Carrier Redistribution Techniques. Seven Level Diode Clamped MLI for 3 Ф 5.1 Sinusoidal PWM Fig.15: Line voltage of 3 Ф seven level DC MLI using SPWM Fig.16: FFT analysis of line voltage of 3 Ф seven level DC MLI using APOD Fig.17: FFT analysis of line voltage of 3 Ф seven level DC MLI using POD Fig.18: FFT analysis of line voltage of 3 Ф seven level DC MLI using PD 126
9 5.2 Third Harmonic injection PWM Fig.19: Line voltage of 3 Ф seven level DC MLI using THPWM Fig.20: FFT analysis of line voltage of 3 Ф seven level DC MLI using APOD Fig.21: FFT analysis of line voltage of 3 Ф seven level DC MLI using POD Fig.22: FFT analysis of line voltage of 3 Ф seven level DC MLI using PD 127
10 5.3 Modified Space Vector PWM Fig.23: Line voltage of 3 Ф seven level DC MLI using Modified SVPWM Fig.24: FFT analysis of line voltage of 3 Ф seven level DC MLI using APOD Fig.25: FFT analysis of line voltage of 3 Ф seven level DC MLI using POD Fig.26: FFT analysis of line voltage of 3 Ф seven level DC MLI using PD 128
11 The simulated AC output voltage of the seven level Diode Clamped inverter using SPWM, THPWM and Modified SVPWM based on Carrier Redistribution Techniques for 3 Ф and its corresponding FFT analysis are shown in above figures. These waveforms confirm the principle of operation of 7-level Diode Clamped inverter using SPWM, THPWM and modified SVPWM with resistive load. VI. COMPARISON OF RESULTS Input Voltage = 400 Volts Switching Frequency = 10 KHz Modulation Index = Table.3: % THD for various PWM Techniques for Seven Level Diode Clamped Inverter PWM Modified SPWM THPWM Technique SVPWM APOD POD PD Table.4: Fundamental Output Voltage (V rms ) for various PWM Techniques for Seven Level Diode Clamped Inverter PWM Modified SPWM THPWM Technique SVPWM APOD POD PD Fig. 27: % Graphical representation of % THD for various PWM Techniques for Seven Level Diode Clamped Inverter The Diode Clamped Three Phase Seven Level Inverter is simulated for various PWM strategies based on carrier redistribution technique. The simulation results with harmonic spectrum are presented and the corresponding results are shown in table 3 and table 4. In addition to this graphical representation is also shown in fig. 26. In this presentation it is concluded that modified SVPWM scheme with PD carrier redistribution technique has given good harmonic spectrum with fundamental THD when compared with SPWM and THPWM techniques. 129
12 VII. CONCLUSION The diode clamped 3-phase seven level inverter is simulated for sinusoidal PWM, Third Harmonic PWM technique and modified space vector PWM technique with APOD, POD and PD PWM strategies. The simulation results with harmonic spectrum are presented, and in this paper it is concluded that modified reference SVPWM using PD technique has given good harmonic spectrum with fundamental (335.8) and THD (10.78%) when compared with other techniques. One application area in the low-power range ( 100 kw) for Diode clamped inverter is in permanent-magnet (PM) motor drives employing a PM motor of very low inductance. The DCMLI can utilize the fast-switching low-cost low voltage MOSFETs and the IGBT s in the single-phase bridges to dramatically reduce current and torque ripples and to improve motor efficiency by reducing the associated copper and iron losses resulting from the current ripple. These configurations may also be applied in distributed power generation involving fuel cells and photovoltaic cells. VIII. REFERENCES [1] Gui- jia su, senior member, IEEE, Multilevel DC-Link Inverter, IEEE Trans. on Indapplications, vol.41, issue 4, pp ,may/june [2]. Zhong Du, Member,IEEE, Leon M.Tolbert, senior member Fundamental Frequency Switching Strategies of a Seven level Hybride Cascaded H-Bridge Multilevel Inverter, IEEE Transactions on, vol.24, no.1, Jan 2009 [3]. J. Rodr ıguez, J. Lai, and F. Peng, Multilevel inverters:asurvey of topologies, controls and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp , Aug [4]. W. Yao, H. Hu, and Z. Lu, Comparisons of space-vector modulation and carrier-based modulation of multilevel inverter, IEEE Trans. Power Electron., vol. 23, no. 1, pp , Jan [5]. J. N. Chiasson, L. M. Tolbert, K. J.McKenzie, and Z.Du, A new approach to solving the harmonic elimination equations for a multilevel converter, in Proc. IEEE Ind. Appl. Soc. Annu. Meeting, Salt Lake City, UT, Oct , 2003, pp [6]. Z. Du, L. M. Tolbert, and J. N. Chiasson, Active harmonic elimination for multilevel converters, IEEE Trans. Power Electron., vol. 21, no. 2, pp , Mar [7]. V. Blasko, A novel method for selective harmonic elimination in power electronic equipment, IEEE Trans. Power Electron., vol. 22, no. 1, pp , Jan [8]. J. R. Wells, X. Geng, P. L. Chapman, P. T. Krein, and B. M. Nee, Modulation-based harmonic elimination, IEEE Trans. Power Electron., vol. 22, no. 1, pp , Jan [9]. S.Mariethoz, A.Rufer, Resolution and efficiency improvements for three-phase cascaded multilevel inverters, IEEE transaction,2004. [10]. K. Thorborg and A. Nystorm, Staircase PWM: an uncomplicated and efficient modulation technique for ac motor drives, IEEE Transactions on Power Electronics, Vol. PE3, No.4, 1988, pp [11]. J. C. Salmon, S. Olsen, and N. Durdle, A three-phase PWM strategy using a stepped 12 reference waveform, IEEE Transactions on Industry Applications, Vol. IA27, No. 5, 1991, pp [12]. M. H. Ohsato, G. Kimura, and M. Shioya, Five-stepped PWM inverter used in photovoltaic systems, IEEE Transactions on Industrial Electronics, Vol. 38, October, 1991, pp [13]. J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multi-level inverter: a survey of topologies, controls, and applications, IEEE Trans.Ind. Electron, vol. 49, no. 4, pp , Aug
13 [14]. Gerardo Ceglia, Víctor Guzmán, Member,IEEE, Carlos Sánchez, Fernando Ibáñez, Julio Walter, and María I. Giménez, Member,IEEE, A New Simplified Multilevel Inverter Topology for DC AC Conversion, IEEE Transactions on Power Electronics, vol. 21, no. 5, Sep AUTHOR S DETAIL S.Nagaraja Rao was born in kadapa, India. He received the B.Tech (Electrical and Electronics Engineering) degree from the Jawaharlal Nehru Technological University, Hyderabad in 2006; M.Tech (Power Electronics) from the same university in He is currently pursuing his Ph.D under JNTUK, Kakinada. He has published several National and International Journals and Conferences. His area of interest power electronics and Electric Drives. Dr. D. V. Ashok Kumar, was born in Nandyal, India in He received the B.E (Electrical and Electronics Engineering) degree from Gulbarga University and the M.Tech (Electrical Power Systems) from J.N.T.U.C.E, Anantapur and Ph.D in Solar Energy from same University. Currently he is working as Pricipal in Syamaldevi Institute of Technology for women, Nandyal, He has published/presented technical research papers in national and international Journals/conferences. His field of interest includes Electrical Machines, Power electronics, Power systems and Solar Energy. Ch. Sai Babu received the B.E from Andhra University (Electrical & Electronics Engineering), M.Tech in Electrical Machines and Industrial Drives from REC, Warangal and Ph.D in Reliability Studies of HVDC Converters from JNTU, Hyderabad. Currently he is working as a Professor in Dept. of EEE in JNTUK, Kakinada. He has published several National and International Journals and Conferences. His area of interest is Power Electronics and Drives, Power System Reliability, HVDC Converter Reliability, Optimization of Electrical Systems and Real Time Energy Management. 131
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