A 5-Level Three-Phase Cascaded Hybrid Multilevel Inverter

Transcription

1 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December A 5-Leel hree-phae Cacaded Hybrid Multileel Inerter P. hongprari Abtract hi paper preent a 5-leel three-phae cacaded hybrid multileel inerter that conit of a tandard 3-leg (one leg for each phae) and H-bridge in erie with each inerter leg with eparate DC oltage ource, 4 and 48. he control ignal for thi hybrid multileel inerter are implemented by a FPGA controller uing ignal modulated technique and digital technique. A 5-leel three-phae cacaded hybrid multileel inerter model baed on PSCAD/EMDC i preented in thi paper. he propoed hybrid multileel inerter i decribed in detail that it i erified experimentally in three type of load; 8W fluorecent lamp-ballat, RL, and HP 3-phae induction motor; without filtering. Reult of the experiment; the output waeform of line-line and phae oltage ha 5 leel that percent of HD i between 5.6% and 8.3%, the output waeform of phae current i cloe to inuoidal that percent of HD i between.7% and 4.%. deirable, but increaing the number of leel need more hardware, alo the control will be more complicated. It i a tradeoff between price, weight, complexity and a ery good output oltage with lower HD. Fig. how ingle phae topology of the diode Clamped, flying capacitor, a cacaded H-bridge, and cacade hybrid multileel inerter that they hae the number of witche, diode, and capacitor a hown in table I (a 5- leel multileel inerter). C C C 3 S S S 3 S 4 o C C C 3 C 5 C 6 C 7 C 8 C 9 C S S S 3 S 4 o Index erm Hybrid multileel inerter, PSCAD/EMDC, FPGA controller, h-bridge. C 4 (a) Diode Clamped multileel inerter S 7 S 8 S 7 C 4 S 8 (b) Flying capacitor multileel inerter I. INRODUCION A multileel inerter i a power electronic conerter built to yntheize a deired AC oltage from eeral leel of DC oltage which the DC leel were conidered to be identical in that all of them were batterie, olar cell, capacitor, etc. he multileel inerter ha gained much attention in recent year due to it adantage in lower witching lo better electromagnetic compatibility, higher oltage capability, and lower harmonic []-[3]. Seeral topologie for multileel inerter hae been propoed; the mot popular being the diode-clamped [4], [5], flying capacitor [6], and cacade H- bridge [7] tructure. Beide the three baic multileel inerter topologie; other multileel conerter topologie hae been propoed, mot of thee are hybrid circuit that are combination of two of the baic multileel topologie. he cheme of multileel inerter are claified in to two type the multicarrier ub-harmonic pule width modulation (MC- SH ) and the multicarrier witching frequency optimal pule width modulation (MC-SFO ) [8], [9]. he MC-SH cacaded multileel inerter trategy reduced total harmonic ditortion and the MC-SFO cacade multileel inerter trategy enhance the fundamental output oltage []. he HD will be decreaed by increaing the number of leel. It i obiou that an output oltage with low HD i Manucript receied Augut 4, ; reied September 3,.hi work wa upported by the Department of Electrical Engineering, Faculty of Engineering at Si Racha, Kaetart Unierity Si Racha Campu, and hailand. P. hongprari i with the Department of Electrical Engineering, Faculty of Engineering at Si Racha, Kaetart Unierity Si Racha Campu, Chonburi, hailand ( fengprt@ rc.ku.ac.th). S S S3 S4 S5 S6 S7 S8 (c) Cacaded H-bridge multileel inerter o S S S3 S4 C C o (d) Cacaded Hybrid multileel inerter Fig.. One phae of a 5-leel multileel inerter. ABLE I: COMPONENS OF ONE PHASE OF A-5 LEEL MULILEEL INERER ype of multileel inerter Number of witche Number of diode Number of capacitor Diode Clamped 8 4 Flying capacitor 8 - Cacaded H-bridge Cacade hybrid 6 - In thi paper, the propoed a 5-leel three-phae cacaded hybrid multileel inerter include a tandard 3-leg inerter (one leg for each phae) and H-bridge in erie with each inerter leg a hown in Fig.. o deelop the model of a 5-leel cacaded hybrid multileel inerter, a imulation i done baed on PSCAD/EMDC. All ignal for controlling the hybrid multileel inerter are created by a FPGA controller uing ignal modulated technique and digital technique. he prototype i teted with 3 type of load; a 8W fluorecent lamp-ballat, RL (R i 65 Ω, L i.5 H ), and a HP 3-phae induction motor (no load); without filtering. 789

2 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December II. OPERAION PRINCIPLE OF HE HYBRID MULILEEL INERER S a S a3 i a LOAD c S a S a4 b S a S a S a3 S a4 S b S b S b3 S b4 S c S c S c3 S c4 S S Fig. 3. Single phae topology of the hybrid multileel inerter. S S S 3 S 4 Fig.. opology of a 5-leel three-phae cacaded hybrid multileel inerter. Fig. how the topology of the propoed a 5-leel 3-phae cacaded hybrid multileel inerter. Single phae topology of the hybrid multileel inerter i hown in Fig. 3; the bottom i one leg of a tandard 3-leg inerter with a power ource ( ), the top i a hybrid in erie with each tandard inerter leg that the H-bridge inerter can ue a eparate power ource ( / ). Conidering the output oltage of thi leg i either + / when S cloed or / when S cloed. hi leg i connected in erie with a full H-bridge inerter, then the output oltage of the H-bridge inerter i either + / when S, a Sa4 cloed, when S, a Sa3 or S, a Sa4 cloed, or / when S, a Sa3 cloed. An example output waeform that thi topology can achiee a hown in the Fig. 4, when the output oltage = + i required to be zero, one can either et / = + and = / or = /, and = + /. In [], eeral different two-leel multileel carrier-baed technique hae been extend for controlling the actie deice in a multileel conerter, the mot popular and eaiet technique to implement ue eeral triangle carrier ignal and one reference, or modulation, ignal per phae. In order to achiee better link utilization at high modulation indice, the inuoidal reference ignal can be injected by a third harmonic with a magnitude equal to 5% of fundamental. Fig. 5 how MC-SH of a 5-leel inerter, m- carrier with the ame frequency fc and the ame amplitude Ac are dipoe uch that the band they occupy are contiguou, he reference waeform ha peak-to-peak amplitude A m, a frequency f m, and it zero centered in the middle of the carrier et, he reference i continuouly compared with each of the carrier ignal. If the reference i greater than a carrier ignal, then the actie deice correponding to that carrier i witched on, and if the reference i le than a carrier ignal, then the actie deice correponding to that carrier i witched off. + + / / π = + i π Fig. 4. Output waeform of the hybrid multileel inerter. Fig. 6 how the relationhip between the inuoidal reference ignal and the triangular ignal which ued to create the ignal; the output of the ignal i either, when > tri or when, < tri, and the ignal width can be written a equation (). A ; A () = tri Nomenclature: Width of the ignal. A Height of the control ignal. tri Period of the triangular ignal. Output oltage of the control ignal. Output oltage of the triangular ignal. tri A r Fig. 5. MC-SH of a 5-leel inerter. tri control > tri Fig. 6. he relationhip between the inuoidal referenceignal and the triangular ignal. tri 79

3 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December + / / + / / + + / / Signal for H bridge inerter Signal for 3 phaeinerter Output waeform of hybrid inerter π/ 6 5π / 6 π 7π /6 π / 6 π Fig. 7. Output waeform of the 5-leel hybrid multileel inerter. π 6 5π π 7π 6 6 π π 6 Output Mod. ( 3 ) Fig. 8. Signal for controlling the hybrid multileel inerter. Fig. 7 how output waeform of the 5-leel cacaded hybrid multileel inerter that it i ued to be the pattern to create the control ignal for hybrid multileel inerter. ( 3 ),, and ignal hown in Fig. 8 are the parameter in digital proce to create all control ignal that they are hown in table II. Modulated ignal i created a equation () and (3), amplitude modulation index ma can be found at the following equation (4); ma in thi paper i.8. III. SIMULAION RESULS he imulation model baed on PSCAD/EMDC i hown in appendix; are 4 and 48, RL load (R i 65 Ω, L i.5 H ), inuoidal reference ignal frequency i 5Hz, carrier ignal frequency i,5hz, and m i.8. Fig. 9. Simulation reult of,,, a Mod. ( 3 ) 3 and modulated ignal. Reult of the imulation; Fig. 9 how modulated ignal,,, and ) ( 3 ignal. Fig. how all control ignal for the power electronic witche. Fig. how the output waeform of phae oltage and phae current. S S S a S a = m a tri π ωt < ( in( ωt ; 6 () 5π < ωt π 6 S a3 S a4 Fig.. Simulation reult of all control ignal for electronic witch deice (IGB). π 5π = matri ( in( ωt) ) ; ωt 6 6 (3) m a = (4) tri ABLE II: DIGIAL PROCESS OF HE CONROL SIGNALS. Electronic witch deice Digital proce a 3 (( ) + ( a 3 (( ) + ( a3 3 (( ) + ( a4 3 (( ) + ( a ia Fig.. Simulation reult of phae oltage and phae current when load i b ib ic c RL (R i 65 Ω, L i.5 H ). I. EXPERIMENAL RESULS Fig. how the topology of the hybrid multileel inerter with eparate DC oltage ource ;4 and 48; that the IGB (G6M33) are ued to be power electronic witche in the H-bridge inerter, and the IGB module (CM75DU-H) are ued to be power electronic witche in the 3-phae inerter. he output oltage of the hybrid 79

4 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December multileel inerter i connected to a 3-phae tep up tranformer (55/38/5Hz, Y-Y) rated.5kw. Prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter a hown in Fig. 3 ha been built in order to erify the propoed hybrid multileel inerter. he control ignal in thi paper are created by the field programmable gate array (FPGA, dicoery III XC3S model) controller. Fig. 4 including output waeform of line-line oltage that line-line oltage HD i 7.9%, 7.4%, and 8.3%. how three ignal; (3 ),, and ; for the hybrid multileel inerter, modulation index i.8. tep up tranformer a b c 3 R Y Y 55 / 38 N H bridge inerter 4 Sa Sa3 Sa Sa4 48 Sb Sb3 Sb Sb4 S S3 S5 S S4 S6 Sc Sc3 Sc Sc4 Fig. 4. he control ignal for hybrid multileel inerter are created by FPGA ( ma =.8). 3 phae inerter Fig.. opology of the hybrid multileel inerter with eparate DC oltage ource; 4 and 48. H bridge inerter 3 phae inerter FPGA Fig. 5. Prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with 3 fluorecent lamp-ballat load. Fig. how prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with a 3-phae induction motor load (no load). Fig. 3 how the experimental reult including phae oltage and phae current; the output phae oltage waeform ha 5 leel that it rm oltage i 6, and the phae current waeform i cloe to inuoidal that it rm current i 786mA, and the output frequency i 5Hz. Fig. 4 how the experimental reult including the phae oltage HD of 6%, and phae current HD of 4.%. Fig. 5 how the experimental reult including output waeform of line-line oltage that line-line oltage HD i 6.%, 5.6%, 6.7%, and the output frequency i 5 Hz. ource and 3 phae tep up tranforme r Fig. 3. Prototype of the 5-leel 3-phae cacaded hybrid multileel inerter. Fig. 5 how prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with a 8W fluorecent lamp-ballat load. Fig. 6 how the experimental reult including phae oltage and phae current; the output phae oltage waeform ha 5 leel that it rm oltage i 5, and the phae current waeform i cloe to inuoidal that it rm current i 36mA. Fig. 7 how the experimental reult including output waeform of line-line oltage and line-line that oltage HD i 7.4%, 6.6%, and 8%. Fig. 8 how prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with RL load (R i 65 Ω, L i.5 H ). Fig. 9 how the experimental reult including phae oltage and phae current; the output phae oltage waeform ha 5 leel that it rm oltage i 95, and the phae current waeform i cloe to inuoidal that it rm current i 78mA. Fig. how the experimental reult including the phae oltage HD of 7% and phae current HD of.7%. Fig. how the experimental reult Fig. 6. he output waeform of phae oltage and phae current (he top i phae oltage that it rm oltage i 5, the bottom i phae current that it rm current i 36mA). 79

5 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December Fig. 7. he output waeform of line-line oltage that line-line oltage HD i 7.4%, 6.6%, and 8%. he output frequency i 5Hz. Fig.. Prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with a 3-phae induction motor rated HP load (no load). Fig. 8. Prototype of the kw 5-leel three-phae cacaded hybrid multileel inerter with RL load (R i 65 Ω, L i.5 H ). Fig. 3. he output waeform of phae oltage and phae current (he top i phae oltage that it rm oltage i 6, the bottom i phae current that it rm current i 786mA). Fig. 4. he output waeform of phae oltage HD of 6%, phae current HD of 4.%. he output frequency i 5 Hz. Fig. 9. he output waeform of phae oltage and phae current (he top i phae oltage that it rm oltage i 95, the bottom i phae current that it rm current i 78mA). Fig. 5. he output waeform of line-line oltage that line-line oltage HD i 6.%, 5.6%, 6.7%. he output frequency i 5Hz. Fig.. Phae oltage HD of 7%, phae current HD of.7%, the output frequency i 5 Hz. (RL load, R i 65 Ω, L i.5 H ). Fig.. he output waeform of line-line oltage that line-line oltage HD i 7.9%, 7.4%, and 8.3%. he output frequency i 5Hz.. CONCLUSION Prototype of the 5-leel three-phae cacaded hybrid multileel inerter conit of a 3-phae inerter and 3 H-bridge inerter that it ue eparate power ource; 4 and 48. he control ignal for power electronic witche are created by FPGA controller uing ignal modulated technique and digital technique. he prototype i teted with three type of load; 8W fluorecent ballat-lamp, RL, and 3-phae induction motor rated HP; without filtering. Reult of the tet; the output line-line and phae oltage ha 5 leel that it HD oltage i between 5.6% and 8.3%, the output waeform of phae current i cloe to inuoidal that it HD current i between.7% and 4.%. 793

6 International Journal of Computer and Electrical Engineering, ol. 3, No. 6, December APPENDIX Fig. 6. he imulation model of a 5-leel three- phae cacaded multileel inerter baed on pcad/emt (ingle phae). ACKNOWLEDGMEN he author would like to thank the Faculty of Engineering at Si Racha, Kaetart Unierity Si Racha Campu, HAILAND, for intrument upport on thi reearch. REFERENCES [] J. S. Lai and F. Z. Peng, Multileel conerter A new breed of power conerter, IEEE ran. Ind. Applica, ol. 3, no. 3, pp , May/June 996. [] L. M. olbert, F. Z. Peng, and. G. Habetler, Multileel conerter for large electric drie, IEEE ran. Ind. Applica., ol.35, no., pp , Jan./Feb.999. [3] K. A. Corzine, M. W. Wielebki, F. Z. Peng, and J. Wang, Control of Cacaded Multileel Inerter, IEEE ran. power electron, ol.9, no.3, pp , May 4. [4] M. Fracchia,. Ghiara, M. Marcheoni, and M. Mazzucchelli, Optimized modulation technique for the gemeralized N-leel conerter, in proc. IEEE power electronic pecialit conf, 5-3, Madrid, Spain, 99. [5] K. A. Corzine and J. R. Baker, Reduced part-count multileel retifier, IEEE ran. Ind. Electron. ol.49, no.3, pp , Aug.. [6] F. Z. Peng, A generalized multileel inerter topology with elf oltage balancing, IEEE ran. Ind. Applica, ol. 37, pp. 6-68, Mar./April 4. [7] M. D. Manjrekar, P. K. Steimer, and. A. Lipo, Hybrid multileel power conerion ytem: a competitie olution for high-power application, IEEE ran. Ind. Applica, ol. 36, pp , May/June. [8] L. M. olber and. G. Habetler, Noel Multileel Inerter Carrier baed Method, IEEE ran. Ind. Applic, ol. 35, pp. 98-7, Sep/Oct 999. [9] B. P.McGrath and Holme, Multicarrier trategie for multileel inerter, IEEE ran. Ind. Electron, ol. 49, no. 4, pp , Aug. [] A. M.Haa, R. J.Kerman, and.a.lipo Carrier-baed -SI Oermodulation Strategie: Analyi, Comparion, and Deign, IEEE ran. Power Electron, ol. 3, no. 4, pp , Jul [] S. Khomfoi, L. M. olbert, Multileel Power Conerter, nd ed. Power Electronic Handbook, Eleier, 7, ch. 3, pp. -5. P. hongprari wa born in Suphanburi, hailand, on June 9, 97. He receied the B.Eng. degree in electronic engineering and M.Eng. degree in electrical Engineering from King Mongkut Intitute of echnology Ladkrabang, hailand, in 995 and 5, repectiely. He i currently lecturer at the Department of Electrical Engineering, Faculty of Engineering at Si Racha, Kaetart Unierity Si Racha Campu, hailand. Hi reearch interet are Power Conerter, Power Electronic, Robotic, Application of Microcontroller and FPGA controller. 794