New Resonance Type Fault Current Limiter

Transcription

1 New Reonance Type Fault Current imiter Mehrdad Tarafdar Hagh 1, Member, IEEE, Seyed Behzad Naderi 2 and Mehdi Jafari 2, Student Member, IEEE 1 Mechatronic Center of Excellence, Univerity of Tabriz, Tabriz, IRAN 2 Faculty of Electrical and Computer Engineering, Univerity of Tabriz, Tabriz, IRAN tarafdar@tabrizu.ac.ir,.b.naderi87@m.tabrizu.ac.ir, m.jafari87@m.tabrizu.ac.ir Abtract Thi paper propoe a new parallel C reonance type Fault Current imiter (FC). Thi tructure ha low cat becaue of uing dry capacitor and non-uperconducting inductor and fat operation. The propoed FC i able to limit fault current in contant value near to pre-fault condition value againt erie reonance type FC. In thi way, the voltage of point of common coupling (PCC) will not change during fault. Analytical analyi i preented in detail and imulation reult are involved to validate the effectivene of thi tructure. Keyword-reonance circuit; fault current limiter; dc reactor; total harmonic ditortion I. INTRODUCTION Growth of power tranmiion and ditribution ytem ha reulted in a continuou increae in ort circuit current level [1]. The mot common way to limit high-level fault current are: upgrading of witchgear and other equipment, plitting the power grid, introducing higher voltage connection (ac or dc), uing high-impedance tranformer and etc. Thee alternative may create other problem uch a lo of power ytem afety, reliability, high cot and more power loe. In uch condition, the realization of a FC i going to be expected, trongly. The SFC tructure offer a good way to limit the fault current level in ditribution network due to natural low- loe in uperconductor during the normal operation [2]. The implementation of FC in electric power ytem i not retricted to uppre the amplitude of the ort circuit; they are alo utilized to variety of performance uch a the power ytem tranient tability enhancement, power quality improvement, reliability improvement, increaing tranfer capacity of ytem equipment and inru current limitation in tranformer [3] [6]. An ideal FC ould have the following characteritic [2]: 1) Zero impedance at normal operation; 2) No power lo in normal operation; 3) arge impedance in fault condition; 4) Quick appearance of impedance when fault occur; 5) Fat recovery after fault removal; Reonance type uperconducting FC have been propoed in literature [7], [8]. Thee type of FC limit fault current by uing variou topologie of erie C reonant circuit. In thi paper new tructure of parallel C reonance type FC i propoed. Serie reonance type FC limit fault current and doe not allow the ort circuit current to increae intantaneouly. It i important to note that, if fault continue, erie reonance type FC will not be able to limit level of fault current, o we propoe parallel C reonance type FC. Parallel C circuit offer high impedance at reonant condition. It can limit fault current by electing variou value for and C. Thi type of FC ha high flexibility for fault current limiting purpoe. Indeed, by uing the propoed FC, fault current will alway have contant value againt erie reonance type of FC. Analytical analyi and deign conideration are preented and their olution i done by MATAB oftware. The circuit operation in normal and fault condition are imulated by uing EMTDC/PSCAD. II. POWER CIRCUIT TOPOOGY AND OPERATION PRINCIPES Fig. 1 ow ingle phae power circuit topology of propoed FC. Thi tructure i compoed of two main part which are decribed a follow: 1) Bridge part: Thi part conit of a Semi-Conductor Rectifier (SCR) bridge containing D1 to D4 diode, a uperconducting dc limiting reactor ( dc ), an IGBT witch, a dc voltage ource and a freewheeling diode ( D ). 2) Reonance part: Thi part conit of a parallel C reonant circuit that i tuned on 5 Hz network frequency and a reitor in erie with the capacitor. Bridge part of FC operate a a high peed witch that change fault current path to reonant part, when fault occur. Obviouly, a a conventional method, it i poible to ubtitute thi part with an anti parallel connection of two emiconductor witche. In thi cae, it i neceary to ue a erie inductor with each witch for limiting evere di dt. Figure 1. Power circuit topology of new propoed reonance type FC f

2 Thee inductor make a voltage drop on FC and affect FC operation in normal tate. But, uing diode rectifier bridge and placing IGBT in thi bridge ha two advantage a follow: 1) Thi tructure ue only one controllable emiconductor device which operate at dc ide, intead of two witche that operate at ac current. So, control circuit i impler becaue of no need to witching ON/OFF at normal operation cae. In addition, there i not witching loe. 2) It i poible to placing a mall reactor in erie with IGBT at dc ide. Thi reactor play two role; Snubber for IGBT to protect it and current limiter at firt moment of fault that will be dicued in detail. In thi tructure, by IGBT a a elf turn-off device, operation delay problem of FC i mitigated. The dc voltage ource i ued to compenate the voltage drop on diode and IGBT. So it value i defined a follow: V = 2V + V (1) dc DF SW Where V SW tand for the voltage drop acro IGBT and the forward voltage drop acro rectifier diode i defined a V. DF Fig. 2 ow that by placing dc voltage ource in propoed FC topology, THD and ditortion of load voltage i reduced [2]. Thi i important to note that dc voltage ource can be provided by diode rectifier [3]. In normal operation of power ytem, mall dc reactor charge to the peak of line current and behave a ort circuit. On the other hand, the dc voltage ource compenate the voltage drop on diode and IGBT witch. So, voltage drop on the bridge become almot zero. Conequently FC doe not affect normal operation of ytem. A fault occur, dc reactor limit ort circuit current and tart to charge. When the line current rie to the pre-defined value that can be et by ytem operator, control ytem turn off the IGBT witch. So, the bridge retreat from the utility. At thi moment, freewheeling diode turn on and provide free path for dicharging dc reactor. oad voltage ditortion When the bridge turn off, fault current go through the parallel reonant part of FC. Conequently, large impedance enter to the circuit and prevent riing the fault current. It i obviou that, in fault condition, parallel C circuit tart to reonance. In thi cae, becaue of reonance, line current ocillate with large amplitude that pae from power ytem equipment. Thi may lead to harm them or put them in tre. But, by placing a reitor ( R ) in erie with the capacitor, tranient wing of current damp quickly. Some previou tructure have ac power loe at reonant circuit in no-fault condition, becaue of placing large inductor in line current path [9], [1]. But, thi tructure ha very lower loe in normal condition. Alo, during fault, propoed FC behave in a way that power ytem i not affected by fault current. So, there will not be any voltage ag on PCC voltage. In addition, at perviou tructure, capacitor i in power ytem, alway. So, oil capacitor mut be ued. But capacitor of thi tructure i bypaed at normal operation of power ytem and dry capacitor with low cot can be ued. III. ANAYTICA ANAYSIS Fig. 3 ow the ingle phae power ytem model of propoed FC. The utility voltage i a three-phae inuoidal waveform where ω and V tand for it angular frequency and effective voltage value in each phae, repectively. The utility impedance i modeled by erie connection of a reitor R and an inductor. Analytical analyi i dicued in three mode a follow: Mode 1: Pre-fault teady tate operation. Mode 2: Jut after fault occurrence until IGBT turning off. Mode 3: Between IGBT turning off and fault removal. A. Mode 1 In normal operation of power ytem, a dicued, SCR bridge bypae reonant circuit. In thi condition, line current ( i ) can be expreed by differential equation (2): V in( ωt) = Ri + ω di dωt (2) oad voltage Time() Figure 2. oad voltage with ( ) and without ( ) dc voltage ource Figure 3. Single phae power ytem model

3 R = R + R (Reitance of ource and load, repectively) = + (Inductance of ource and load, repectively) V : RMS of utility voltage So the line current equation can be derived a: i ( ωt) = ( V R + ω )[( ω R + ω ) e + in( ωt ϕ )] ( R ) ωt ω ϕ = arctan( ω R) (4) B. Mode 2 When a ort circuit occur, the dc limiting reactor can limit the increaing rate of fault current. The IGBT witch doen t operate until line current reach to per-defined value. Since time interval of fault occurrence intant to IGBT operation i very mall, it analyi i not preented in detail in thi paper. C. Mode 3 After IGBT operation, the bridge i witched off and the dc limiting reactor retreat from the utility; then, the fault current i limited by the reonant circuit. So, differential equation of fault current can be expreed a follow: (3) t w : IGBT witch turn off intant. Equation (5) i olved by MATAB oftware and it reult are preented in imulation ection. In addition, the calculation reult of MATAB and imulation of PSCAD are compared together to prove accuracy of analytical analyi. A mentioned before, uing reitor in propoed reonant tructure, can damp tranient wing in primal cycle of fault. After removal of thi tranient tate, the equation of fault current can be expreed by: i = Aco( ωt) + B in( ωt) (7) V R Cω( d b ω ) (1 C ω )( c ω a ω ) A = ( c ω a ω ) + ( d b ω ) V RCω ( a ω c ω) (1 Cω )( d b ω ) B = ( c ω a ω ) + ( d b ω ) a = C, (8) b = R C + RC + R C, c = + RC R +, d = R Conidering (7) and chooing proper value for and C, it i poible to limit the line current in fault condition in a way that it value be near to the pre-fault line current. In thi tate, if fault occur, PCC voltage will not ene the fault. 3 3 C d i dt + ( R C + RC + R C ) d i dt + ( + RCR + )( di dt ) + Ri = 2 ( V Cω )in( ωt) + RCVω co( ωt) With initial value a follow: 2 2 i ( t = tw ) = I ( di dt) ( t = t ) = ( V in( ωt ) I ( R + R )) 2 2 ( d i dt )( t = tw) = ( Vω co( ωtw) 2 + I (( R ) ( 1 C ) ) ((( V in( ωtw ) I ( R + R )) )( R + R )) Where: w w I : Pre-defined line current; (5) (6) IV. SIMUATION RESUTS AND DESIGN CONSIDERATIONS The power circuit topology of Fig. 3 i ued for imulation in fault condition. The imulation parameter are a follow: Sytem parameter: V = 6.6kV ( rm), Z ource =.57 + jω. 3Ω Z load = 15 + jω. 1Ω Z Fault =.1+ jω. 1Ω Z line =. 5Ω FC parameter: R = 16Ω, C = 15µ F, = 68mH dc = 1mH V = V = 3V DF SW I =5A Fault occur at 1.5 and lat.12 (6 cycle of power frequency). A fault occur, without uing FC, fault current increae extremely (Fig. 4a). Alo, without uing R in reonance circuit, tranient ocillation appear on the line current caued

4 by C reonance a own in Fig. 4b. After damping of thee tranient, line current become a mall value. Fig. 4c ow the line current in fault condition with uing propoed reonant type FC. A own in Fig. 4c, when fault current reache to I that i the pre-defined fault level, IGBT turn off ( at tw = 1.52 ) and line current i mitigated in fault condition. After fault removal, IGBT turn on again and line current return to the normal tate, after negligible ditortion. Fig. 5 ow dc reactor current. A fault occur, it tart to charge until IGBT turning off. Then freewheeling diode turn on and dicharge dc reactor. After fault removal, dc reactor recharge becaue of reonant circuit voltage. With dicharging reonant circuit, dc reactor current dicharge and return to normal tate. Fig. 6 ow PCC voltage with and without propoed tructure. A own in thi figure, propoed FC can prevent voltage ag on PCC, properly. To demontrate the accuracy of calculation, differential equation (5) that ow the line current in fault condition, i olved by MATAB oftware and reult i diplayed in Fig. 7. ine current (ka) Thi figure i in accordance with Fig. 4c. Value and variation of curve ow that reult of calculation are adapted by imulation reult of PSCAD. Fig. 8 ued to chooe proper value for C, and R. Curve are plotted for R from 1 to 1 ohm. ower limit of R i elected to enure proper tranient repone of reonant circuit. Standard value for C i obtained from [11]. PCC voltage (kv) DC reactor current (ka) Time () Figure 5. Dc reactor current Fault occurance intant Time () Time () (a) Figure 6. PCC voltage without ( ) and with ( ) propoed topology ine current (ka) Time () (b) Figure 7. Fault current calculated by MATAB.4 IGBT turning off Fault removal intant ine current (ka) Fault occurance intant IGBT turning on -.8 Time () (c) Figure 4. Fault current (a) without FC (b) without FC (c) with propoed FC R in reonant type Figure 8. Variation of fault current repect to R

5 It i conidered that feeder average current i 256A at tet ytem. In thi condition, pre-deired value of fault current (256A) can be achieved by two value for reonant circuit parameter a follow: Cae 1: C = 15µ F, = 68mH, R = 16Ω Cae 2: C = 17µ F, = 95mH, R = 49Ω In cae (1), R i maller than it value in cae (2). So, generated heat in R i reduced in fault condition. A a reult, deign of R become impler. However, we can chooe another value for R, for example lower than 16Ω, in thi cae (A own in Fig. (8)), line current in fault condition will be lower than pre-fault condition value. In addition, tranient wing of fault current will be increae. V. HARMONIC STUDY A explained previouly, uing the dc voltage ource in propoed tructure and compenation of voltage drop on emiconductor device reduce THD of voltage waveform. Magnitude of dc voltage ource obtain from (1). Fig. 9 ow the frequency pectrum of load voltage in normal operation of power ytem with and without dc voltage ource. A own in Fig. 2 and Fig. 9, by uing dc voltage ource in propoed topology, the ditortion of voltage waveform in normal operation are decreaed to lower value. Simulation reult prove thi tatement a follow: oad voltage THD, without dc voltage ource: 1.98% oad voltage THD, with dc voltage ource:.61% It i important to note that the THD of load voltage i near to zero for propoed tructure. VI. CONCUSIONS In thi paper, a new topology of parallel C reonant type fault current limiter that include a erie reitor with the capacitor of C circuit i introduced. The analytical analyi and deign conideration for thi tructure of FC are preented. The overall operation of mentioned FC in normal and fault cae are tudied in detail. Propoed reonant type FC can limit fault current in a way that PCC voltage doen't change during fault. Thi mean that, in cae of tranient fault, it i not neceary to open the line. By uing R in propoed topology, tranient wing of current caued by reonance jut after fault damp quickly. In addition, thi tructure ha low loe, low harmonic ditortion, low cot becaue of uing dry capacitor and non-uperconducting inductor, fat operation becaue of uing IGBT witch and capable of controlling fault current at contant value againt erie reonant type FC. In general, propoed reonant type FC ha high flexibility for fault current limiting aim. REFERENCES [1] Zhang Xiaoqing, Ming i, Uing the Fault Current imiter With Spark Gap to Reduce Short-Circuit Current, IEEE Tran. Power Del., vol. 23, no. 1, pp , January 28. [2] M. Tarafdar Hagh, M. Abapour, Non-uperconducting fault current limiter, Euro. Tran. Electr. Power, Publied online in Wiley InterScience, pp , March 28. [3] Mehrdad Tarafdar Hagh, Mehdi Abapour, Nonuperconducting Fault Current imiter With Controlling the Magnitude of Fault Current, IEEE Tran. Power Elec., vol. 24, no. 3, pp , March 29. [4] M. M. R. Ahmed, G. A. putru,. Ran, Power Quality Improvement Uing Solid State Fault Current limiter, IEEE, Tranmiion and Ditribution Conference, Aia Pacific, vol. 2, pp , Oct. 22. [5] M. Tarafdar Hagh and M. Abapour, DC reactor type tranformer inru current limiter, IET Electr. Power, vol. 1, no. 5, pp , Appl., 27. [6] M. Tuda, Y. Wlitani, K. Tuji, K. Kakihana, Application of Reitor Baed Superconducting Fault Current imiter to Enhancement of Power Sytem Tranient Stability, IEEE Tran. Appl. Supercond., vol. 11, no. 1, pp , March 21. [7] K. Arai, H. Tanaka, M. Inaba, Tet of Reonance-Type Superconducting Fault Current imiter, IEEE Tran. Appl. Supercond., vol. 16, no. 2, pp , June 26. [8] H. Arai, M. Inaba, T. Iigohka, Fundamental Characteritic of Superconducting Fault Current imiter Uing C Reonance Circuit, IEEE Tran. Appl. Supercond., vol. 16, no. 2, pp , June 26. [9] Hector G. Sarmiento, A Fault Current imiter Baed on an C Reonant Circuit: Deign, Scale Model and Prototype Field Tet, irep Sympoium-Bulk Power Sytem Dynamic and Control-VII, Revitalizing Operational Reliability, pp. 1-5, Augut 27. [1] S. Henry, T. Baldwin, Improvement Of Power Quality By Mean Of Fault Current imitation, IEEE, Sytem theory, Proceeding of the Thirty-Sixth Southeatern Sympoium on, pp [11] High Voltage Capacitor and Power Supplie, General Atomic, Electronic Sytem, gaep.com Figure 9. Frequency pectrum of load voltage (kv)