Self-Programmable PID Compensator for Digitally Controlled SMPS

Transcription

1 6 IEEE COMPEL Workhop, Renelaer Polytechnic Intitute, Troy, NY, USA, July 16-19, 6 Self-Programmable PID Compenator for Digitally Controlled SMPS Zhenyu Zhao and Alekandar Prodi Univerity of Toronto Toronto, Canada M5S 3G4 Paolo Mattavelli DTG, Univerity of Padova Vicenza - Italy Abtract-Thi paper how an auto-tuning ytem for digitally controlled witch-mode power upplie (SMPS) that automatically adjut parameter of PID compenator baed on pre-pecified bandwidth requirement. The PID compenator parameter are determined from intentionally introduced limit cycle ocillation (LCO) through two conecutive auto-tuning procedure. Firt, the placement of pole and zero i defined from LCO at the corner frequency of the power tage. Then, the gain of the PID compenator i found from the ocillation occurring at the deired croover frequency of the ytem. The propoed auto-tuning procedure i verified through Matlab/Simulink imulation that how fat load tranient repone and hort ettling time. I. INTRODUCTION In a recent publication [1] an LCO-baed auto-tuning ytem ha been demontrated a an effective olution for the etimation of parameter of digitally controlled SMPS and conecutive compenator adjutment. It ha been hown that limit-cycle ocillation contain ueful information and that by examining their frequency and amplitude parameter of power tage (PS) uch a the value of inductor, output capacitor and load, can be determined and conequently ued for PID compenator adjutment. The method i baed on a relatively complex pre-calculation of the relation between the LCO feature and power tage parameter value, whoe reult are later tored in look-up table to implify implementation. In thi paper we how an extenion of thi concept, an autotuning method that doe not require parameter etimation and therefore can be realized in a impler manner. Controller coefficient and it gain are adjuted directly from the meaured LCO eliminating the need for pre-calculation of the correponding control parameter. Thi elf-programming digital PID compenator minimize compenator deign effort and can be ued with a variou power tage having wide range of inductor, capacitor and load value. Practically, a ytem deigner only need to et the cro-over frequency, e. t. bandwidth, of the loop gain and the remaining part of the compenator deign i automatically performed. A imilar tuning concept ha been reported in [4] where relay feedback controller are applied. However, the propoed LCO baed tuning method take advantage of inherent nonlinear characteritic and more information of the ytem. Moreover it i baed on mall ocillation (i.e. limit-cycle ocillation) which may already appear in dc-dc converter and whoe amplitude i inherently limited to a few Leat-Significant-Bit (LSB) of the Analog to Digital (ADC) converter. A different auto-tuning approach, baed on non-parametric method for the on-line aement of ytem dynamic in dcdc converter, ha been propoed in [,3]; the method reported in [,3] are very intereting for converter tranfer function identification, but they require open-loop operation during the identification proce and lightly more complex ignal proceing. A block diagram of the elf-programmable ytem i hown in Fig.1. It comprie of a conventional digital pule width modulator controller (analog-to-digital converter (ADC), digital pule-width modulator (DPWM), and programmable compenator) and an auto-tuner. The tuner ha an intability detector / mode elector block [1], which can be triggered periodically or externally, upon intability in the ytem i detected, and a LCO initiator for introduction of limit cycle during tuning proce. The limit cycle ocillation are intentionally introduced during monitoring and auto tuning proce, through a reduction of the DPWM reolution [1]. A it will be decribed in later ection in more detail, all Fig. 1. Self-programmable SMPS ytem block diagram of the block of the elf-programmable controller can be /6/$ X/6/$. 6 IEEE. 11

2 implemented with a very imple hardware allowing it ue in low-power SMPS (power upplie for miniature portable device, conumer electronic ). Traditionally, auto-tuning ytem have not been utilized in low-power application due to high complexity and cot of conventional olution ued in higher power ytem. The paper i organized a follow: the following ection briefly addree the relationhip between LCO feature and ytem tranfer function and it explain how LCO are ued for deigning PID coefficient. The PID tuning and deign procedure with bandwidth control i decribed in Section III. Section IV how imulation reult obtained with a Matlab/Simulink model that utilize auto-tuning method. III. SELF-PROGRAMMABLE PID COMPENSATOR Self-programmable PID compenator, whoe implified block diagram i hown in Fig.3, can operate in three different mode. When all three data witcher (SW1 to SW3) are in regular mode, it operate a a conventional controller. Digital II. PROPERTIES OF LIMIT-CYCLE OSCILLATIONS IN DIGITALLY CONTROLLED SMPS In a digitally controlled SMPS, whoe model i hown in Fig., limit cycle ocillation can exit even when the ytem i conditionally table and the output voltage i kept around deired reference V ref. The LCO are caued by nonlinear element, ADC and DPWM, whoe gain M DPWM and M ADC repectively, depend on input ignal amplitude. Fig.. Linear model of SMPS feedback loop The LCO occur at certain magnitude of output voltage v out and control ignal d, for which the ytem loop gain ( ) = (, ) ( ) ( ) (, ) T M d G G M v dpwm vd c ADC out ha unit magnitude and phae of -18, i.e. T() = Given that LCO condition trongly depend on G vd () and G c (), the power tage control-to-output and compenator tranfer function repectively, by examining LCO we can etimate ome of their parameter. Even more, ince in digitally controlled ytem G c () i uually exactly known, etimation proce can be implified and, a will be hown in the following ection, all main feature of G vd () can be accurately determined. Conequently, an appropriate PID compenator can be automatically deigned to atify predetermined bandwidth requirement. (1) equivalent of the analog output voltage v out i compared to the reference V ref and the reulting error ignal i proceed with PID compenator, whoe coefficient are determined through auto-tuning proce. In addition, it ha two auto-tuning mode, labeled a a.t.1 and a.t., defined with the correponding poition of the data witcher. In auto-tuning mode the reolution of the DPWM i intentionally reduced by ending truncated binary control ignal d tr to it input. A a reult a trong nonlinearity cauing LCO i introduced allowing dynamic adjutment of PID compenator parameter. In the firt auto-tuning tep PID compenator zeroe w z1 and w z are defined. Then, in the following tep appropriate gain of the compenator, K p, i determined to reult in a deired bandwidth of the controller f bw that can be et externally. In both tep the reolution of the ADC i kept ufficiently high, o that it nonlinear quantization effect are negligible compared to thoe of the DPWM. The two-tep auto-tuning proce can be explained through the following example auming that a buck-converter with control-to-output tranfer function G vd Fig. 3. Self-programmable PID compenator block diagram Vg Vout / D ( ) = () Qω ω Qω ω o i the power tage, where corner frequency ω and Q factor are determined with the power tage component and it load [5]. The value D define teady-tate duty ratio value. In () and hereafter in the paper we will aume that the zero of the o 113

3 ESR output capacitor i outide the control bandwidth, i.e. we conider the cae of output capacitor with mall ESR. During the firt auto-tuning tep SW1 and SW3 are et in poition a.t.1 and the output voltage i regulated with a digital integrator, whoe analog equivalent ha the following form 1 GC1 ( ) = K I D (3) The compenator gain, K I, i multiplied with D to eliminate the influence of the input voltage change effectively behaving a a feedforward element. The reulting loop gain in thi mode i decribed with the following equation and depicted in Fig.4. It can be een that in thi cae phae hift of 18 alway correpond to the corner frequency of the power tage. A a reult, the LCO can occur only at the corner frequency and their magnitude i proportional to Q factor, which trongly influence the gain of G vd () at that frequency. Hence, by meauring amplitude and frequency of the limit cycle ocillation thee two parameter can be directly determined. In the dual-mode etimator in Fig. 3 Magnitude (db) Phae (deg) ( ) T = M ( d, G ) ( G ) ( M ) AT1 dpwm C1 vd ADC Power tage G () vd Loop gain T AT1 () Integrator LCO amplitude LCO frequency Fig. 4. Bode plot of ytem during firt tep tuning include imple hardware for amplitude and frequency meaurement [1] to determine the LCO parameter. Baed on the meaured reult elf-programmable PID compenator i adjuted in accordance with the following equation: r + ω + ω Q GC() = D KI k + ωlco+ ωlco ALCO = D KI LCO LCO (5) (4) where ω LCO and A LCO are the radial frequency and amplitude of LCO, repectively. In accordance with the procedure decribed in [6] the compenator zeroe are adjuted with factor k to minimize the influence of the econd-order pole in G vd (). Initially the gain K I i et at a low value and the elftuning compenator i witched into the econd auto-tuning mode. A hown in Fig. 5, the reulting loop gain, T AT (), in thi mode reaemble behavior of a pole at origin and the whole ytem behave a an integrator, i.e. K TAT ( ) = Mdpwm ( d, )) G ( ) G ( ) C vd MADC To complete compenator deign and achieve deired bandwidth, the gain of compenator in (5) need to be determined. The gain etimation i performed in two tep: 1) LCO at the deired croover frequency are introduced and ) the value of K I i determined from the meaurement of the mall ignal gain of nonlinear element, i.e. DPWM. Magnitude (db) Phae (deg) phae hifter Loop gain T () AT Loop gain after tuning Loop gain before tuning croover frequency f bw The idea i baed on the fact that at the amplitude and frequency of LCO the gain of nonlinear element, i.e. DPWM, i automatically adjuted to reult in unit loop gain T AT (). In other word, if the LCO occur at predefined croover frequency, the gain of DPWM i exactly equal to the deired value of K I when the nonlinear effect i eliminated and the controller operate in regular mode utilizing high-reolution DPWM. The abovementioned two-tep proce i performed during the econd auto-tuning tep, when all witcher of Fig. 3 are in the poition a.t.. In thi cae, the PI compenator of the firt tep i replaced with the initially deigned low-gain PID (5) and a programmable phae hift block i added. For example, in thi cae we ue a econd-order unity-gain low-pa filter with programmable cutoff frequency a our phae hifter. The P Unit gain Fig. 5. Bode plot of ytem during econd tep tuning (6) 114

4 programmable phae hift introduce additional -9 at the deired frequency, f bw, to reult in the total phae hift of 18 and LCO at the ame frequency. After the LCO are initiated the gain of DPWM (deired K I ) i determined through meaurement of the ratio of variation of the truncated ignal d tr and it high reolution value (ee Fig.3) M dpwm dtr[ n] = KI = d [ n] Finally, the elf-programming PID i witched to regular mode and the initial low gain value i replaced with the one given in (7). Becaue the phae hifter i removed the reulted new cloed-loop ytem will have a phae margin of 9 degree a hown in Fig. 5. It hould be noted that in actual ytem implementation the bandwidth of the controller can be compromied with the proceing delay of the other element of the ytem caued by finite proceing and analog-to-digital converion time. In addition, the delay of the uniformly ampled DPWM need to be included. Thu, there are everal delay in the control loop and, correpondingly, the pecification on the required phae margin (or bandwidth) need to be adjuted accordingly. The propoed autotuning procedure can be eaily extended to account for thee delay by repreenting the control-loop tranfer function in the Z-domain, including the PWM modulator tranfer function and the control and ADC delay [9]. However, under the aumption that the time delay i much maller compared to time contant of the deired ytem and controller bandwidth far from PS corner frequency, the propoed method may be applied to achieve acceptable dynamic repone. IV. SYSTEM VERIFICATION Baed on diagram hown in Fig.1 a Matlab/Simlink model of a khz 1 V-5 V buck converter i built and the reult Truncated duty cycle command d tr Original duty cycle command d d tr (7) time () x 1 4 d time () x 1 4 Fig. 6. Input (bottom) and output (top) of the nonlinear element (DPWM quantizer) V out (volt) A 1A time () x 1 3 Fig. 7. Tranient repone of the auto-tuned ytem to a load current change from.4a to 1A proving the proper operation of the ytem are obtained. The ytem parameter ued in the imulation are: L=µH, C=47µF, witching frequency f w = khz and Controller bandwidth 6 khz. Some reult of firt tep auto-tuning have been explicitly reported in [1] and will not be included here. Reult of the newly propoed econd tep auto tuning are hown in Fig. 6 to 7. The truncated DPWM ignal d tr and it high reolution input ignal d are hown in Fig. 6 repectively. It i een that the reulted LCO frequency i around 3 khz. A we tated in previou ection the dicrepancy from deignated controller bandwidth i a reult of ytem delay. Form thi example, it alo how that the ytem ha an ability to provide a good control bandwidth by itelf even in the cae of an unrealitic bandwidth etting. The gain of DPWM i obtained to be equal to 5 by applying (7). Figure 7 how load tranient repone of the auto-tuned ytem for output current change from.4a-1a. It i een that the output i able to ettle down in 6 witching cycle (3µ ), which i comparable to tate of the art analog olution. An FPGA-baed phyical prototype utilizing the preented controller architecture i currently under contruction. Experimental reult will be preented in our future work. V. CONCLUSIONS A elf-programmable PID compenator i preented. It i hown how the information extracted from limit-cycle ocillation (LCO) can be ued for automatic compenator deign. The ytem ha relatively imple hardware tructure and a uch i uitable for low-power SMPS application, where auto-tuning method have not been uually ued due to the high complexity of conventional auto-tuning method deigned for high power ytem. Effective operation of the ytem i verified through Matlab/Simulink imulation and it wa hown that fat tranient repone comparable with tate of the art analog olution can be achieved. 115

5 REFERENCES [1] Zhenyu Zhao, Huawei Li, A. Feizmohammadi and A. Prodic, Limit- Cycle Baed Auto-Tuning Method for Digitally Controlled Low-Power SMPS, in Proc. IEEE APEC Conf., 6, March 6, pp [] B. Miao, R. Zane, D. Makimovic, Sytem Identification of Power Converter with Digital Control through Cro-Correlation Method, IEEE Tranaction on Power Electronic, vol., no. 5, pp , Sept. 5. [3] B. Miao, R. Zane, D. Makimovic. Automated digital control deign for witching converter, IEEE Power Electronic Specialit Conference (PESC 5), Recife, Brazil, June 5. [4] W. Stefanutti, P. Mattavelli, S. Saggini, M. Ghioni, Autotuning of Digitally Controlled Buck Converter Baed on Relay Feedback, IEEE Power Electronic Specialit Conference (PESC 5), Recife, Brazil, June, 5.. [5] Robert W. Erickon and Dragan Makimovic, Fundamental of Power Electronic - Second Edition. Kluwer [6] A. Prodic and D. Makimovic, Deign of a digital PID regulator baed on look-up table for control of high-frequency DC-DC converter, in Proc. IEEE Workhop on Computer in Power Electronic., June,pp [7] A.V. Peterchev, S.R. Sander, Quantization reolution and limit cycling in digitally controlled PWM converter, IEEE Tran. on Power Electronic, Vol. 18, No. 1, January 3, pp [8] H. Peng, D. Makimovic, A. Prodic, E. Alarcon Modeling of Quantization Effect in Digitally Controlled dc-dc Converter, IEEE PESC 4, Aachen, Germany, 4. [9] Van de Sype, D.M.; De Gueme, F. De Belie, K.; Van den Boche, A.R.; Melkebeek, J.A.; Small-ignal z-domain analyi of digitally controlled converter ; IEEE Tran. on Power Electronic, Vol. 1, No., March 6, pp