PULSEWIDTH CONTROL WITH DELAY LOCKED LOOP

Transcription

1 PULSEWITH ONTOL WITH ELAY LOKE LOOP Goran S. Jovanović and Mile K. Stojčev Faculty of Electronic Engineering, Univerity of Niš, Aleandra Medvedova 4, Niš, Serbia, Abtract-- The duty-cycle of a cloc, within the VLSI I, i liable to be changed when the cloc pae through everal buffer tage in the multitage cloc buffer deign. The pule-width may be changed due to unbalance of the p and n MOS tranitor in the long MOS buffer. Thi paper decribe a delay loced loop with double edge ynchronization mainly ued in a cloc alignment proce. SPIE imulation reult, that relate to.2 mm MOS technology, hown that the duty-cycle of the multitage put pule can be preciely adjuted to (50 0.8)% within the operating frequency range, from 55 MHz up to 66 MHz. Index term-- dll, duty cycle corrector, delay line. INTOUTION Almot all complex ynchronou MOS digital VLSI I rely on cloc pule to control data tranfer. In order to reach a highet circuit peed, the cloc ditribution ytem mut be carefully deigned. A great deal of attention ha been paid to cloc recovery, cloc regeneration, timing, and ditribution []. Automatic control technique, uch a Phae-Loced Loop (PLL) and elay-loced Loop (LL) have been widely ued in high-peed cloc alignment application uch a double-data rate () SAM, pipelined microproceor, networ proceor, etc. [2]. In a PLL implementation the chip ha it own reference cloc ocillator (VO) that i phae-loced to an external reference cloc. In general, a PLL cloc aligner i uperior in application where noie on the reference cloc dominate, and elf-induced jitter within the VO i negligible. On the other hand, a LL provide uperior performance when a clean reference cloc i available. A LL i commonly ued to loc the phae of the buffered cloc to that of the input data. Typically, we meet thi in application where no cloc ynthei i required, uch a often the ituation for multi-chip digital ytem with well-deigned ytem cloc ditribution networ [2]. In high-peed deign a multitage cloc buffer implemented with a long inverter chain i often needed to drive a heavy capacitive load. For thee deign, a well a for application in which the timing of both edge of the cloc i critical [0], it i difficult to eep the cloc duty cycle at it ideal value 50 %, primarily due to variou aymmetrie in ignal path and unbalance of the p and n tranitor in the long buffer. A a conequence the cloc duty cycle will deteriorate from 50 %, and in the wort cae, the cloc pule may diappear inide the cloc buffer, a the pule width become too narrow or too wide [6-9]. uty-cycle ditortion i uually addreed in PLL by imply running the PLL VO at twice the ytem frequency and uing a pot divider triggered on one edge of the VO put to produce the put cloc of the PLL. Thi enure good 50 % duty cycle. In a LL, however no frequency multiplication i poible. Therefore, the duty-cycle of the put ignal mut be corrected to 50 %. A conventional olution i to attach duty-cycle correction circuit to the cloc put driver with the price of added area [4]. In thi paper, we decribe a new tructure of a LL circuit with cloc alignment capability of both leading and trailing put pule edge. Thi circuit can be ued to obtain correct the duty-cycle factor (50 %) in a multitage cloc buffer. 2. LL WITH OUBLE EGE SYNHONIZATION The tructure of the propoed elay Loced Loop with ouble Edge Synchronization (LL ES) cloc alignment circuit i pictured in Fig.. The clic aligner i compoed of a voltage controlled delay line, VL, two phae detector, P and P2, two charge-pump, P and P2, two firt

2 order low-pa filter, LP and LP2, and a multitage cloc buffer, B. The negative feedbac in the loop adjut the delay through the VL by integrating the phae hift error that reult between the periodic reference input, LK in, and the multitage put, LK. Voltage ontrolled elay Line - VL - harge V ctrl V Filter ctrl2 Pump - LP - - LP2 - Phae etector - P - Low-Pa V BP UP 2 N 2 Phae etector 2 - P2 - loc Buffer - B - Low-Pa Filter 2 harge Pump 2 -P- -P2- Fig.. LL architecture with double edge ynchronization LK The underlying idea for thi approach i to provide delay regulation for both a riing and trailing edge of the put cloc pule LK. For implementation of variable delay regulation the building bloc VL i ued. The control voltage (V BP ) define delay regulation of a riing (trailing) cloc pule edge. The phae detector P (P2) compare phae hift of riing (trailing) edge between the input, LK in, and put, LK, cloc pule. UP (UP2) pule caue I p to add charge to loop filter capacitor, wherea N (N2) pule remove charge. The LP (LP2 ) put, V ctrl (V ctrl2 ), i connected to the VL control input at node (V BP ). When the ytem, from Fig., enter in table tate both edge of LK are ynchronized and phae hifted in repect to the referent cloc LK in. An important feature of thi architecture i that the duty-cycle of LK i maintained at value of 50 %. 3. EQUIVALENT MOEL OF LL-ES: TANSFE FUNTION AN PULSE- WITH The equivalent model of a LL-ES i pictured in Fig. 2. It i decompoed into two independent control loop, LL- and LL-F. The upper one, LL-, determine a time delay of the put riing edge, while the lower, LL-F, define the time delay of falling edge. Both control loop are of almot identical tructure. The difference are the following: i) The phae detector P i enitive to a riing, while P2 to a falling pule edge; ii) The voltage controlled delay line VL- define the time delay of a riing put pule edge, while VL-F of the falling edge. The building bloc P ha identical tranfer function a P2. The tranfer function of contituent LP and LP2 are identical, too. ref ref LL-F LL- reff F K P K P IP KLP K L V Phae harge ctrl elay Line etector Pump (riing edge) P P low-pa filter LP K PF K PF F KLPF Phae etector harge Pump 2 P2 P2 F LP2 K LF V ctrl2 elay Line (falling edge) low-pa filter 2 Fig. 2. Equivalent model of LL-ES. Having in mind that the delay alignment i performed independently for the riing and falling edge, in the analyi that follow, we aume that LL-ES operation can be decribed a independent activitie of two eparate loop. Our analyi i baed on frequency repone of the LL and i imilar to that one decribed in []. Accordingly, for the upper loop, the put pule delay (), i related to the input delay, ref (), by P ( ( ) ) ref P LP ref L F where: dp P correpond to phae d T detector enitivity; dip P IP charge pump current d P () enitivity; dvctrl LP loop filter tranfer function; di P and d L delay line enitivity, dv ctrl with: f ref frequency of the referent cloc, ; T ref time period of referent cloc; duty-cycle of P put at f ref ; delay ref difference; put charge pump current; and filter capacitance. By rearranging Eq. (), for the LL cloed loop tranfer function, H LL (), we obtain H LL ref + P P + + N P P P P L L L (2)

3 where N P P L f ref I P repreent a pole of the LL tranfer function. L By analyzing Eq. (2) we conclude that the LL ha firt order tranfer function and the frequency of it pole correpond to a loop bandwidth. The delay at the LL-ES put can be determined according to the tranfer function which i obtained uing an identical approach a one for conventional LL architecture. oncerning the rie pule edge, a tranfer function ha the form defined by Eq. (2). Accordingly the delay of a riing edge i defined by H LL in in. (3) + N For the tranfer function of the falling edge, H LLF (), we have F H LLF (4) + NF fref IPF LF where NF. The delay of a falling edge i F H + NF LLF F. (5) The pule-width W ref and W of the reference cloc,, and from the LL-ES put, LK, (ee Fig. 2) are defined a W and W F ref, repectively. The pule-width of the LL-ES put depend on a difference between and F and i defined a W + N in F + NF in (6) ue to ymmetry in the LL-ES, i.e. identical realization of the upper and lower branch in the circuit model preented in Fig. 2, the following i valid, N NF N. Accordingly, Eq. (6) can be written a W ( in ) + N (7) Wref + N Finally the tranfer function H W () which define the ratio between the put and input pule-width i given a W HW (8) W ref + N By analyzing Eq. (8) we can conclude that the LL- ES i: firt order ytem, alway table, and the duty-cycle of the referent input,, and put pule, LK, i identical, an i equal to 50%. 4. IUITS IMPLEMENTATION In the equel we will decribe, in more detail, the tructure and principle of operation of each contituent of a LL-ES baed cloc aligner. 3.. Voltage controlled delay line The actual implementation of a VL i compried of a number of cacaded variable delay buffer. Each delay buffer (adjutable timing element) i of identical tructure. urrent tarved delay element (SE) wa choen a a convenient candidate for realization of the delay buffer. The main deign deciion for uch a choice wa the following: SE provide independent delay regulation of both riing and falling cloc pule edge. Independent delay regulation can be achieved by varying the current of p and n MOS tranitor. In conventional SE (ee Fig. 3(a)) a ingle control voltage V ctrl, generated by a bia circuit, modulate the on reitance of pull-down M 3, and through a current mirror, pull-up M 4 [5]. The variable reitance control the current available to charge or dicharge the paraitic load capacitance. V ctrl M 9 M 8 M 7 bia circuit in (a) V BP M 4 M 2 M M 3 M 6 M 5 Fig. 3. Modified current tarved delay element In order to achieve independent, intead of ingle, variable reitance control, we propoe here a modified verion of SE, a one given in Fig. 3(b). In our approach, both control voltage, and V BP, directly drive gate of M 3 and M 4 MOS tranitor, repectively. Tranitor M 5 and M 6 act a ymmetric load and are ued for two purpoe: a) to linearize a voltage-to-delay tranfer function of the SE; and V BP in M 4 M 2 M (b) M 6 M 5 M 8 M 7

4 b) provide correct initial condition for LL operation even in a cae when both control voltage and V BP are -of-regulation limit (for example, M 4 and M 3 are witched off). The modified SE wa deigned for.2μm MOS technology, for 5V power upply voltage. A SPIE imulation reult that correpond to delay function of both riing and falling pule edge are given in Fig. 4. The obtained reult in Fig. 4 how that linear regulation of voltage-veru-delay can be achieved. In general, SE offer good delay line tability in repect to temperature and upply voltage variation. It main diadvantage i relatively limited range of delay regulation, i.e. low-enitivity. elay [p] iing edge Falling edge V 600 BP Voltage [V] Fig. 4. iing and Falling edge delay in term of control voltage 3.2 Phae detector The phae detector meaure the phae difference between the time reference and the delay chain. High preciion dynamic phae detection circuit baed on true ingle phae logic [3] i adopted in our deign. The main advantage of thi circuit are imple hardware tructure, high-peed of operation, and mall dead zone [5]. The UPx and Nx (x refer to or 2) are ued to control the charge-pump circuit Px. The P (P2) i enitive to riing (falling) cloc pule edge. A modification, in repect to tandard olution [5], i performed by ubtituting MOS tranitor P 2, N 2, P 22, and N 22 (ee Fig. 5 (a)) with complementary one N, P 3, N 2, and P 23 (ee Fig. 5(b), repectively. P P 2 P 3 N2 P N P 2 P 3 Operational principle of P and P2 are hown in Fig. 6. The width of UP and N ignal are proportional to the phae difference of the input ignal. Fig. 6a (6b) how the operation of P (P2). Waveform on the left ide of Fig. 6a (6b) correpond to a cae when the ignal LK (ee Fig. 2) lead in repect to the ignal. Otherwie, timing diagram on the right ide are valid ( lead the LK ignal). LK LK (a) (b) LK LK Fig. 6. Waveform of input and put ignal for (a) phae detector and (b) phae detector harge pump and loop filter The charge-pump and loop filter tructure i preented in Fig. 7. Tranitor P and N act a witching element driven by pule UP and N, while tranitor P 2 and N 2 are employed a current in and ource, repectively. The charge-pump charge or dicharge the filter capacitor,. The voltage on thi capacitor, V ctrl (V BP or in Fig. 2), et the VL tage propagation delay. The chargepump the realization of an integrator tranfer function with no additional active amplifier, reulting in a zero-phae error in teady tate. A mall capacitor,, i ued for the low-pa loop filter. The current level of the charge-pump and the charge delivered/accepted at every riing/falling cloc edge tranition are et to a mall value [5]. Thi allow the implementation of the loop capacitor on chip. I ref M 5 8/6µ M 6 M 0 M 9 From Phae etector x UP x V P M 4 N N 3 N 2 N 3 UP2 M 3 V ctrl x M 3 M 4 M 8 V N M 2 LK LK M M 2 M 7 M N x P 2 P 22 P 23 N22 P 2 N 2 P 22 P 23 Bia circuit harge Pump x Low-Pa Filter x N 2 (a) N 23 Fig. 5. Implementation of phae detector for (a) raiing and (b) falling edge N 22 (b) N 23 N 2 Fig. 7. urrent pump and loop filter The bia circuit provide correct operation of the charge pump. It tructure i given on the left ide of Fig. 7. Thi circuit generate two control voltage, V P and V N. Thee voltage define the charge and

5 dicharge current of loop capacitor,, that pa through tranitor M 2 and M SIMULATION ESULTS The ES-LL etched in Fig. 2 i implemented in.2 µm MOS technology. It i upplied with 5V. SPIE imulation reult that relate to referent cloc excitation f ref 80MHz are given in Fig. 8. The ES-LL i operative within the frequency range from 55 MHz up to 66 MHz. duty-cycle error (%) frequency (MHz) Fig. 9. uty-cycle error. 6. ONLUSION Fig. 8. Simulation of LL with ouble Edge Synchronization Timing diagram that correpond to referent input cloc pule,, and buffer put, LK, are given in Fig. 8(a). Thi Fig. how that the locing time, T LOK, between the referent and put LK pule i le than 200n. We define T LOK a a time interval tarting from initial condition up to the intant when total coincidence of riing and falling edge between both pule, and LK, exit, (ee Fig. 8(a)). If we aume that i ymmetrical then the coincidence correpond to 50% duty-cycle of LK. Fig. 8(b) (8(c)) deal with waveform that are obtained at the put UP (UP2), N (N2), and V ctrl (V ctrl2 ). A can be een from Fig. 8(b) (8(c)) UPx and Nx ignal define the control voltage V ctrlx during the tranition period (0 < t < T LOK ). After that the ytem enter in table tate and UPx and Nx ignal diappear and V ctrl x tae a contant value. According to the obtained reult we can conclude that the propoed ES LL can be een to have a wide-operational range and good duty cycle correction capability. According to the obtained reult we can conclude that the propoed ES-LL can be een to have a wide-operational range and good duty-cycle correction capability. Simulation reult preented in Fig. 9 how that, within the full LL-ES operating range (55 66 MHz), the duty cycle error i le then 0.8%. In thi paper a new LL architecture with cloc alignment capability of both leading and trailing edge i decribed. The propoed circuit wa imulated uing model for.2 µm MOS technology and SPIE imulator. The cloc aligner ha been deigned pecifically to correct preciely the duty-cycle factor in a multitage cloc buffer to (50±0.8) % within the operating frequency range from 55 MHz up to 66 MHz. Timing diagram are meaured by imulation. The propoed LL baed cloc aligner eep the ame benefit of conventional LL' uch a good abolute tability, fat-repone, and low-level put jitter for both (riing and falling) edge. Such circuit erve in many application including cloc ditribution networ within the VLSI I, high-peed AM, and coreto-core interconnect within a ytem-on-chip deign. EFEENES [] Olobdzija V., Stojanovic M., Marovic., and Nedovic N.: igital Sytem locing: High- Performance and Low-Power Apect, John Wiley & Son Pub., Hoboen, New Jerey, [2] azavi B., ed.: Phae-Locing in High- Performance Sytem: From evice to Architecture, John Wiley & Son Pub., Hoboen, New Jerey, [3] Yuan J., and Svenon.: High-Speed MOS ircuit Technique, IEEE Journal of Solid-State ircuit, vol.24, No., pp.62-70, February 989. [4] Garleep B., et al.: A Portable igital LL for High-Speed MOS loc Buffer, IEEE Journal of Solid-State ircuit, Vol. 34, No. 5, pp , May 999. [5] Moon Y., et al.: An All-Analog Multiphae LL Uing a eplica elay Line for Wide-ange Operation and Low-Jitter Performance, IEEE Journal of Solid-State ircuit, Vol. 35, No. 3, pp , March 2000.

6 [6] Fenghao M., Svenon.: Pule ontrol Loop in High-Speed MOS loc Buffer, IEEE Journal of Solid-State ircuit, Vol. 35, No. 2, pp. 34-4, February, [7] Han S.-., Liu S.-I.: A 500MHz-.25GHz Fat- Locing Pulewidth ontrol Loop with Preettable uty-ycle, IEEE Journal of Solid- State ircuit, Vol. 39, No. 3, pp , March [8] Yang P.-H., Wang J.-S.: Low Voltage Pulewidth ontrol Loop for So Application, IEEE Journal of Solid-State ircuit, Vol. 37, No. 0, pp , October [9] Liu W.- M., Huang H.- Y.: A Low-Jitter Mutual- orrelated Pulewidth ontrol Loop ircuit, IEEE Journal of Solid-State ircuit, Vol. 39, No. 8, pp , Augut [0] Kim., Kang S.: A Low-Swing loc ouble- Edge triggered Flip-Flop, IEEE Journal of Solid-State ircuit, Vol. 37, No. 5, pp , May, [] Maneati J.: Low-jitter proce-independent LL and PLL baed on elf-biaed technique, IEEE Journal of Solid-State ircuit,vol. 3, No., pp , November, 996.