Simulation and Modeling of Fractional-N sigma delta PLL for Quantisation Noise Optimisation

Transcription

1 Simulation and Modeling of Fractional-N igma delta PLL for Quantiation Noie Optimiation Appu Baby M.Tech, VLSI Deign and Embedded Sytem RV College of Engineering Bengaluru, India Dr. Kariyappa B. S. Profeor, E and C Dept. RV College of Engineering Bengaluru, India Abtract Wirele Communication ha expanded and achieved great height. It ha increaed demand for rate of data tranmiion uing low noie clock. Fractional-N frequency yntheizer i ued mot commonly in today wirele technologie. Thi paper preent imulation and modeling of fractional-n frequency yntheizer and compare architecture that optimize quantization noie. Fractional-N frequency yntheizer i derived from integral-n frequency yntheizer uing diviion control architecture uch a Error Feedback Modulator (EFM), Multi-Stage Noie Shaping (MASH) and modified verion of MASH. Reult how that fractional-n frequency yntheizer i capable of producing frequencie between 200MHz- 225MHz with a phae margin of 48. Spuriou noie i oberved at -200dBc. Keyword fractional-n frequency yntheizer, CppSim, EFM, MASH W I. INTRODUCTION irele application like GSM, FM, EDGE etc. ha limited number of band and the local ocillator(lo) ued in tranceiver are expected to achieve thee frequencie at low noie and high bandwidth. LO require panning a range of frequencie at an increment of fine reolution. It hould be capable of hopping between channel in a hort duration or at a great peed. Thi reult in high bandwidth. LO are required to meet noie requirement uch that it doe not corrupt data or interfere on adjacent channel. LO are achieved through Phae Locked Loop(PLL. Thee PLL mimic noie characteritic of crytal ocillator (reference ocillator). Integer-N frequency yntheizer i an application of PLL. It i capable of producing frequencie that are integer multiple of reference frequency. Therefore, the integer-n frequency yntheizer i limited by reolution [1]. The reolution i dependent on reference frequency and for maller reolution, reference frequency hould be reduced. Bandwidth of PLL i dependent on reference frequency. Reducing reference frequency reult in reducing bandwidth. Fractional-N frequency yntheizer decouple reolution from bandwidth [2]. Due to the demand in high data rate and exitence of more number of uer have led to need for a deign where interference and ignal-to-noie ratio are key conideration. Phae noie and puriou noie affect the deign conideration for frequency yntheizer. Minimizing phae noie and pur of the frequency yntheizer while taying within power, ize and cot contraint i a challenge for deign engineer. A behavioral model of integral-n frequency yntheizer i developed and it component are analyzed. A fractional-n yntheizer i developed from integral-n yntheizer architecture by uing an additional igma-delta modulator for diviion control. Modification in igma delta modulator i analyzed for reducing inherent pur noie. The tool ued are CppSim for behavioral imulation and PLL deign aitant tool i ued for achieving table deign parameter of integral-n PLL. Thi paper mainly deal with the behavioral imulation of fractional-n frequency yntheizer, to achieve tability, to improve jitter and pur noie and alo making ue of imple architecture for reducing area. II. DESIGN OF FRACTIONAL-N PLL Figure 1: Block Diagram of fractional-n PLL Figure 1 how block diagram of fractional-n PLL. Phae detector compare the pule edge between reference ignal (input) and feedback ignal from frequency divider. Charge pump charge the capacitor preent in low pa filter when reference ignal i leading and dicharge when input i lagging. High frequency error ignal i filtered by low pa filter. The DC output from low pa filter drive voltage controlled ocillator (VCO). Frequency divider reduce the frequency of output ignal by mod value of the frequency divider. For integral-n PLL frequency divider hold a tatic Page 16

2 mod value. In fractional-n PLL the divide value i received from diviion control unit. Diviion control unit dynamically varie the mod value of frequency divider compared to tatic value in integral-n PLL. Dynamic variation reult in achieving a fractional value due to averaging nature of low pa filter. Dynamic variation reult in increaing noie characteritic. To reduce the impact of thi noie, noie haping circuit are ued for diviion control unit. A. Modelling of Tritate Phae Frequency Detector(PFD) If the phae detector can detect phae difference more than 2π then it i called a Phae Frequency Detector(PFD). Phae frequency detector i ued to compare the phae between reference ocillator output and feedback output from VCO in PLL. Tritate PFD i a digital circuit. If the poedge of input(ref) phae lead when compared to feedback(fb) ignal it give a high voltage [3]. If the poedge of input phae lag when compared to output ignal it give a low voltage. Otherwie it remain at zero. Tritate PFD i ued a Phae frequency detector, thi mainly compoed of ub-module D- flip-flop (DFF) and logical AND gate a hown in figure 2. A DFF can be contructed from latch. Output of DFF can be obtained by calling latch function in erie and giving latch function with appropriate input. Flowchart for AND gate i hown in figure 4. The flowchart initially check previou output. Initial cae i that if previou output i low then the output tranition only when both input are not low value. At thi time output move from low to high indicated by giving tate high value and out ignal will be taking an intermediate value. If both input are in tranition output will alo be in tranition. During tranition ignal take a value between -1 and 1 which i indicated uing ignal i in tranition (T). Figure 4: Flowchart of AND gate Figure 2: Tritate PFD The input to PFD are voltage ignal of reference and feedback ignal. It compare the phae difference during the poedge tranition. The DFF can be derived from a latch. Figure 3 how flow chart of latch. B. Modeling of Charge Pump(CP) The output of phae detector i in digital tate. By uing charge pump or a current teering DAC, the input digital tate drive current to filter. Thi current charge or dicharge loop filter. The width of PFD output tate repreent the phae difference. Thi phae difference from PFD output need to be converted into analog voltage. Charge pump along with low pa filter give analog output. Thi analog output i equivalent to the phae difference between reference ignal and output ignal. Charge pump i deigned for a upply current. For a high input, it drive the current while for a low input it dicharge. By conidering upply current to be ival the output value it can have i hown in table 1. TABLE I: CHARGE PUMP OUTPUT Input(V) from PFD Output(μA) -1 -ival ival T T*ival Figure 3: Flowchart of latch C. Modelling Low Pa Filter (LPF) The loop filter convert current from charge pump to a voltage. For thi purpoe and for deriving filter equation let u Page 17

3 conider practical ytem hown in figure 5. It how a current teering DAC connected to a reitor, capacitor etup. i related to frequency. VCO can be modelled a hown in eq (5). eq (5) Figure 5: Loop filter with current teering DAC [4] Capacitor one terminal i connected to current teering DAC output or charge pump output, while another end i grounded. When up i high capacitor charge and when down i high capacitor dicharge. By ohm law the voltage acro capacitor i given by the eq (1). v v ctrl t 1 ( t) I ( ) d eq (1) 1 ctrl ( c c cp t t) I ( up( ) dw( )) d cp eq (2) In eq (2) a long a t i much greater than period or τ, it give an average value at the output. The reitor capacitor erie circuit in cacade with capacitor i the loop filter. It act a a low pa filter or average over long period. Loop filter gain can be calculated a, 1 1 H( ( R ) ( ) c c x 1 1 cr H( ( c c cc x) x 1 R c c Where 1 z and 1 cr p c R x cx c cx, eq (3) the above eq (3) can be written a 1 1 z H( ( c c x ) 1 p eq (4) Thi loop filter architecture conit of integrator and propagator in the combination of reitor(r), capacitor(c) network. The R in the RC network achieve a proportional output while C give integrator output. The above RC network act a low pa filter [4]. The output of PFD conit of DC component. Thi DC component i filtered out through low pa filter. D. Modeling of Voltage Controlled Ocillator (VCO) Voltage Controlled Ocillator i a ytem that give a pecific frequency for given input voltage. The output frequency i related to input voltage by a contant K vco. Phae eq (6) A output phae from VCO need to be modelled, phae i integral of angular frequency a hown in the below eq (7). ( t ) ( t) dt eq (7) Phae in Laplace domain i modelled in eq (8). ( ( eq (8) Subtituting eq (6) in eq (8) reult eq (9). K ( v v( eq (9) Analog component vco i modelled uing above equation. Phae equation i ued for modeling it. It can alo be oberved that an integrator i inherently preent. E. Modeling of Frequency Divider Frequency Divider reduce input ignal frequency by mod value N. It allow the high frequency ignal to be comparable frequency at the input of phae detector. Flowchart for divider i hown in figure 6. The div_val determine the number of cycle output need to be low/high. Cycle are counted when there i a tranition from low value to high value in input ignal in. State variable determine if output ignal mut be high tate or low tate. Figure 6: Flowchart for frequency divider The cloed loop gain of integral-n PLL i given in eq (10), where g( i forward path gain and 1/N i feedback path gain. Page 18

4 C( G( out eq (10) 1 ref 1 G( N For low frequencie or within loop bandwidth the above eq become C( N Therefore, out N ref Where the frequency i derivative of phae and hence, d d out ref N Fout N F eq (11) ref dt dt From the above eq (11) an integral PLL i alo frequency yntheizer or multiplier of mod N. The output of integral PLL will have a frequency N time that of reference frequency. F. Deign Parameter for integral-n PLL For a table PLL to be deigned zeroe and pole in the Laplace model mut be carefully placed. The Laplace model i a hown in figure 7. The cloed loop gain i given in eq (12). It how that it ha two pole at the origin and another pole p3, zero z. Figure 7: Laplace Model for integral-n PLL eq (12) Correponding deign parameter are given in table 2. TABLE II: DESIGN PARAMETERS FOR INTEGRAL-N PLL Deign Cae A G. Diviion Control Unit Non-Integer ratio can be achieved by dynamically witching between the divider value. For the divider value equence N+1, N, N+1, N, for thi equence diviion value obtained over a long period of time i given by eq (13). count( N)* N count( N 1)*( N 1) N count( N) count( N 1) eq (13) Four architecture are conidered for diviion control unit. Thee architecture are digital in nature a they are eay to implement. Error Feedback Modulator (EFM), Multitage Noie Shaping (MASH) 1-1 are two architecture conidered. EFM i firt order in nature while MASH i econd order. 1-1 indicate that it i compoed of firt order EFM connected in erie. Another two architecture conidered i modified verion of MASH 1-1. In one architecture, an extra PRBS tructure i ued for bringing a random nature. In the other an odd initial tate i conidered for MASH 1-1. H. Modeling of EFM EFM i firt order Digital Delta Sigma Modulator (DDSM). It conit of an accumulator and delay element. Required fractional value determine width of accumulator, number of delay element required and input to the accumulator. There are two input to accumulator a contant and feedback. Output of the accumulator i the carry out and error. Carry out in firt order implementation i ingle bit and it can have value zero and one. The divider value then can be N+C out. The flowchart given in figure 8 calculate carry out and tore in variable out while it tore the accumulator output in um. The output of delay element i um. Accumulator width i the number of bit required to repreent input. It depend on number of channel. For each channel, correponding input mut be preent. Max value i dependent on width of accumulator. When error i greater than max value, carry out i et. Accumulator width and input are the parameter that need to be determined. ω_ugb fz fp gain Icp Kvco f out f in 2.5MHz 0.5MHz 4.233MHz 8.13E E-05A 2e9Hz/V 200MHz 25MHz N 8 Figure 8: Flowchart of EFM Page 19

5 I. Modeling of MASH 1-1 MASH architecture i contructed from EFM itelf. In thi architecture two EFM will be preent. It i oberved that maximum number of tate achieved i equal to where w i the width of accumulator. According to pareval theorem more number of tate allow reduction in quantization noie due to pur. It i oberved that even input ha le number of tate and odd input i oberved to have maximum number of tate. It i a econd order architecture. It comprie of two EFM connected in erie [5]. Carry out from both EFM reult in a noie cancellation network. Output of noie cancellation network i a two-bit. Hence the frequency divider hould be able to handle four mod value. In thi cae 7,8,9 and 10. J. Modeling of MASH 1-1 with PRBS3 In the previou architecture, the number of tate increaed only by double. Number of tate i dependent on nature of input. Thi i tochatic approach where Leat Significant Bit (LSB) of input i randomly varied. The LSB i replaced by the output from three-bit PRBS generator. Hence here the number of tate MASH 1-1 goe through i not determinitic [6]. K. Modeling of MASH 1-1 with Odd Initial State (OIS) Here one of the EFM accumulator i initialized to one. For MASH, leat number of tate i oberved for even input. Previouly in MASH and EFM architecture, for a given fraction number of tate remained ame, even if accumulator width wa increaed. For MASH with OIS, very high determinitic number of tate can be achieved for higher accumulator width. Higher number of tate allow decreae in noie due to pur [8]. L. Deign Parameter for fractional-n PLL To pan frequency from 200Mhz-225MHz uing 16 channel, the frequency reolution i given by eq (14). eq (14) The parameter required to be determined are input bit length and input value for each channel. N frac =N+=N+ eq (15) eq (16) Input bit length can be determined uing eq (16). For the above pecification k or input bit length i determined to be four. Table 3 give fraction achievable when k=4 and k=11. Uing k=11 allow more reolution, the fraction uing k=4 i alo achieved and achieve more number of tate. TABLE III: INPUT FOR K=11 AND K=4 Input when k=4 Input when k= Schematic model of fractional-n PLL i hown in figure 9. Div_val_in i input to frequency divider. It i um of output from diviion control unit and mod N value. Figure 9: Schematic model for fractional-n PLL III. RESULTS A. Integral-N PLL reult CppSim i ued for behavioral imulation. Figure 10 how integral-n PLL reult. Time period T can be calculated. T= ( ) econd and frequency f i F= 1/T = 200 MHz Hence output frequency i equal to 200 MHz. Vctrl i at a tatic value zero a hown in figure 10. Uing eq (17) phae margin i calculated a = eq(17). Page 20

6 Figure 10: Integral-N PLL reult B. Analyi of Diviion Control Unit Initially all four architecture of diviion control unit are imulated for accumulator width k=4. An averaging function i ued to calculate the fraction. The reulting fraction for correponding input are hown in figure 11. It i oberved that for PRBS, abolute value are not achieved rather cloer value are achieved. LSB of input in MASH with PRBS i dithered, hence when input even i conidered it eentially dither between ix and even. Thi i the reaon average oberved i not expected value and for both ix and even ame average i oberved. While EFM, MASH and MASH with odd initial tate achieve expected fractional value for all input. Maximum tate for odd input at 32 and wort cae oberved for even with four tate. The number of tate remain ame for thee fraction even when the accumulator width i increaed. MASH with Odd Initial State (OIS) improve minimum number of tate to eight. It alo allow the fraction to improve the number of tate with increae in accumulator width. Accumulator width of eleven i conidered for improving number of tate. To achieve ame fraction for accumulator width of eleven, input need to be multiplied with 2 7. For all fraction when accumulator width i eleven, the number of tate oberved i Where a in MASH without odd initial tate, number of tate doe not improve when accumulator width i eleven. The improvement oberved i very high. Figure 12: Comparing number of tate when k=4 C. Fractional-N PLL reult The reult of fractional-n PLL whoe bandwidth i 1/10 th of reference frequency and MASH 1-1 divider modulator with odd initial tate i hown in figure 13. Input given i 896 which implie that expected frequency i MHz. From figure the freq_avg i approximately at MHz and jitter goe up to 200 pico-econd. Figure 11: Comparing fractional value input The average output i equivalent to fraction, where n 2 n i the width of accumulator. It i alo oberved that number of tate are maximum for odd input while it varie for even input. Figure 12, give the following obervation about number of tate for all input when bit length of input i four. In EFM maximum number of tate oberved for input i 16. For even input leer number of tate i oberved and wort cae i 2. The number of tate remain ame for thee fraction even when the accumulator width i increaed. Figure 13:Fractional-N PLL reult Page 21

7 D. Noie Analyi The phae noie plot for different architecture for the accumulator width of eleven and input to divider control of 512 i hown in figure 14. Uing 512 a input expected output frequency i MHz. It can be oberved that pur noie i leat in cae of PRBS and MASH with odd initial tate while highet in cae of EFM and MASH. It can alo be oberved that pur are preent but it trength i le in MASH with PRBS and odd initial tate. It i le than -200dBc. Spur are oberved at offet of more than 2MHz from center frequency in MASH with odd initial tate. Their trength i le by 200 db compared to center frequency. IV. CONCLUSION Four different diviion control architecture uch a EFM, MASH 1-1, MASH 1-1 with odd initial tate and MASH 1-1 with PRBS are conidered for achieving fractional diviion and low pur. Thee architecture are digitally implementable and unconditionally table circuit. Spur trength achieved i le than -200dBc. Lower architectural requirement i een in MASH with odd initial tate compared to PRBS. Behavioral imulation i carried out through CppSim oftware. The output frequency of integral PLL achieved i 200MHz from a 25MHz reference frequency. A diviion control module i deigned for 200MHz-225 MHz range output with 16 channel. REFERENCES Figure 14: Phae noie plot The freq_avg for all architecture are et at a hown in Table 5. It can be een that MASH with PRBS architecture perform well. Their performance i attributed to the fact that not all input combination are ued. While uing PRBS in architecture it i highly recommended to confirm that it achieve expected frequency for the required fraction. Since it a tochatic approach ometime it can vary. MASH with odd initial tate ha approximate performance to MASH with PRBS. Architecture required for MASH with odd initial tate i le compared to PRBS. Architecture TABLE IV: JITTER RESULTS average frequency(mhz) rm jitter(p EFM MASH MASH PRBS MASH IS [1] G. A. Leonov, N. V. Kuznetov, M. V. Yuldahev and R. V. Yuldahev, "Hold-In, Pull-In, and Lock-In Range of PLL Circuit: Rigorou Mathematical Definition and Limitation of Claical Theory," in IEEE Tranaction on Circuit and Sytem I: Regular Paper, vol. 62, no. 10, pp , Oct [2] Shuai Zhou, Xiaoteng Fan, Liang Liu, Panfeng He and Jiwei Fan, "A pur-reduction Delta-Sigma Modulator with efficient dithering for fractional frequency yntheizer," 2016 IEEE Advanced Information Management, Communicate, Electronic and Automation Control Conference (IMCEC), pp , Xi'an, [3] Q. Lu, H. Liu and Q. Li, "Charge pump baed PLL deign for IEEE 1394b PHY," th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, Guilin, [4] R. G. Bozomitu, V. Cehan, C. Barabaşa and N. Cojan, "A VLSI implementation of a frequency yntheizer baed on a charge pump PLL," 2014 IEEE 20th International Sympoium for Deign and Technology in Electronic Packaging (SIITME), pp , Bucharet, [5] K. Hoeini and M. P. Kennedy, Calculation of equence length in MASH digital delta igma modulator with a contant input, in Proceeding of PRIME 2007, Bordeaux, France, pp , July [6] H. Mo and M. P. Kennedy, "Maked Dithering of MASH Digital Delta-Sigma Modulator with Contant Input Uing Linear Feedback Shift Regiter," in IEEE Tranaction on Circuit and Sytem I: Regular Paper, vol. 63, no. 8, pp , Aug [7] S. Pamarti and I. Galton, LSB dithering in MASH delta-igma D/A converter, IEEE Tranaction on Circuit and Sytem I, vol. 54, no. 4, pp , Apr [8] H. Mo and M. P. Kennedy, "Influence of Initial Condition on the Fundamental Period of LFSR-Dithered MASH Digital Delta Sigma Modulator with Contant Input," in IEEE Tranaction on Circuit and Sytem II: Expre Brief, vol. 64, no. 4, pp , April [9] M. P. Kennedy, H. Mo and Y. Donnelly, "Phae noie and pur performance limit for fractional-n frequency yntheizer," th Irih Signal and Sytem Conference (ISSC), Carlow, pp. 1-6, [10] P. K. Hanumolu, M. Brownlee, K. Mayaram, and U.-K. Moon, Analyi of Charge-Pump Phae-Locked Loop, IEEE Tranaction on Circuit and Sytem, vol. 51, no. 9, pp , September Page 22