MAX3610 Synthesizer-Based Crystal Oscillator Enables Low-Cost, High-Performance Clock Sources

Transcription

1 Deign Note: HFDN-31.0 Rev.1; 04/08 MAX3610 Syntheizer-Baed Crytal Ocillator Enable Low-Cot, High-Performance Clock Source

2 MAX3610 Syntheizer-Baed Crytal Ocillator Enable Low-Cot, High-Performance Clock Source 1 Introduction The MAX3610 i a yntheizer-baed crytal ocillator IC optimized for ue in Fiber Channel (FC) torage area network application, uch a Hard Dik Drive, Hot Bu Adapter, Switch and RAID Controller. The device incorporate a fullyintegrated crytal ocillator and a frequency multiplier baed on a phae locked loop (PLL). Uing a low-cot MHz AT-cut fundamental crytal reonator, the device generate a MHz or 212.5MHz clock output with either an LVPECL or an LVDS interface. The output clock phae jitter i typically 0.7p rm in a bandwidth of 12kHz to 20MHz. Thi deign note decribe the characteritic of the MAX3610 reference clock generator, and the methodology for meauring the power upply induced determinitic jitter uing a pectrum analyzer. Meaurement reult are preented for the clock output ingle-ide-band (SSB) phae noie and the power upply induced determinitic jitter. The recommended crytal reonator parameter and the meaured frequency tability of the MAX3610 with a crytal are given in Section 4 of thi document. +3.3V 2 Crytal Ocillator with PLL Syntheizer Traditional 1Gbp and 2Gbp FC application ue a MHz crytal-baed ocillator with ingleended LVCMOS interface a a reference clock ource. A the FC erial data rate i moving toward 4.25Gbp today and probably 8.5Gbp in the next generation, ytem deigner tend to ue higher reference clock frequencie, uch a 212.5MHz with a differential LVPECL or LVDS interface, to meet the jitter requirement of the application. To achieve uch a high frequency, the traditional 3 rd overtone or 5 th overtone crytal ocillator become more expenive due to high crytal manufacturing cot. The MAX3610 provide a low-cot clock module olution by uing a fundamental AT-cut crytal reonator to generate a high-frequency, low-jitter clock output. The functional block diagram i hown in Figure. 1. FREQSET X1 X2 Crytal Ocillator MHz PFD Filter VCO M Buffer OUT+ OUT- OE N MAX3610 Figure 1. Syntheizer-baed Crytal Ocillator Deign Note HFDN 31.0 (Rev.1; 04/08) Page 2 of 6

3 With the crytal ocillation frequency f xo running at MHz, the MAX3610 output frequency f out i given by: f = f N (1) out oc N i the frequency multiplication factor, controlled by the external FREQSET pin. The control etting i given in Table I: Table 1. Output clock frequency control etting: FREQSET N Output Frequency VCC or open MHz GND MHz To optimize the SSB phae noie at the clock output, coniderable care ha been taken in deigning the MAX3610 PLL and VCO. The clock output phae noie i determined by the low-frequency crytal ocillator phae noie, Φ XO (f), the VCO phae noie, Φ VCO (f), and the PLL voltage noie, V N (f), from the phae detector and loop filter. The PLL phae model i illutrated in Figure 2, where K d i the phae detector gain, F() i the loop filter tranfer function, and K o i the on-chip VCO frequency control enitivity. V N Φ VCO Φ XO Kd F() K 0 /S Figure 2. MAX3610 PLL Phae Model By trading-off the noie contribution from Φ XO (f), V N (f) and Φ VCO (f), the MAX3610 PLL 3dB bandwidth i et at approximately 50kHz. The meaured output SSB phae noie at MHz i hown in Figure 3. The calculated phae jitter i 0.7p-rm when the phae noie i integrated from 12kHz to 20MHz. N M Φ OUT Figure 3. MAX3610 Output SSB phae noie at MHz(LVDS) Page 3 of 6

4 3 Power Supply Noie Rejection In a real ytem, power upply noie come from different ource: random noie, digital pike from witch upply or other digital circuit. Even with good upply filtering, there i till ome noie on the upply which, when injected into the active component on board, may degrade the ignal quality. Special conideration have been taken for the MAX3610 crytal ocillator gain block, PLL and VCO deign to achieve good power upply noie rejection. To characterize the power upply noie rejection for a clock ource, a inuoidal ignal i injected into the power upply, and the determinitic jitter i meaured at each ingle frequency tone. There are different kind of equipment that can be ued to perform thi meaurement, for example an ocillocope, a time interval analyzer (TIA), or a pectrum analyzer. If the amount of determinitic jitter i large enough, a bimodal ditribution can be oberved from the ocillocope hitogram, and the determinitic jitter can be meaured at the time offet of T/2 from the trigger point, where T i the period of the modulation ignal. A pectrum analyzer i ued to accurately meaure the MAX3610 clock output determinitic jitter. The meaurement etup i hown in Figure 4. Sinewave Generator 3.3V Bia-T VCC MAX3610 Figure 4. Meaurement etup for upplyinduced determinitic jitter Ocillocope HP8561E Spectrum Analyzer The inuoidal tone on the upply produce a frequency modulated output clock with a reduced modulation index f/f m, where f i the frequency deviation caued by the upply modulation ignal having a frequency f m. For a mall modulation index, the pectrum conit mainly of the carrier and two ideband ignal ited ±f m around the carrier. The magnitude of the two ideband pectral line relative to the carrier i dependent upon the modulation index. Thi in turn affect the maximum phae deviation perceived here a determinitic jitter. Thi determinitic jitter i given by: Determinitic Jitter (UIp-p) x( dbc) / DJ ( p p p ) = (2) π f out x i the ideband frequency modulation magnitude relative to the carrier magnitude. Figure 5 how the determinitic jitter in UI p-p veru x in dbc Sideband Frequency Modulation Power (dbc) Figure 5. Determinitic jitter caued by ingle tone frequency modulation A an example, if a 100kHz inuoidal ignal i injected into the power upply, and the meaured frequency modulation pectral line at (f out ±100kHz) i 50dBc relative to the carrier frequency f out, then according to Figure 5, the determinitic jitter i 2mUI p-p. Thi correpond to 18.8p p-p if the carrier frequency i MHz. Page 4 of 6

5 A another example, a inuoidal ignal with amplitude of 50mV i injected into the upply, and it frequency i wept from 5kHz to 1MHz. The meaured MAX3610 upply induced determinitic jitter can be een in Figure 6. Determinitic Jitter (p p-p) E E E E+06 Figure 6. MAX3610 upply-induced determinitic jitter 4 Crytal Reonator Selection: Figure 7 how the crytal model and the crytal connection to MAX3610. The recommended crytal reonator parameter can be found in table II. Table 2. Crytal Parameter Parameter Crytal Nominal Ocillator Frequency Shunt Capacitance (Co) Frequency (Hz) Value Fundamental AT cut MHz 2pF Figure 7. Crytal model and crytal connection to MAX3610 The crytal total load capacitance include the MAX3610 ocillation circuit input capacitance C L a well a the paraitic capacitance C p caued from the aembling/packaging of the blank crytal and the IC. It i important to place the crytal a cloe a poible to the MAX3610 to minimize the paraitic capacitance C p, o that the total load capacitance i dominated by the MAX3610 on-chip capacitor C L. The crytal erie reonant frequency f and it relation to the crytal ocillator frequency f xo i given below: and C R L C 0 f f xo XTAL C = f (1 + ) (3) 2( C + C ) 1 = 2π L C C p C p o X1 X2 C L L Crytal Ocillator MAX3610 (4) From the equation (3), we can etimate that the frequency hift due to load capacitance variation i about 20ppm/pF. The MAX3610 input capacitance C L i trimmed within ±10% of the nominal value. Co/C 280 Load capacitance Equivalent Serie Reitance (ESR) 12pF 5Ω to 40Ω Page 5 of 6

6 5 Frequency Stability When a clock module i built uing the MAX3610 die and a crytal reonator, the output clock frequency tability over temperature will be determined by the crytal temperature coefficient, a well a the load capacitor variation over temperature. The MAX3610 input capacitance variation from 0 o C to 85 o C i controlled well within 1%, which reult in le than 2ppm variation over the entire temperature range. Therefore, the clock output frequency tability i mainly determined by the crytal temperature characteritic. The MAX3610 crytal ocillator gain block characteritic have little dependence on the upply variation. Figure 8 how that the frequency varie le than 1ppm when upply voltage i changed from 3.0V to 3.6V. In addition, the MAX3610 crytal ocillation gain block ha the automatic amplitude control which maintain an almot contant AC power, conitent with the power level required for reduced crytal aging. 6 Concluion The MAX3610 provide a low cot olution for high frequency and high performance clock module. To obtain MAX3610 die ample, or for information regarding the ue of the MAX3610 for other frequencie or other application, pleae contact your local Maxim ale repreentative. Frequency Variation (ppm) Supply Voltage (V) Figure 8. MAX3610 frequency variation over upply Page 6 of 6