Available online at ScienceDirect. Procedia Technology 17 (2014 )

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1 Available online at ScienceDirect Procedia Technology 17 (014 ) Conference on Electronic, Telecommunication and Computer CETC 013 DC-DC buck converter with reduced impact Miguel Andrade a, *, Vitor Cota a,b a Intituto Superior de Engenharia de Liboa, Libon, Portugal b Intituto de Telecomunicaçõe, Libon, Portugal Abtract One of the mot contraint in DC-DC converter i the upply bouncing caued by the fat witching of power MOSFET. The purpoe of thi paper i to preent a DC-DC buck converter uing lew-rate modulator to increae the lew time of the PWM output intead the conventional output tage in order to minimize the bouncing, It doe not contitute a trivial tak. Thi paper preent preliminary reult of upply bouncing imulation made with a Slew-ate Modulator. Thee imulation reult how a very good agreement with the expected reult. 014 The Author. Publihed by Elevier Ltd. Thi i an open acce article under the CC BY-NC-ND licene ( Selection and peer-review under reponibility of ISEL Intituto Superior de Engenharia de Liboa. Peer-review under reponibility of ISEL Intituto Superior de Engenharia de Liboa, Libon, POTUGAL. Keyword: Supply bouncing; MOSFET power tranitor; Buck converter; Slew-rate modulation; CMOS technology. 1. Introduction Nowaday, the mot important electronic device that haring the day-to-day of ociety, uch a cellular phone, tablet and laptop are upplied by batterie and it require a very high autonomy. They have a lot of electronic circuit that hould be upplied with different voltage level, which i created the neceity to have circuitry capable of managing and ditributing the voltage neceary for the proper operation of the electronic device [1]. egarding the current cenario, with repect to the requirement of the new electronic device, there i a growing need for improving the overall efficiency of a ytem through the development of thee management block and power ditribution that allow the minimization of loe. Thi i accomplihed uing topologie of DC-DC converter and their control cheme, o it integration in CMOS technology bring new challenge [1]. DC-DC * Correpondence to: ISEL Intituto Superior de Engenharia de Liboa, ua Conelheiro Emídio Navarro,1, Liboa, Portugal. Tel.: (+351) ; fax: ( +351) addre: a3311@aluno.iel.pt (Miguel Andrade) The Author. Publihed by Elevier Ltd. Thi i an open acce article under the CC BY-NC-ND licene ( Peer-review under reponibility of ISEL Intituto Superior de Engenharia de Liboa, Libon, POTUGAL. doi: /j.protcy

2 79 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) converter can be realized a linear, witched-capacitor, and inductive converter that temporarily tore the energy tranferred between the input ource and the load. DC-DC converter have been developed uing increaingly improved method make them a a whole life upport ytem, which mut exhibit high power efficiency, high performance, together with a contribution ignificant reduction in area that can reduce overall ytem cot. In addition to the DC-DC converter allow generate multiple voltage level from a ingle power ource, they are ued to attenuate ripple regardle the change in load current or input voltage [6]. Typically, they ue pule width modulation, PWM, to control one or more tranitor (depending on the topology ued). The witching of the power MOSFET controlled by the PWM uually caue upply bouncing. Thi kind of phenomenon will caue noie in remaining circuit. It can be reduced uing a lew-rate modulation that allow increaing of lew time [7]. The main objective of thi paper i to preent a olution to reduce upply bouncing created by the tranitor witching of power tage of CMOS inductor-baed witch-mode DC DC converter, baed on the lew rate modulation of the ignal which attack the power gate. The lew rate modulator i preented in Section, including a timing analyi of the output ignal provided by thi modulator. The power lo model baed in [1], [], [3] i defined in Section 3. In Section 4 i howed an analyi of the efficiency of the converter veru the deign parameter, and circuit imulation reult for a V, 30mA buck converter working at a witching frequency of 100MHz, deigned with the UMC 180nm CMOS technology.. educing upply bounce in DC-DC converter Figure 1. Schematic of the triple-phae lew rate modulator [4]. The propoed work conit on a tudy of power electronic witched circuit topologie, followed for the development of a power circuit for the DC-DC buck converter with a technique to minimize the bouncing effect and baed in the deign methodology for DC-DC converter preented in [], [3]. The main objective i the tudy and development of a circuit capable to minimize the upply bouncing caued by the witching of the power tranitor. The idea preented by H. Jiao and V. Kurun in [4], [5] related activation and deactivation within block of microproceor, a a way to reduce conumption, can be applied to witched converter. It conit in lew-rate modulation technique divide in three phae. The incluion of a circuitry in addition to the non-overlap circuit which minimize thi effect, it ha very high importance a way to reduce the impact of the introduction of thi type of converter in a ytem on a chip, SoC.

3 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) Figure 1 how the triple-phae lew rate modulator preented in [4], where it poible identify the three tranitor M 1, M 5 and M 11, which are ued for tuning the lew rate of input ignal during reactivation event that occur in three ditinct phae. Thee tranitor are configured to the cut off in low level of the riing edge of the input ignal. When there i a tranition from low to V dd, the tranitor M 1 i turned on and the output ignal tart to rie till when reach the threhold voltage defined by tranitor M 4. Thi correpond to the phae 1, PH1, howed on the tranient analyi illutrated in Figure. Thi imulation wa performed for an input ignal with period of 0n. Figure. Tranient analyi detailed waveform of output ignal of the lew-rate control output tage. After that, the M 1 i placed to the cut off and the phae, PH, i tarted with M 5 turned on. In thi phae, the lew rate of output ignal i reduced a it i poible to oberve in Figure. The delay chain preented in Figure 1 allow defining the time of PH. The end of delay chain mark the third phae, PH3. In thi lat phae, the tranitor M 11 i turned on and the lew rate of output ignal i raied fater toward V dd. Figure 3. Circuit model of the power tage of a buck DC DC converter, including paraitic impedance. 3. Power lo model There are ome approache that how a circuit model developed to analyze the efficiency in function of the frequency [1], [], [3]. The propoed circuit model for the paraitic impedance of the power tage of buck converter

4 794 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) i preented in Figure 3, and it i baed on that work. However, it will be not conidered the incluion of gate driver a mentioned, with the paraitic reitor and capacitor, becaue they cannot be ued after the lew-rate modulator. Thi model will be centered jut on the tudy of the diipated energy due to conduction and witching loe in the power tage. Auming the conduction loe in the power tage are proportional to the conduction reitance of power MOSFET, P cond on I rm, and witching loe are proportional to the intrinic capacitance, P w C int f, it' poible to create a relationhip between the cutback of both type of loe. The conduction loe for the two power MOSFET (P 1 and N 1 in Figure 3) can be determined by the follow equation (1) and (), where i rmpmos and i rmnmos are the effective current that flow through the PMOS and NMOS tranitor, repectively, 0PMOS and 0NMOS are the PMOS ON-reitance per unit length, and W P1 and W N1 are the tranitor width in μm. D i the duty-cycle, I the output current, and Δi L i the current ripple in the filter inductor. where: E 0PMOS PMOS irmpmos W, 0NMOS E conduction NMOS i conduction rmnmos P1 WN1 D I i il rmpmos 3, il 1 rmnmos D I 3 (1) i () To get a fundamental undertanding of the witching loe of the power tage, it i neceary to analye the paraitic capacitance dipoal reulting from the MOSFET phyical proce ued on the deign. The witching diipated energy for the power tranitor P 1 and N 1, which compoe the power tage are given by the equation (3) and (4), where C gb0, C gd0, C g0 and C db0 are the gate-bulk, gate-drain, gate-ource overlay and drain-bulk capacitance per unit length, repectively. E E V gp C C V V C V V V C V (3) P1TOTALwitching gb0pmos g0pmos I gp gd0pmos I gp I db0pmos I C C C V C C V (4) N1TOTALwitching gb0nmos g0nmos gd0nmos gn gd0nmos db0nmos I The total power loe aociated to P 1 and N 1 repreented in Figure 3 are obtained a follow: f (5) 0PMOS PP 1TOTAL irmpmos WP1EP1TOTALwitching WP1 0NMOS PN 1TOTAL irmnmos WN1EN1TOTALwitching WN1 f (6) Chooing the tranitor width according to (7) will minimize the power loe (maximize efficiency) in the buck converter through an equilibrium between conduction and witching loe decribed on the Eq. (5) and (6), where it poible verify relationhip between the loe, width for the power tranitor and frequency. 0PMOSirmPMOS 0 NMOSirmNMOS WP1opt, WN1opt (7) f E f E P1TOTALwitching N1TOTALwitching

5 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) Simulated reult Figure 3 how the circuit diagram of the DC-DC converter. The power circuit conit in a conventional ynchronou buck configuration. Due to the focu on bouncing reduction, the prototype i implemented with a baic voltage mode PWM control and dominant pole compenation that generate corrective control ignal to maintain the output voltage contant. Thee ignal are modulated with triple-phae lew-rate modulator and it applied to the power MOSFET. The output ignal generated by lew-rate modulator i illutrated in Figure. The buck converter i being deigned to be prototyped in a twin-well UMC 0.18um CMOS proce. In thi implementation, it i aumed that the buck convert 3.3V into 1.8V with 30mA of output current, output voltage ripple (ΔV out ) le than 1% of the output voltage, inductor current ripple (ΔI L ) below 50% of output current, and the witching frequency i 100MHz. The filter component are external. L min V out Vout D i f 1 L Vout 1 D 8 L C. f For the buck DC-DC converter, the required inductor and output capacitor are determined by the equation 8 and 9, repectively, where V out i the output voltage, C i the capacitance value, and L min i the inductor minimum value [1]. The value determined for the filtering capacitor i 1.67nF, and for the filtering inductor i 545nH. With the elected component, it poible to calculate the ytem efficiency. The dc-dc converter efficiency i in mot cae a primary pecification for any deign target, becaue it i trongly dependent on the witching frequency, f. egarding (3) and (4), it verified that the value of L and C required to atify the target output voltage and current are reduced if f i increaed. The converter efficiency i given by the (10), where the P out i the output power and P buck i the power loe. 100 P out Pout P buck Uing the MATLAB tool and the equation on (7), it wa poible generate 3-D graph that correlate the power tranitor width with the witching frequency and duty-cycle. The gate width of the witche P1 and N1 for target pecification are deigned to be 660 um and 404 um, repectively, by equating the conduction lo and witching lo of the witche. However, regarding the following 3-D graph (Figure 4 and Figure 5), it oberved that the tranitor width decreae with the increaing of witching frequency. (8) (9) (10) Figure 4. NMOS tranitor width. Figure 5. PMOS tranitor width.

6 796 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) By the ue of ame analyi, in Figure 6 it illutrated the buck converter efficiency according to the witching frequency and the duty-cycle. The calculated efficiency i 80.8% for a converion from 3.3V to 1.8V with 30mA of output current, at a 100MHz witching frequency. Figure 6. Buck converter efficiency. Figure 6 how the effect of different value of witching frequency on the converter power efficiency where it poible to ee that the capacitive loe dominate at higher witching frequencie. A can be een the maximum efficiency i achieved when the frequency i about 5 MHz (more than frequency 5 MHz) after thi frequency the efficiency i decreaed due to higher capacitive loe in the output power tage. From the ame figure it poible to conclude that the duty cycle variation on the buck converter have low influence on the buck DC-DC converter power efficiency. An output voltage tranient analyi of the buck converter i howed in Figure 7 belong to the circuit preented in Figure 3, wherea can be een the voltage drop acro the load and the converter output tabilize for 1.8V at 300n. However, thi value i not final, the work till under progre. Figure 8 how the output voltage ripple waveform of DC/DC buck converter circuit under following condition (uing type I compenation network); V in = 3.3V, V ref = 1V, L = 545nH, C L = 1.67nF, load = 60Ω and witching frequency f = 100MHz. The imulated ripple of output voltage i 10mV. Thi value i le than the theoretical value of 18mV, which i 1% of output voltage. Figure 9 how the tranient repone of inductor peak-to-peak current ripple (Δi L ) and the load current which i equal to average of Δi L, 30mA. Figure 7. Output voltage tranient analyi of the buck converter.

7 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) Figure 8. Output voltage ripple tranient analyi of the buck converter. Figure 9. Inductor peak-to-peak current ripple (Δi L) tranient analyi of the buck converter. In Figure 10 it repreented the tranient repone reult, validating the upply bouncing reduction from 800mV to 50mV by applying the lew rate modulation technique that correpond to 65% of upply bouncing reduction, when compared with buck DC-DC converter with a conventional output tage. However, thi value i a preliminary reult becaue the work till under progre. Figure 10. Tranient analyi detailed waveform of VDD with (a) the conventional output tage, and (b) the lew-rate control output tage, repectively. Concerning to the total power delivered to the load i 53.mW at maximum current, and the power upplied i 71mW, thi mean that the obtained efficiency i around the 75%. 5. Concluion In general, the upply bouncing caued by the fat witching of power MOSFET the converter contitute a big problem during the deign phae. Thi kind of iue will caue noie in all circuit that compoe the DC-DC converter. To capitalie on the full advantage of the high frequency witching and low upply bouncing, a lew rate modulator integrated on the converter control ha been propoed and imulation reult how that the propoed

8 798 Miguel Andrade and Vitor Cota / Procedia Technology 17 ( 014 ) topology ha 65% of upply bouncing reduction when compared with the conventional topology compoed by driver circuit. Thee preliminary reult how a very good agreement with the upply bouncing reduction. The upply bouncing i ignificantly reduced by uing the triple-phae lew-rate modulator tage intead of the conventional deign. A prototype of the 100 MHz converter i being deigned to be prototyped in a twin-well UMC 0.18um CMOS proce. Only the paive component like L=545nH and C=1.67nF will be off-chip. Simulation reult how that, a maximum of 80% power efficiency i achieved, however thi value i preliminary. By imulation, the converter ha an output ripple i 10 mv with an output capacitor of 1.67nF. Table 1 how a comparion with a previouly reported work [7]. Thi deign [7] ha imilar input-output rating can be compared directly with thi work. The propoed DC-DC buck converter how a upply bouncing of 65% even at 100 MHz wherea [7] ha only 40% at 500 khz. Table 1. Comparion between buck converter with upply bouncing olution. eference [7] 011 Simulation on thi work Switching frequency 500kHz 100MHz Input range 3.3V 3.3V Output voltage 1.8V 1.8V Output current 700mA 30mA Supply bouncing reduction 40% 65% Efficiency - 75% Area.3mm - Proce 0.35um 0.18um The focu of thi work i the upply bouncing reduction. All reult preented on thi paper are preliminary. Thi deign work i ongoing. eference [1] Kurun, V., Narendra, S. G., De, V. K., & Friedman, E. G. (Jun 003). Analyi of Buck Converter for On-Chip Integration With a Dual Supply Voltage Microproceor. IEEE Tranaction on Very Large Scale Integration (VLSI) Sytem, 11, [] Cota, V. M. (010). Converore CC-CC de Alta Frequência para Sytem-On-Chip (SoC). Ph.D. thei, Intituto Superior Técnico, Liboa. [3] Cota, V., Santo, P. M., & Borge, B. (01). A deign methodology for integrated inductor-baed DC DC converter. Microelectronic Journal, 43, [4] Jiao, H., & Kurun, V. (Mar 013). eactivation Noie Suppreion with Sleep Signal Slew ate Modulation in MTCMOS Circuit. IEEE Tranaction on Very Large Scale Integration (VLSI) Sytem, 1, [5] Jiao, H., & Kurun, V. (Apr 01). Threhold Voltage Tuning for Fater Activation with Lower Noie in Tri-Mode MTCMOS Circuit. IEEE Tranaction on Very Large Scale Integration (VLSI) Sytem, 0, [6] Kazimierczuk, M. K. (008). Pule-width Modulated DC DC Power Converter (1t ed.). Dayton, Ohio, USA: John Wiley & Son, Ltd. [7] Liu, J.-M., Huang, Y.-C., Ying, Y.-C., & Kuo, T.-H. (011). Slew-ate Controlled Output Stage for Switching DC-DC Converter. IEEE International Conference on IC Deign & Technology (ICICDT), pp. 1-4, May -4, 011. [NSC99-18-E ].