Paralleling Electrolytic and Ceramic Capacitors Perks Up POL Transient Response

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1 ISSUE: March 0 Paralleling Electrolytic and eramic apacitor Perk Up PO Tranient epone by Timothy Hegarty, National Semiconductor, Tucon, Ariz. The ditributed power upply architecture, pervaive in myriad application including communication infratructure equipment and computing ytem, ue an intermediate bu and multiple downtream dc-dc regulator dedicated and proximate to each point-of-load. The ASI, FPGA, and microproceor that comprie thee load have upply voltage requirement whoe level are decreaing on an abolute bai and whoe tolerance band are decreaing on a percentage bai. Thi trend i compounded in the face of rapidly increaing upply current amplitude and lew rate demand, and it become imperative to undertand the effect of load-current tranient demand in the context of the tatic and dynamic regulation voltage contraint. The hallmark of point-of-load (PO) dc-dc regulator are efficiency, load tranient repone, and cot. The ingle-phae ynchronou buck converter [,] ha proven over time to be the definitive, preferred and univerally-ued PO topology with -Vdc bu voltage and low to medium load current (up to 5 A). Ordinarily, the PO regulator output capacitor energy tore combined with it control loop repone are precribed to maintain the integrity of the output voltage within both the tatic and tranient tolerance margin. Two limitation are materially apparent: the output capacitor and the control loop bandwidth. The uual boundarie retricting the output capacitor in power management application are driven by finite available pc-board area, component footprint and profile pecification, and cot. The capacitor paraitic equivalent erie reitance (ES) and equivalent erie inductance (ES) take increaing precedence in haping the regulator load tranient repone a the output current ramp amplitude and lew rate increae. The econd limitation relate to the witching frequencie of PO regulator, typically ranging from 50 khz to 750 khz and limited by, for example, exceive frequency-proportional witching loe (epecially at high output current), thermal limitation or EMI concern. A a conequence, the control-loop bandwidth, normally contrained to 0% of the witching frequency when conventional fixed-frequency linear control cheme are employed, i relatively low. For example, a PO regulator witching at 300 khz ha a modet maximum practical loop bandwidth of jut 60 khz. That aid, it worthwhile to obtain ome perpective not only on PO tep-load tranient behavior, but alo it dependence on the output filter capacitance. In thi article, we ll explore the rationale of paralleling capacitor of diimilar chemitrie yet complementary performance. The load tranient waveform will be reported uing time-domain imulation, allowing examination of the key indice of load tranient performance peak deviation and ettling time. atly, we ll ae the implementation of a PO module baed on a commercially available PWM controller I. PO egulator Tranient epone Fig. repreent the model of a buck regulator that erve a the template for the ubequent dicuion. The three-element model of the output filter capacitor denote the ES and ES explicitly. Detailed modeling of the temperature and frequency dependence of the variou capacitor element or the dielectric leakage loe i uperfluou to thi dicuion. 0 HowPower. All right reerved. Page of

2 Fig.. Single-phae dc-dc ynchronou buck regulator model. The reitive paraitic component of the filter inductor dcr, power MOSFET DS(on), and PB trace and connection reitance b of the power delivery path are alo hown in Fig.. To the extent that it effect i far above the frequency range of interet, paraitic inductance in the power path, denoted by b, i uually overlooked. Thi i epecially true if numerou mall capacitor are connected immediately adjacent to the load, for example in the ocket cavity of a microproceor. A time-varying current ource i o (t) i ued to model the load. Note that the remote ening point of the output voltage V o i purpoely located on the load ide of the bu reitance b. Fig. conceptually illutrate the relevant current waveform during both load tepup and tepdown tranition. A hown, the large-ignal lew rate of the inductor current i limited a the inductor current ramp to match the new load-current level following a load tranient. Thi lew-rate limiting exacerbate the deficit of charge in the output capacitor, which mut be replenihed a rapidly a poible during and after the load-on tranient. Similarly, during and after a load-off tranient, the lew rate limiting of the inductor current add to the urplu of charge in the output capacitor that need to be depleted a quickly a poible. Fig.. onceptual repreentation of the load tranient repone illutrating urplu or deficit of charge in the output capacitor. 0 HowPower. All right reerved. Page of

3 In a typical PO application of -V input to low output voltage (ay. V), it mut be emphaized that the load-off tranient repreent wort-cae. Here, the teady-tate duty cycle i approximately 0% and the largeignal inductor current lew rate when the duty cycle collape to zero (u 0 in Fig. ) i approximately Vo/. ompared to a load-on tranient, the inductor current take much longer to tranition to the required level. The urplu of charge in the output capacitor caue the output voltage to ignificantly overhoot. In fact, to deplete thi exce charge from the output capacitor a quickly a poible, the inductor current mut ramp below it nominal level following the load tep. In thi cenario, a large output capacitance can be advantageouly employed to aborb the exce charge and rein in the voltage overhoot. Alo, the location in the PWM cycle where the tranient occur i important: wort-cae for a load-off tranient i at the end of the PWM cycle when inductor current i at it peak (a illutrated in Fig..) Polymer Electrolytic apacitor The ue of a highly conductive olid polymer electrolyte in place of the more common liquid electrolyte in aluminum and tantalum electrolytic capacitor reult in greatly improved electrical propertie: reduced ES, higher ripple-current rating and extended MTBF and operational life. The electrolyte act a the electrical connection between the negative cathode and the dielectric. The development of better electrolyte ha primarily focued on reducing the ES and increaing the ripple current rating by uing higher conductivity material. Improving the capacitor' electrical characteritic over temperature (pecifically at low temperature) and auaging concern related to afety with more benign failure mode and uppreion of combution have alo driven &D in electrolyte. Polymer electrolytic capacitor, like their wet electrolyte counterpart, are polarized with the polarity bar normally deignating the poitive terminal. ow ES and high capacitance are the major deign benefit of polymer electrolytic capacitor facilitating reduced board pace becaue of the ability to replace numerou multi-layer ceramic capacitor (M) with jut one, high-capacitance poly device. Thee feature further enable excellent noie uppreion, ripple aborption and decoupling abilitie. In addition, polymer electrolytic offer capacitance tability at high operating frequencie and with applied voltage and high temperature. at but not leat, the cot per unit capacitance of polymer device i typically more favorable than ceramic. Given the demand for low component profile, everal capacitor manufacturer provide polymer capacitor in SMT rein-molded cae package, including but not limited to: Sanyo POSAP, e.g. TPF erie [3] Panaonic SP-ap, e.g. X, SX erie Murata EAS erie Kemet KO-AP, e.g. T530 erie ubycon P-ON, e.g. SX erie NE Tokin Neoapacitor, e.g. PSG erie NI omponent, e.g. NSP erie and ornell Dubilier, e.g. SPA erie. Paralleling Electrolytic And eramic A polymer electrolytic capacitor in parallel with a multi-layer ceramic capacitor i hown in Fig. 3. The frequency repone of each capacitor i complementary and accretive uch that each capacitor provide deirable performance over a certain portion of the frequency range of interet. While the ceramic provide excellent midand high-frequency decoupling characteritic with it low ES and ES to minimize witching frequency output ripple, the polymer device with it large bulk capacitance provide low-frequency energy torage to cope with load-tranient demand. 0 HowPower. All right reerved. Page 3 of

4 0 HowPower. All right reerved. Page 4 of Fig. 3. Paralleling ceramic and polymer electrolytic capacitor provide complementary performance over a broad frequency range. The complex impedance function of the output filter tructure in Fig. 3 i given by ( )( ) ( ) ( ) ( ) () () (). () The magnitude and phae of the impedance of the output filter capacitor bank i given by ( ) ( ),,, () where () () () () () () () () () X X X X X ()

5 () () () ( () ()) tan X () tan X () tan X () X (). (3) The effective ES and capacitance at a particular angular frequency, ω, are expreed a ES eff ( ω) e( ( jω) ) ( jω) co( ( jω) ) oeff ( ω) ω Im ( ( jω) ) ω ( jω) in( ( jω) ). (4) The total current ditribute in each capacitor depending on the relative impedance of each capacitor at a given frequency and can be found uing the current-divider rule. The capacitor voltage ripple, v(t), i found by taking the FFT of the triangular capacitor current waveform, i(t), convolving it with the complex impedance function of the output filter network and then performing an invere FFT to yield the time-domain waveform. A brick-wall filter function can be applied to the FFT to act a an anti-alia filter above, for example, nine harmonic of the fundamental. Practical choice of capacitor to invetigate in more detail are decribed a follow; the relevant pecification and rating are outlined in Table [3,4]. TDK 00-µF X5 6.3-V 06 multilayer cla-ii ceramic capacitor [4]. Fine ceramic material layer are intered with highly accurate internal electrode material lamination. apacitance derate ignificantly with applied dc bia (large capacitance voltage coefficient). ES i very low. Suceptible to the piezoelectric effect. Sanyo 70-µF POSAP [3] TPSF erie B cae capacitor with conductive polymer electrolyte and tantalum dioxide dielectric. Face-down contruction i provided to facilitate low ES. Multi-anode contruction and high-conductivity electrolyte provide low ES. apacitance and ES are relatively table over the operating voltage and temperature range. Allowable MS ripple current i limited by ES power diipation and, importantly, operating temperature. Table. Polymer electrolytic and ceramic capacitor parameter and pecification [3,4]. apacitor Vendor TDK SANYO Vendor P/N 36X50J07M TPSF70M9G Family la-ii eramic POSAP Polymer Electrolytic apacitor Dielectric BaTi03 Tantalum-oxide film Voltage ating 6.3 V V urrent ating Temperature ating Package Size 4 Arm at 500 khz 0 temp. rie -55 to 85 (X5 ±5%) 3. x.6 x.6 mm (EIA 06).4 Arm at to 500 khz -55 to x.8 x.9 mm (B) o 00 µf ±0% 70 µf ±0% ES mω at 300 khz 6 mω (typ.) 9 mω (max) at 300 khz ES 0.5 nh 0.7 nh Etimated ot (EAU 0 million pc) $0.30 (MOQ k/reel) $0.3 (MOQ k/reel) 0 HowPower. All right reerved. Page 5 of

6 Uing equation () through (3), Fig. 4 and 5 plot the impedance magnitude and phae of the TDK and Sanyo capacitor and the ame parameter when both component are in parallel. 0 TDK eramic 00µF SANYO POSAP 70µF eramic & POSAP in parallel apacitor Impedance Magnitude (Ω) Frequency (MHz) Fig. 4. Output capacitor impedance magnitude v. frequency plot. 90 TDK eramic 00µF SANYO POSAP 70µF eramic & POSAP in parallel 45 apacitor Impedance Phae ( ) Frequency (MHz) Fig. 5. Output capacitor phae v. frequency plot. Tantamount to the lower impedance in the low-frequency range (below 00 khz) i the large bulk capacitance of the POSAP. The low ES and ES of the ceramic optimize the impedance characteritic between 00 khz and MHz wherea the impedance above MHz i effectively the component ES in parallel. To ait with the control-loop compenation, the equivalent ES zero frequency occur when the phae i -45 and the real and reactive impedance component are equal. Uing equation (4), the effective ES i plotted veru frequency in Fig HowPower. All right reerved. Page 6 of

7 Fig. 6. Effective ES v. frequency. Simulation With the circuit operating condition and key component value lited in Table, a SIMPIS circuit imulation i preented in Fig. 7 to inpect the output-voltage tranient-repone characteritic. Table. Specification and nominal value of the PO imulation. ine and oad ondition V in V I o 5 A I o 5 A Slew ate I out 5 A/µ Power-Stage omponent DSon(HS) 5 mω 0.68 µh DSon(S).5 mω dcr 5 mω 90 µf mω 0.5 nh 70 µf 9 mω (max.) 0.7 nh PWM-ontroller Parameter f c 55 khz Type-III voltage-mode compenation Static and Dynamic egulation equirement V out 0.9 V V out(max) 0. V f 300 khz 0 HowPower. All right reerved. Page 7 of

8 Fig. 7. M740-baed buck converter tranient analyi imulation chematic. oad-on and load-off tranient repone are obtained with current lew rate of 5 A/µ. Uing type-iii voltage-mode loop compenation with the croover frequency et at 50 khz, the reult are plotted in Fig. 8. Two output-capacitor configuration are imulated: out #: out #: one 70-µF SANYO POSAP in parallel with one 00-µF TDK ceramic; two 00-µF TDK ceramic in parallel. Fig. 8. Simulated 0-A load-tep tranient repone with two output-capacitor configuration. 0 HowPower. All right reerved. Page 8 of

9 Interetingly, the total capacitor olution footprint i imilar in both cae. A indicated in Table, the ceramic capacitance i derated by 0% on the bai of it capacitance voltage coefficient at 0.9 Vdc bia. Fig. 7 and 8 how the imulation chematic and tranient repone reult, repectively. The loop bandwidth i held approximately contant by changing compenation reitor c in Fig. 7 from 30 kω to 5 kω, hence enuring imilar loop performance with both capacitor configuration. It i evident from Fig. 8 that the paralleled POSAP and ceramic of configuration # provide better performance (ee red voltage trace) with approximately 40 mv and 65 mv reduction in peak deviation during the load-on and load-off tep, repectively. In percentage term, thoe reduction in peak deviation equate to a 30% and a 40% improvement, repectively. During the load-off tranient, the duty cycle become aturated at zero and the open-loop output impedance, plotted in Fig. 9, determine the repone. Implicit with the lower output peak deviation of the POSAP configuration i that the open-loop output impedance between khz and 00 khz in Fig.9 i lower (by a much a 9 dbω) relative to the arrangement with two ceramic. Fig. 9. Simulated open- and cloed-loop output impedance plot with two output capacitor configuration. PO Module Implementation et ue the quantitative information captured up to now and conider a deign and implementation baed on the parameter of Table. The double-ided PB of an M740[]-baed PO regulator i hown in Fig. 0. Thi module provide high current and power denitie with dimenion of 0.85 in. x 0.73 in. x 0.4 in. To capture a multiplicity of intermediate bu rail, a wide input voltage range of 3 V to 0 V i available. 0 HowPower. All right reerved. Page 9 of

10 Fig. 0. A PO module implementation baed on the M740 buck controller PB top and bottom ide. The cope hot of load tranient repone in Fig. demontrate the lower peak deviation attainable with the POSAP capacitor configuration, albeit with lightly longer ettling time. There i ome ubjectivity related to when the ocillocope i triggered a the load-off peak deviation varie omewhat depending on where in the witching cycle the tranient occur. The voltage waveform in Fig. repreent the repone when the tranient occur midway through the witching cycle (i.e. when the inductor current approximately equal the load current). Fig.. Meaured PO module 0-A load tep tranient repone with two output capacitor implementation. 0 HowPower. All right reerved. Page 0 of

11 eference. National Semiconductor, M740 High Performance Synchronou Buck ontroller with D urrent Sening from the PowerWie Family, National Semiconductor, M5 High Performance 5-A Synchronou Buck egulator from the PowerWie Family, 3. Sanyo Electric apacitor General atalog 00-7, omponent/posap. 4. TDK SEAT eramic apacitor Technical Guide, About the Author Timothy Hegarty i a principal application engineer at the National Semiconductor deign center at Tucon, Ariz. He received the B.E.(Elec.) and M.Eng.Sc degree in Electrical Engineering from Univerity ollege ork, Ireland in 995 and 997, repectively. Prior to joining National, he worked for Arteyn Technologie deigning iolated board-mounted brick converter. Hi area of interet are integrated PWM witching regulator and controller, DO, reference, hot-wap controller, renewable energy ytem, and ytem-level imulation of ame. For more on tranient repone of point-of-load regulator, ee the HowPower Deign Guide, elect the Advanced Search option, go to Search by Deign Guide ategory, and elect Tranient epone in the Deign Area category. 0 HowPower. All right reerved. Page of