Fast Thermal Cycling Stress and Degradation in Multilayer Interconnects

Transcription

1 Fat Thermal Cycling Stre and Degradation in Multilayer Interconnect H.V. Nguyen 1, C. Salm 1, J. Vroemen 2, J. Voet 2, B. Krabbenborg 2 J. Bichop 2, A. J. Mouthaan 1 and F. G. Kuper 1,2 1 Univerity of Twente, MESA Reearch Intitute/ Faculty of Electrical Engineering P.O. Box. 217, 75 AE Enchede The Netherland Phone: +31 () Fax: +31 () Philip Semiconductor, Nijmegen H.V.Nguyen@el.utwente.nl Abtract- The thermal cycling tre method i popularly ued to tudy the thermal mechanical effect on metallization film in VLSI application, pecially in interconnect ytem of power IC. The fat thermal cycling tre method reported in thi paper ha everal advantage compared with uing a conventional oven for thermal tre. A pecial tet chip i deigned to demontrate the application of thi method. A diode in the tet chip play a part a temperature enor. The diode thermal coefficient i determined to be 1.8mV/ O C. The firt experiment of temperature cycling tre i done with temperature ranging to be from 46 to 286 o C ( T of 24 o C). The failure analyi i done by SEM equipment with Backcatter Electron (BSE) detector. The reult how the mechanim oberved that the failure mechanim i quite imilar with temperature cycling tre uing a conventional oven. Keyword- Thermal cycling; multilayer interconnect; chip temperature meaurement; SEM; BSE I. INTRODUCTION In recent year, increaing failure rate during temperature cycling are noted due to the increaed power pecification. Temperature cycling i one of the main factor that create tre cracking in paivation and metal layer [1]. The mechanim of fatigue failure i mainly due to mechanical tre caued by temperature cycling [2]. However, a very fat thermal tranient experiment to mimic temperature cycling of operational condition cannot be carried out uing an oven. The tet condition in an oven i far from the real operation of power IC, which work at very high frequency. Thi paper preent a method to tudy fat temperature cycling without uing an oven. It i ueful to tudy interconnect ytem for power IC under more realitic to temperature cycling condition. The exact temperature in the chip can be meaured by uing a diode a temperature enor. Otherwie, it can be ued to tudy the combination of temperature cycling with electromigration. The fat thermal cycling can be ued a accelerated factor in electromigration experiment. A pecial tet tructure will be introduced to demontrate the tudy method. The detail of the experimental et-up uing thi tructure will be preented. Finally, the firt reult of fat temperature cycling will be hown. SEM verification howed that the failure and degradation of multilevel interconnect ytem caued by extruion and voiding. II. EXPERIMETAL TECHNIQUE AND RESULTS A. Decription of the Tet Chip The tet tructure i briefly howed in figure 1. There i a very large 4Ω poly-ilicon reitor jut below the die urface where a very long meandering metal level 1 (M1) i located. Thi reitor can be ued to generate a high temperature tranient. Thi temperature can be meaured with an integrated diode in the middle of the reitor. Extruion monitor in M1, between the meandering line, and in metal level 2 (M2), large plate above the whole tructure, allow detection of hort circuit due to extruion caue by thermal tranient or electromigration. A part of the very long meandering M1 reitor (about 14Ω) can be ued for electromigration teting. In thi paper we only tudy the effect of temperature. No current i applied o electromigration doe not take place. The module i encapulated in a 17 pin power package. Fig. 1. Tet chip with pecific connection. 5(6,6725, , 9 ( ( (;75,( (;75 (;75 9, ( 5 9, 727 'LRGH, GLRGH

2 B. Experiment Set-up To carry out the fat temperature cycling with tet chip a decribed above we engaged the experiment et-up a hown in figure 2. The reitor i connected to pule current ource to generate temperature peak. Thi pule current ource can change amplitude, I max and duty cycle, D. The diode i connected to a DC current ource to force the DC current to the diode. A digitalizing ocillocope i alo connected to diode to monitor the change of diode voltage due to change of temperature. 'LJLWDOL]LQJ 2V LOORV RSH 5HVLVWRU, '& Fig. 2. The cheme to force pule power for heating-up the chip and to monitor temperature cycling. C. Meaurement of Tet Chip - Diode a Temperature Sening Thi method i baed on Shocklely relation for the current, I, veru forward voltage, V, characteritic of an ideal diode. Here i only briefly introduced and detail can be found in [3]. The relation i of form: qv I = I { e 1} (1) Where, q i the elementary electron charge, k i the Boltzman contant, T i the abolute temperature, and I i the revere aturation current. I i temperature dependent and can be expreed a: Eg r I KT e (2) Where, K, r, and E g are independent of temperature. E g i energy gap. In the forward direction I>>I, equation (1) can be written a qv I = I e (3) Mot real diode follow thee relation approximately over a limited range of current and experimental reult are the bet repreented by empirical form [3],SXOVH qv nkt I = I e (4) Aumption that the diffuion current dominate, we will take the value of n to be 1. Equation (3) can be combined with equation (2) to get a relation in term of forward voltage, V a Eg kt V = + (ln I ln K r lnt ) (5) q q Thi relation how that at contant current, the forward voltage drop i almot a linear function of temperature. For mot practical purpoe thi relation can be expreed a T = A + BV (6) The contant A, and B are determined by uing iothermal calibration. The B value will be called diode thermal coefficient, α D. The chip peak temperature i can be determined by the equation below: T = T amb + V / α (7) D Where V i difference of diode voltage from ambient (room) temperature, V =V T V amb, and T amb i ambient temperature. The average temperature of chip during temperature cycling i uually calculated by equation below [4]. T = T + R * P = T + R * D P (8) avg amb th avg amb th * Where, R th i thermal reitance, P i pule power, and D i duty cycle. - Experiment To Determine Diode Thermal Coefficient The characteritic of diode in our tet chip ued in thi tudy, i how in figure 3. I F [ma] I F -V F at room temp 1E V F [mv] Fig. 3. Current veru voltage characteritic obtained from the temperature ening diode in the thermal tet chip. The data how that thi diode eentially follow the current veru forward voltage relation in equation over arrange current of about.1 to.5ma. Hence for temperature ening, thi diode mut be operated within thi range current range. In thi tudy, we elected the

3 current at.1ma. To calculate the diode thermal coefficient, the temperature and diode voltage are equentially meaured at a contant current of.1ma during the iothermal tep by uing a oven. Thee meaurement are done uing a computer controlled data acquiition ytem. The reult are hown in figure 4 for different iothermal tep. The time of an each iothermal tep of 1 hour i long enough to table temperature. It thank to the very high temperature tability of equipment (about.2 o C), the diode voltage and temperature meaured are almot table. To find the diode thermal coefficient we take the average value of diode voltage and temperature at each iothermal tep. They are fitted uing the leat quare linear fit. The reult i hown in figure Temp Profile 25 Normally, the thermal reitance i calculated by equation below [4] T R th = (9) P Where P i power, R th i thermal reitance, and T i a difference of temperature comparing with ambient temperature. The thermal reitance of our chip i calculated a follow. The different power are applied on the reitor, and each power induced a different T. After applying the power, we waited for 1/2 hour, and then meaured the voltage of diode by applying a current 1µA. From the change of diode voltage comparing with ambient temperature, the T i calculated baing on equation (8). The data of T and power P are fitted uing the leat quare linear fit to find R th. The reult are howed in figure 6. [V] Time [minute] Diode Voltage Fig. 4. Temperature tep and diode voltage are equentially meaured T [ o C] T[ o C] Experimental data Linear fit P [W] R Th =9.8 [ o C/W] [V] =A+B*T A= /-.49 B= / α Diode : 1.83 mv/ o C T [ o C] Experimetal Data Linear Fit Fig.5. Calibration data for the diode (at.1 ma current) fitted to a linear curve. The diode thermal coefficient obtained to be 1.83mV/ o C. The approximation of linear fit i good enough, becaue the tandard deviation i only about.6mv/ o C. -Thermal Reitance Meaurement Equation (8) how that in order to calculate the average temperature, we need to know the thermal reitance. Fig. 6. The curve fit to find the thermal reitance R th D. Fat Temperature Cycling Experiment and Reult - Experimental Detail The experimental et-up a hown in figure 3 i ued to carry out temperature cycling tre with T, period, and duty cycle to be repective 24 o C, 1m, and 1%. Figure 7 how the diode voltage waveform and reitor voltage waveform (from 4Ω reitor to heat up the chip) by uing the digitalizing ocillocope. The peak temperature (T max, T min ), and average temperature, T avg are calculated from diode voltage which are hown in table I. TABLE I T min [ o C] T max [ o C] T[ o C] T avg [ o C] The tranient temperature profile and power pule are calculated from diode voltage waveform and reitor voltage waveform (4Ω poly-ilicon reitor to heat up the chip) a qualitatively hown in figure 8.

4 Diode Voltage (a) (b) Fig. 9. BSE image of M2, (a) the tre device, (b) the virgin device. Reitor Voltage Fig.7. The changing of diode voltage due to the changing of temperature, and applying pule voltage for the reitor heating up to get T of 24 o C. T[ o C] Temp Profile Power Pule Time [] Fig. 8. Tranient thermal repone for a ingle power pule. -Oberving Failure and Degradation of Metal Sytem Four chip were treed for 2 hour. We found that they all were already failure due to the extruion in metal level 2 a well a from metal level 2 to metal level 1. Thi time tre i only roughly elected. The detail lifetime of thi tet chip will be dicued with another paper when are experiment will be finihed. The device were unpackaged, the paivation layer and the top metallization layer (M2) are completely removed. Then the interlayer dielectric (ILD) i etched uing plama etcher with end-point detection. The ILD i etched until 2nm left. The urface of M1 i inpected uing SEM equipment with a Backcatter Electron (BSE) detector. The detail of thi method can be found elewhere[5]. Thi method i better than in cae the ILD i completely removed a the commonly ued method SEM, becaue the void were oberved without influence of etching ilicon precipitate P[W] (a) (b) Fig. 1. The cro-ection by FIB; (a) the tre device, (b) the virgin device. M2 M1 Extruion Fig. 11. The cro-ection by mechanical polih howing the extruion from M1 to M2. The cro-ection by FIB alo how voiding in both M1 and M2. To look for the extruion from M1 to M2, the cro-ection i made by mechanical polih and i inpected by SEM. The ILD i etched from cro-ection away about ome micrometer before SEM inpection. The SEM image of the cro-ection i hown in figure 11. III. DISCUSSION The temperature tre method preented above can ued to tudy thermal cycling tre very flexibly. However, we cannot get very big T comparing with uing conventional oven becaue the T min cannot get a miue temperature value like uing oven. The advantage of thi method comparing with oven tre that, it can get much higher number of cycle in a hot time, and the tre condition i cloer by operation condition of power IC. Literature experimental data preented that the failure of thin film by temperature cycling could be fitted to Coffin-Manon law a below [2];

5 m α (1) N f ( T) Where N f i the lifetime in cycle, T i the temperature range, and m i the exponent determined experimentally. From (1) we can ee that when T i mall reulted N f i very high. In thi method, although the T i mall, a very large number of cycle can be gotten in a hort time. Therefore, the teting time did not lat for a long time. The tet chip decribed above i ued to carry out the fat thermal cycling experiment of multilayer interconnect. Otherwie, it can be ued to carry out electromigration experiment with acceleration of temperature cycling. In thi tet chip, the diode i ued a temperature enor with enitivity much higher than uing a reitor, becaue thermal coefficient of a diode (1.8mV/ o C in thi tet chip) i higher than that of reitor (<.5mV/ C, normally). BSE image and FIB cro-ection howed a lot of voiding a well a extruion in M1 by fat thermal cycling, the extruion eem to be due to crack growth. The cro-ection in figure 11 howed the extruion from M1 to M2 due to cracking of IDL. Alo M1 to M1 ha been oberved. The failure mechanim of temperature cycling can be conidered fatigue failure; in which crack i a part of fatigue failure[2]. The failure mechanim in thi tudy i found to be imilar with oven temperature cycling in [1,2,6,7,8]. IV. CONCLUSION The method of fat temperature cycling ha been preented to tudy the failure and degradation of interconnection ytem by thermal tre. The temperature in the chip can be meaured exactly and a million or more of cycle tre can be done with thi method in hot time, which cannot be done with uing oven for thermal tre. A pecial tet chip ha been deigned and fabricated, and it ha been uccefully ued with thi thermal tre method. Otherwie it can be ued to tudy electromigration uing temperature cycling a an accelerated factor. The failure analye by SEM of urface and cro-ection of metal film howed that the failure mechanim are quite imilar with failure metal film with uing oven for thermal tre. The reearch program did not finih yet. The thermal tre experiment of metal film uing in pecified power IC indutry product will be done with thi tet chip together with thi method. Teting Laboratory of Quality and Reliability Buine Line Video Conumer Sytem Nijmegen (Q&RI BL- Video CSN) helping with experiment et-up. The author would alo like to thank to Marco Kloppenborg and Failure Analyi Department of Q&RI BL-Video CSN for many SEM characterization. REFERENCES [1] Alan R. Cory, Improve Reliability Prediction through Reduced-Stre Temperature Cycling, 38 th Annual Proc. Int. Rel. Phy. Sym., 2, pp [2] C. F. Dunn and J. W. McPheron, Temperature Cycling Acceleration Factor for Aluminium Metallization Failure in VLSI Application, 28 th Annual Proc. Int. Rel. Phy. Sym., 199, pp [3] S.M. Sze, Phyic of Semiconductor Device, 2 nd Edition John Wiley & Son, New York, [4] T. Hopkin, C. Cognetti, R. Tiziani, Deigning With Thermal Impedance, 4 th Proc. IEEE SEMI-THERM Sym., 1988, pp [5] M. Kloppenborg, J. Vroemen, Analyi of Aliminium Void, Private communication, previouly unpublihed, Philip Semiconductor, Nijmegen, The Netherland, Sep. 2. [6] R. C. Blih, P.R. Vaney, Failure Rate Model for Film Cracking in Platic IC, 29 th Annual Proc. Int. Rel. Phy. Sym., 1991, pp [7] Richard. C. Blih, Temperature Cycling and Thermal Shock Rate Modeling, 35 th Annual Proc. Int. Rel. Phy. Sym., 1997, pp [8] Richard L. Zelenka, A Reliability Model for Interlayer Cracking During Temperature Cycling, 29 th Annual Proc. Int. Rel. Phy. Sym., 1991, pp ACKNOWLEGEMENTS Thi work i being upporting by FOM and Philip Semiconductor Njimegen. The author wih to acknowledge their aociate who contribute to the ucce of thi work. Thank go to Ahmet Bulut and Life