Analysis of Breakdown in New Stepgate Structures with Graded LDD

Transcription

1 106 Analyi of Breakdown in New Stepgate Structure with Graded LDD Roji Marjorie S Govindacharyalu PA Lal Kihore K Saveetha School of Vaavi College of CVR College of Engineering,Chennai,TN,India Engineering,Hyderabad,TS,India Engineering,Hyderabad,TS,India Summary A new tepped gate tructure with a graded LDD i preented. Thi graded LDD help to pread the electric field throughout the LDD region and thereby obtain a high breakdown voltage of 68 V. Effort were made to obtain the optimum tructure from the breakdown point of view by determining the number of LDD implantation needed, the optimum LDD doe and the optimum device length. A 2D analyi wa carried out on the variou parameter uch a the horizontal and vertical electric field pattern, the impact generation profile, generation recombination, impact generation before and after breakdown, the carrier concentration, electron and whole current denitie and the conduction current denitie of the tructure. A mathematical analyi wa alo carried out which etablihed that the breakdown phenomenon i not only by the ionization integral but the hape of the field contour alo contribute to the breakdown region and breakdown occur in the middle of the wedge haped neutral region. Key word: Stepped gate; breakdown voltage; LDMOS; LDD; carrier. 1. Introduction LDMOS device have an important role to play in mart power and RF power application [1]. LDMOS i mainly ued due to it qualitie of eae of integration, thermal tability and high input impedance at high drive current. The LDMOS i alo ued in bae tation application in RF power amplifier ince thi provide high power. They can alo be eaily fabricated with the Silicon proce and can therefore be involved in integration along with the CMOS technology. The LDMOS device work on the principle of RESURF wherein the vertical junction i depleted by the horizontal junction which in turn caue the breakdown voltage to increae [2]. Different LDMOS tructure uch a, the LDMOS with the drift region under the FOX, tepped gate tructure, the hallow trench iolation tructure and the ilicon on inulator tructure have been reported in the variou journal. Many tudie have been reported to optimize or to change the device tructure, doping profile and they are aimed at improving the breakdown voltage and on tate reitance Ron [10], [11], [12], [13], [14], [15], [16], [17], [18]. One of the important tructure i the tepped gate tructure where there i a thicker and a thinner tepped gate. The thicker tepped gate help get a higher breakdown voltage and the thinner tep over the drift region, help to get a lower on tate reitance. The tepped gate tructure which wa propoed by Der-Gao Lin, S. Larry Tu et al. [3] i a modification to the LDMOS tructure. After thi there are many development to thi tepped gate tructure. A few of thee are baed on SOI tructure. Radhakrihnan Sithanandam and M. Jagadeeh Kumar imulated [4] an extended p+ tepped gate, on thin-film ilicon-on-inulator. The hole current generated due to impact ionization i now collected from an n+p+ junction intead of an n+p junction, thu delaying the paraitic bipolar junction tranitor action. The breakdown voltage obtained in thi work i around 50 V. G. Toulon, I. Corté et al. [5] had put forth a tructure where the breakdown voltage i high but they have thick oxide everywhere and it i a complex tructure. In another work by Han Yang, Zhang Bin et al. [6], a tructure imilar to the one propoed in thi paper i ued. Their paper mainly focue on the tudy of degradation. The breakdown voltage reported in thi tructure i 30 V. Maoud Kazemy, Morteza Fathipour etal [7] had extended the work done by M. Jagadeeh Kumar and Radhakrihnan Sithanandam [4] where an extended-p+ region i formed beneath the ource. The imulation reult how a breakdown voltage of 89 V but at the cot of a complex circuit which need the implementation of two different gate and different biae. They have alo reported a breakdown voltage of 37.7 V for a normal conventional tructure. A new hetero-material tepped gate (HSG) SOI LDMOS i hown in [8], where the gate i divided into three ection - an n+ gate andwiched between two p+ gate and the gate oxide thickne increae from ource to drain. The breakdown voltage i around 60V. In another work by M. Jagadeeh Kumar et al. [9] uing a tepped gate (SG) for the InGaA LDMOS, the author were able to obtain a breakdown voltage of 60 V. Thee work were primarily concentrated on extended gate tructure. The preent work propoe a new improved tructure which i a modification of the conventional tepped gate tructure. The breakdown voltage.i optimized to 68 V which i higher than mot of the breakdown voltage reported. Thi i achieved by preading out the electric field throughout Manucript received April 5, 2017 Manucript revied April 20, 2017

2 107 the LDD region by having a graded LDD tructure. The graded LDD i implemented by a two tepped LDD implant. By employing thi modification, it wa poible to obtain a higher breakdown voltage and it demontrated an increae over the other tructure reported o far. 3. Simulation Reult and Dicuion 2. Contruction of the Structure Fig 1 how the propoed graded LDD tructure. The tructure ha a pbody, an oxide layer, a graded LDD tructure which i low doped initially followed by a region which i moderately doped and thi end with the n+ contact. The tepped gate device which ha been conidered in thi work i formed on a p-type epitaxial layer whoe concentration i 1e15 cm-3. The LDD were formed with doe of 0.05e14 cm-2 and 0.25e14 cm-2. The gate oxide i alo tepped, the thickne initially being 0.04 µm and the thicker oxide i of µm thickne. Thi tructure of two tepped LDD help in optimizing the potential and field ditribution which in turn optimize the breakdown voltage. The pbody i formed by doing a elective p implant (boron) and a diffuion tep. Thi decide the active channel of the tepped MOSFET (Fig 1). The thicker gate oxide i formed by diffuing dry Oxygen with trace HCl. Thi i followed by a photolithographic tep and the thinner gate oxide i formed next, by doing a dry oxidation again. The gate i formed next, followed by the formation of the ource and drain region. The ource and drain region are formed by doing an Arenic implant and the metallization proce follow thi. Thi complete proce reult in a device of length 11 µm. Thi device ha the ource ending at 2.2 µm from the edge of the device and the LDD tarting at 4 µm, the econd LDD and the thick oxide at 4.8 µm and the n+ contact at 9 µm. The effective length of the pbody i 3 µm. The urface concentration in the firt tep of the LDD i 1e16 cm-3 and at the econd tep it i 7e16 cm-3 a hown in Fig 1. The proce imulation oftware ATHENA i ued for imulating the tructure. The device imulation oftware ATLAS i ued in the analyi. The imulation in the breakdown region take place by the curve tracing algorithm. The Selberrherr model i ued to model the impact ionization. Fig 1. Stepped gate tructure The tructure, doe and the concentration were adjuted in order to get an optimum breakdown voltage without compromiing the on tate reitance. The tructure wa optimized by forming an LDD firt and adding the next tep to it. A few experiment were conducted to compare the breakdown voltage of a conventional LDD with that of a graded LDD. The breakdown voltage meaurement wa done by weeping the VDS from 0 V to 66 V and keeping the gate voltage contant at 0 V. The main aim i to optimize the LDD tructure with regard to the length of the device and the tructure of the device. The firt tak wa to optimize the doping profile. A few experiment were conducted by keeping the econd LDD doe contant at 3.5e14 cm-2 firt and changing the doping of the firt LDD. The breakdown voltage wa at it highet when the firt LDD doe wa at 5e12 cm-2. A econd et of experiment were conducted uing the previou tructure a a reference, by changing the doping of the econd LDD. For all thee experiment the device length wa kept contant at 11 µm. Another et of experiment were conducted, to tudy the dependence of the device on the device length by changing the length of the device and finding out the correponding breakdown voltage. 3.1 Change in Breakdown voltage with the doping of the tepped LDD tructure The reult of the et of thee experiment which are outlined in the previou ection are given in Table 1 and Fig 2.

3 108 and they range from Ω to Ω. The width of the tructure i taken a 1µm which i a tandard for Silvaco 2D imulation. 3.2 Dependence of the breakdown voltage on the device length Fig 2. Breakdown characteritic of the tepped gate tructure Table 1. Variation of breakdown voltage by keeping the econd LDD doe a cm-2 and changing the firt LDD doe. Firt LDD implant doe in cm -2 Breakdown voltage in V 5.00e e e From the Table 1. it i een that the breakdown voltage i high when the firt LDD implant doe i at 5e12 cm-2. The econd et of experiment were conducted by keeping the firt LDD implant doe at 5e12 cm-2 and changing the econd LDD implant doe. The reult are tabulated in Table 2. Table 2. Variation of breakdown voltage by keeping the firt LDD doe a 5e12 cm-2 and changing the econd LDD doe Second LDD implant doe in cm -2 Breakdown voltage in V On tate reitance in Ω 3.50e e e e e e e e The next tep in optimizing the device tructure i to find out the device length which give the bet breakdown voltage. The tructure with the highet breakdown voltage in the previou ection wa conidered and it length wa changed to analye the effect. From Table 2 it i obviou that the highet breakdown voltage i achieved when the graded LDD doe i at 2.5e13 cm-2. The change in the breakdown voltage and the on reitance with device length are given in Table 3. Table 3. Variation in breakdown voltage with device length Device length (µm) Ditance at which n+ contact tart in µm Breakdown voltage (V) Comparion of the breakdown voltage of tructure with ingle and double LDD The breakdown voltage of the tep gate tructure with a ingle LDD i compared with that of a double LDD tep to confirm the enhanced performance of the graded LDD tructure. Both the imulation were carried out for the ame device length of 11 µm. Fig 3 how the breakdown voltage curve plotted for both the tructure. From Table 2 it i een that the breakdown voltage change from 50.2 V to 65 V for a change in econd LDD implant doe from 3.50e14 cm-2 to 3.50e13 cm-2 and then decreae to 55 V when the doe i decreaed to 1.1e13 cm-2. The on tate reitance value were alo calculated

4 109 Fig 3. Breakdown voltage curve of a normal tepgate tructure and a tepgate tructure with two tepped LDD both with the ame device length. 4 Analyi 4.1 Dicuion on Change in Breakdown voltage with change in LDD doping A can be een in the earlier ection the breakdown voltage depend on the LDD doe and the channel length. To undertand thi behavior, 2D analyi of the variou parameter uch a the horizontal and vertical electric field pattern, the impact generation profile, Generation /recombination / impact generation before and after breakdown, the carrier concentration, electron and hole current denitie and the conduction current denitie of the tructure were analyzed. Thee analye were done at a voltage jut above the breakdown voltage. Firt the analyi wa done on the dependence of the breakdown voltage on the LDD doping. A can be een in Table 2 the breakdown voltage increae and then decreae for an increae in LDD doping. The analyi i carried out for three cae. The firt cae conidered here occur when the breakdown voltage i low at 50.2 V, thi occur when the graded LDD doe i at 3.5e14 cm-2 and the firt LDD doe at 5e12 cm-2 (Refer Table 2). The impact generation profile in Fig 4 how that the field free region i moving more toward the ource under the gate. The maximum vertical and horizontal electric field of -3 e5 V/cm occur around 6 µm a can be een in Fig 4.We can ee that it i cloer to the point where the LDD tart grading. It i clear from thee fact, that the depletion region i confined to a mall length or only to the firt LDD region. A a reult, the field at the tip of the field free region become high and lead to the low breakdown voltage. Fig 5. Profile of impact generation rate with econd LDD doping of 1e13 cm-2 The ame reaoning hold good for the tructure with only one LDD implant. A hown in Fig 3 the tepped gate LDMOS tructure without the graded LDD ha a breakdown voltage of V which i cloer to the breakdown voltage of the tructure with the lowet graded LDD doping. An intereting picture evolve when the graded LDD implant doe i at 2.5e13 cm-2. The breakdown voltage for thi doe i high at V. Analyi wa done on the electric field and impact generation rate and the following obervation were made. Fig 6. Profile of impact generation rate with econd LDD doping of cm-3. Fig 6 diplay the impact generation contour map for the 11 µm LDMOS device with 66 V on the drain and 0 V on the gate and the ubtrate, the back contact. The map how that cloe to n+ drain the 66 V potential contour extend below the gate away from the n+ drain region. It can be een from the hape of the contour, that there i a potential gradation between thi contant potential region and the gate. Thi contant potential region narrow down toward ource and diappear at a ditance of about 8 µm from the beginning of the device, approximately 1.2 µm from the gate edge on the drain ide. Thi kind of potential ditribution lead to formation of wedge haped neutral region in ilicon below the gate. The width of the neutral region decreae a we move away from the drain ide edge. Baed on the analyi carried out (Fig 8) it i evident that it i the vertical electric field which i dominating in thi cae. There i a high electric field region between the neutral wedge region and the gate. The breakdown voltage occur around the middle of the graded LDD a hown in Fig 7 which make the breakdown large.

5 110 Fig 7. Vertical and Horizontal Component of Electric Field along a Horizontal Line drawn jut below the urface with the firt LDD implant doe at 5e12 cm-2 and the econd LDD implant doe at 2.5e13 cm-2 The width of the neutral region cloe to the drain can be calculated by approximating the region a a MOS tructure. The MOS tructure conidered here i formed on a n type emiconductor. A negative bia i applied to the gate electrode which deplete the urface. The gate bia get divided into two portion for uch a MOS tructure - one acro the oxide layer and the other to upport the depletion region in the emiconductor. The diviion of the bia acro the oxide layer and the depletion layer can be determined from baic MOS phyic. Total bia acro the MOS tructure i given by a obtained from imulation data at ditance of 8.3 µm and 8.6 µm from the tart of the device in the LDD region are 7e16 cm-3 and 1.1e17 cm-3 repectively. Uing thee value, the Vox, V and the depletion width in the ilicon are calculated uing the above given equation. The calculated value of Vox and V are 45 V and 21 V repectively for the 7e16cm-3 (8.3 µm) and 53V and 13V repectively for 1.1e17cm-3 (8.6µm) tructure.the correponding depletion width calculated are 0.6 µm and 0.45 µm repectively. Thee match very well with thoe obtained from imulation The voltage at the tip of the region i the ame a the applied voltage on the drain. The applied voltage i ditributed, along the length of the device. The electric field in thi direction i not very high and i not primarily reponible for the breakdown of the device. Thi can be confirmed by determining dx over thi path where α i ionization coefficient and i field dependent. dx i determined in one of the unpublihed work by the ame author uing the equation given below [11]. The break down condition i et a that for which the ionization integral αdx = 1 (5) The ionization coefficient α i generally found to have the following dependence on the electric field, where i the critical Electric field.from the experimental data available in literature [11], [12], [13] the following expreion relating the ionization coefficient to the electric field ha been extracted., (1) where V i the total bia acro the tructure, Vox drop acro the oxide and V drop acro the depletion layer in the emiconductor. The drop acro the oxide i given by Q V ox = C ox (2) where Cox i the oxide capacitance per unit area and Q i the depletion charge in the emiconductor per unit area. The depletion charge can be expreed in term of the voltage drop acro the depletion region and the doping concentration in the depletion region a D D ( V Vox ) Vox Cox Q = 2 ε qn V = 2ε qn =. (3) and the width of the depletion layer can be obtained from w Q = q. N D. (4) The width of the depletion layer in the region below the gate at different place can be obtained by olving the equation (1), (2), (3) and (4).The doping concentration, (6) Thi expreion ha been ued to determine the ionization integral from the electric field data which wa obtained from the imulation of the LDMOS tructure. The breakdown in imple revere biaed diode can be modelled baed on ionization integral. The ionization coefficient (α) i a function of electric field preent and the ionization integral αdx calculated over the length of the carrier path hould become equal to unity for breakdown to occur. But the value of α extracted from the imulated tepped gate tructure in thi work i much maller than unity. Thi prove that thi imple model hold good for one dimenional tructure but in the cae of 2D tructure like the LDMOS a different approach ha to be followed. So there hould be ome other factor apart from the ionization integral which ha caued the breakdown and to find it variou 2D analye were carried out the reult of which are given below. Thi expreion ha been ued to determine the ionization integral from the electric field data which wa obtained from the imulation of the LDMOS tructure. The breakdown in imple revere biaed diode can be

6 111 modelled baed on ionization integral. The ionization coefficient (α) i a function of electric field preent and the ionization integral αdx calculated over the length of the carrier path hould become equal to unity for breakdown to occur. But the value of α extracted from the imulated tepped gate tructure in thi work i much maller than unity. Thi prove that thi imple model hold good for one dimenional tructure but in the cae of 2D tructure like the LDMOS a different approach ha to be followed. So there hould be ome other factor apart from the ionization integral which ha caued the breakdown and to find it variou 2D analye were carried out the reult of which are given below. Firt it ha been oberved during the imulation that for drain voltage cloe to the breakdown voltage the drain current and the ubtrate current are almot the ame and the ource current i very le. The picture become different jut around breakdown. A the drain voltage approache the breakdown voltage, the ource current tart increaing. At voltage very cloe to breakdown and in breakdown condition the drain current and ource current are almot equal. The ubtrate current i very mall compared to drain and ource current. Thi i een more in long channel device. Thi indicate that before the breakdown occur, the drain current i eentially due to the leakage between drain and ubtrate. However, after the breakdown a large current flow through the channel region and the ubtrate play a maller role. The following inference were made from the analyi. The firt one wa that the horizontal electric field i alway negative or in other word the field direction i toward ource. The vertical electric field i negative up to a depth of about 0.8 µm from the edge of gate and become poitive afterward. To acertain the field direction plot of electric vector were alo done and i given in Fig 8. Fig 9. Conduction current denity after breakdown in tep gate LDMOS for the 11 µm device. Near the drain it i electron conduction and near ource it i hole conduction A a reult of thee field the hole generated during the impact generation flow toward the gate and the generated electron flow downward. Thi reult in an accumulation of hole near the gate edge a i evident from Fig. 9. A i evident from Fig 8 the potential along the horizontal line i downward, toward the drain for electron. Therefore, there i a channel for the electron in the drain region in the potential well and they flow toward the drain and are collected by the drain. Due to the high electron concentration the drain current alo increae to a large value in the breakdown condition. Fig 10. Potential along the vertical line 6.36µm from the edge of the ource for the 11 µm device Figure 8. Plot of electric field vector near the drain region for the 11 µm device A i evident from Fig 8 the potential along the horizontal line i downward, toward the drain for electron. Therefore, there i a channel for the electron in the drain region in the potential well and they flow toward the drain and are collected by the drain. Due to the high electron

7 112 concentration the drain current alo increae to a large value in the breakdown condition. Referring to Fig 8 again, it can be oberved that the field direction along the channel in the region, point away from the drain point more toward the ource. Thi facilitate the hole that are created, to move toward the ource and get collected by the n+p+ ource terminal. 4.2 Dicuion on change of Breakdown length with device length The reult of change in breakdown voltage with change in device length are hown in Table 3 and Fig. 3 how that the breakdown voltage i directly dependant on the device length. The vertical electric field, in the 11 µm device i much higher than the horizontal field, epecially near the drain ide. Becaue of the horter channel length of the 9 µm device, the drain region tart much ahead. Figure 11 give net doping profile of the 11 µm and 9 µm device along the channel, at a depth of around 3 µm below the gate. The doping concentration in the LDD region at the point where the n+ drain tart for the 9 µm i lightly maller compared to that of the 11 µm device. Becaue of the horter LDD region and the lower doping concentration near n+ region, the electric field profile in thi region change and the horizontal field dominate for the 9 µm device unlike the 11 µm device. Figure 12. Electron and hole current denitie before and after breakdown along a vertical line at a ditance of 4.65µm from the edge of the ource for the 9 µm device. A in the cae of 11 µm device there i an 8 to 9 order of increae in the impact generation rate after breakdown compared to before breakdown. Similar i the ituation with carrier concentration. The current component alo increae in a imilar manner and a Figure 12 how, near the urface region the electron current dominate. Thu it can be een that the breakdown occur in a different way a the device length increae in the tepped gate LDMOS device. Analyi of the conduction current denitie were alo done for the horter channel device and it wa een that the current flow i confined to the urface in thi device. Thi i in contrat to Fig 9 which how the conduction current denitie of a 11 µm device where the current flow exit upto a depth of 0.8µm. To get a deeper inight, two more device tructure were tudied, one without a gate and the other without a tep in the gate oxide. All the other pecification were the ame a in Fig 1. The cro ection of the device without the gate i hown in Fig 13. Thi device break down at 90V. The abence of the gate tructure change the potential pattern and the field pattern. There are no high field in the vertical direction and the field pattern i ymmetrical about the p body and n LDD region. Figure 11. Net doping profile of the tep gate tructure. In both 9 µm and 11 µm device the ource edge i at 2.2 µm, the p body end at about 4 µm and the LDD region tart at thi point. The drain region for 9 µm device tart at around 7 µm, while that for 11 µm device at around 8.6 µm

8 113 Acknowledgment The author would like to thank Prof. Sathyam, Electronic and Communication Engineering Department, Vaavi Engineering College, Hyderabad for the technical dicuion which the author had with him in the analyi of the tepped gate tructure. Fig 13 Potential after breakdown in a device with no gate. The device length i 11 µm In the econd tructure where there wa no tepped oxide, the gate oxide wa uniformly formed with a thickne of 40 µm throughout the length of the device. Thi device break down at a much maller voltage (~ 28V). Thu it can be een that the preence of tepped gate oxide, LDD region and the doping profile in the LDD region determine the breakdown voltage. Optimization of thee parameter will optimize the device operation. 5. Concluion A new tepped gate tructure wa imulated and analyzed uing the proce and device imulator tool ATHENA and ATLAS repectively. A high breakdown voltage of 68 V wa obtained without compromiing on the on reitance which wa around Ω. The breakdown voltage of a graded LDD tepped gate tructure when compared with that of a normal tepped gate tructure exhibited an improvement of almot 18 V. The experiment conducted by changing the firt and the econd LDD doe to get the highet breakdown voltage howed that, the optimal firt LDD doe i 5e12 cm-2 and the econd LDD doe i 2.5e13 cm-2. The device tructure wa further optimized by conducting experiment to ee the dependence of the breakdown voltage on the device length and it can be een that, the highet breakdown voltage i achieved when the device length i at 12 µm. By analyzing the electric field vector, impact generation and the recombination, it i inferred that the recombination current alo contribute to the high drain current after breakdown, unlike imple tructure where only the ionization integral i enough to determine the breakdown. Reference [1] F. van Rij. Statu and trend of ilicon LDMOS bae tation PA technologie to go beyond 2.5 GHz application. Preented at Radio and Wirele Sympoium, IEEE, Jan [2] Appel JA, Vae HMJ, High Voltage Thin Layer Device., IEDM Tech Diget, Dec. 1979, Vol.25, pp [3] Der-Gao Lin, S. Larry Tu, Yee-Chaung See, A Novel LDMOS Structure with A Step Gate Oxide Electron Device Meeting, IEDM '95., International. [4] M. Jagadeeh Kumar and Radhakrihnan Sithanandam Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance, IEEE Tranaction on Electron Device, July. 2010, Vol. 57, No. 7. [5] G. Toulon, I. Corté, F. Morancho, Analyi and optimization of a Novel High Voltage Striped STI-LDMOS Tranitor on SOI CMOS Technology, Prague, Czech Republic., Aug. 2012, pp [6] Han Yan, Zhang Bin, Ding Koubao et.al., Hot-carrierinduced on-reitance degradation of tep gate oxide NLDMOS, Journal of Semiconductor, Dec. 2010, Vol. 32, No. 12. [7] Maoud Kazemy, Morteza Fathipour Extended-p+ Stepped Dual Gate (ESDG) LDMOS Proceeding of the 4th Iranian Conference on Electrical and Electronic Engineering, Gonabad, Iran, [8] Radhakrihnan Sithanandam and M. Jagadeeh Kumar A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Application, Proceeding of the 23rd VLSI Deign - 9th Embedded Sytem, Bangalore, India, Jan [9] M. Jagadeeh Kumar and Avikal Banal Improving the Breakdown Voltage, O N reitance and Gate charge of InGaA LDMOS Power Tranitor Semiconductor Science and Technology, Oct. 2012, Vol.27, no.10, Article No [10] Kun-Ming Chen, Performance improvement in RF LDMOS tranitor uing wider drain contact., IEEE Electr. Device Letter, Sept, 2013 Vol. 34, no.9. [11] Ming Qiao, Xi Hu, Hengjuan Wen, A Novel Subtrate- Aited RESURF Technology for Small Curvature Radiu Junction, in Proceeding 23rd International Sympoium on Power Semiconductor Device & IC', San Diego, USA, May. 2011, pp [12] Min-Hwan Kim, Jong-Jib Ki, A Low On-Reitance 700V Charge Balanced LDMOS with interected WELL tructure, in the Proceeding of 15 th International Sympoium on Power Semiconductor Device and IC (ISPSD), Cambridge, UK, Apr. 2003, pp

9 114 [13] Helmut Puchner, Sungkwon Lee, High Voltage LDMOS Tranitor Utilizing a Triple Well Structure, in Proceeding of 19 th International Sympoium on Power Semiconductor Device and IC, Jeju, Korea, May. 2007, pp [14] Yuehua Dai, Yuan Hu, Phyic-baed Modeling and Simulation of Dual Material Gate(DMG) LDMOS in Proceeding of Aia Pacific Conference on Circuit and Sytem, Singapore, Dec. 2006, pp [15] S. Merchant, R. Baird, High-Performance 13-65V Rated LDMOS Tranitor in an Advanced Smart Power Technologie, in Proc. 27th International Sympoium on Power Semiconductor Device & IC' (ISPSD), Toronto, Canada, May. 1999, pp [16] Seiki Ogura, Paul J Tang, Deign and Characteritic of the Lightly Doped Drain-Source (LDD) Inulated Gate Field-Effect Tranitor. IEEE Journal of Solid-State Circuit, Aug. 1980, Vol. 15, no. 4, pp [17] S. Roji Marjorie, P.A.Govindacharyulu, K.Lal Kihore. Studie on the dependence of breakdown voltage LDMOS device on their tructure and doping profile of LDD region., preented at Aia Pacific Conference in Pot graduate reearch in Micro Electronic and Electronic, Hyderabad, India, Dec [18] S.Roji Marjorie, P.A.Govindacharyulu, K.Lal Kihore Dependence of Breakdown Voltage and Other Device Parameter of a Novel LDMOS Structure on Drift Length. Roji Marjorie S, received her Bachelor of Engineering degree from Govt College of Engineering in She completed her M.Tech from IIT, Madra in After productive tint with variou college in Tamilnadu and Telangana, he i now with Saveetha School of Engineering, Chennai, India.