A Programmable Compensation Circuit for System-on- Chip Application

Transcription

1 JOURAL OF SEMICODUCTOR TECHOLOGY AD SCIECE, VOL., O.3, SEPTEMBER, 0 A Programmable Compenation Circuit for Sytem-on- Chip Application Woo-Chang Choi* and Jee-Youl Ryu** Abtract Thi paper preent a new programmable compenation circuit (PCC) for a Sytem-on-Chip (SoC). The PCC i integrated with 0.8-μm BiCMOS SiGe technology. It conit of RF Deign-for- Tetability (DFT) circuit, Reitor Array Bank (RAB) and digital ignal proceor (DSP). To verify performance of the PCC we built a 5-GHz low noie amplifier (LA) with an on-chip RAB uing the ame technology. Propoed circuit help it to provide DC output voltage, hence, making the RF ytem chain automatic. It automatically adjut performance of an LA with the proceor in the SoC when it goe out of the normal range of operation. The PCC alo compenate abnormal operation due to the unuual PVT (Proce, Voltage and Thermal) variation in RF circuit. Index Term Sytem-on-Chip (SoC), programmable compenation circuit (PCC), low noie amplifier I. ITRODUCTIO A recent trend in advanced wirele communication ytem i to integrate all of the radio frequency (RF) and mixed-ignal device on a ingle chip. Thi trend contribute to high denity ytem-on-chip (SoC) with higher performance and reliability. RF and mixed-ignal tet engineer and deigner in SoC field are mainly Manucript received May. 5, 0; revied Jul. 5, 0. * MEMS/AO Fabrication Center, Buan Techno-Park, Buan, Korea ** Information and Communication Engineering, Pukyong ational Univerity, Buan, Korea ryujy@pknu.ac.kr concerned with unuual proce, voltage and thermal (PVT) variation in RF circuit ince thee variation are hard to ditinguih from acceptable variation and lead to a ignificant performance lo that violate the circuit pecification [-]. Therefore, once chip are fabricated and packaged, ome ophiticated compenation technique need to be applied to adjut performance from chip with the PVT variation. In pite of the coniderable reearch underway to olve thee problem [-], the IC indutry i till eeking more uitable technique. Thi paper preent a novel low-cot alternative for RF SoC teting to adjut PVT variation. The alternative approach utilize programmable compenation circuit (PCC). The main part in propoed ytem involve RF Deign-for-Tetability (DFT) circuit and Reitor Array Bank (RAB). The RF DFT circuit help it to provide DC output voltage, hence, making the compenation ytem automatic. Propoed circuit i very ueful for concurrent RF IC in a complete RF ytem environment. II. PROGRAMMABLE COMPESATIO CIRCUIT. Compenation Circuit Configuration Fig. indicate the SoC tranceiver configuration with a programmable compenation circuit (PCC) for an RF front-end. The PCC contain RF DFT circuit, RAB and digital ignal proceor (DSP). The propoed circuit automatically adjut and compenate performance of the LA and power amplifier (PA) by the proceor when the LA and PA go out of the normal range of

2 JOURAL OF SEMICODUCTOR TECHOLOGY AD SCIECE, VOL., O.3, SEPTEMBER, 0 99 LA Mixer ADC DSP v L Peak Detector V T PCC RF DFT/ RAB LO D - D vl Band-gap Reference TA Peak Detector V T PA DAC θ =πft θ =πft Phae Detector Δθ T Fig.. SoC tranceiver configuration with a PCC. operation due to the unuual PVT. The RF DFT circuit help it to provide DC output voltage, thu, making the network automatic. Fig. how tet et-up to realize our idea hown in Fig.. Our propoed PCC provide DC output o that all of the meaurement can be done by on-chip data converter within the SoC, hence making the meaurement automatic. It contain RF circuit with RAB and RF DFT circuit all on a ingle chip. The tet tructure can be automatically configured by the external data acquiition hardware. The complete tet-bed contain RF ource (v in ) with ource reitance (R ), RF relay (S, S and S3), load impedance (Z L ), and a data converter board. The meaurement et-up contain very low-lo RF relay and input tranmiion matching to the RF and DFT circuit. The poition of the relay were controlled to meaure the output DC voltage and phae, V T, V T, and Δθ T through the DFT circuit, repectively. Thee relay were controlled by DeMux chip on external board. The RF DFT circuit contain a tet amplifier (TA), a band-gap reference circuit, two RF peak detector (PD and PD) and a RF phae detector (PHD) a hown in Fig. 3. Thi additional circuit occupie a very mall area vin R=50Ω S vl vl vl Device Under Tet RF Circuit RF DFT RAB VT VT ΔθT S D - D S3 ZL=50Ω ADC PC with program DSP Interface Board Fig.. Meaurement et-up of the PCC for an RF circuit. Fig. 3. RF DFT circuit. le than 5% on the SoC, and it help to meaure LA performance without expenive external equipment. Two RF peak detector and a RF phae detector are ued to provide DC output voltage (V T and V T ) and phae difference (Δθ T ), repectively.. Cae Study In thi paper, we tudied the teting of RF amplifier. Our RF tet trategy involve the derivation of mathematical equation for many RF device pecification. Thee mathematical equation contain DC parameter and thu provide value that are comparable to actual meaured value uing expenive RF equipment. The following ection decribe mathematical decription of thee parameter uing DC output voltage. We preent the equation for both defective and defect-free cae. A. Input Impedance The input impedance meaurement i performed with the witch S in cloed poition and the witch S in open poition from Fig.. The overall tet technique i to find any deviation between the ource impedance (R ) and the input impedance of the RF amplifier and tet amplifier. For example, the tet amplifier i deigned to find change in input impedance of the RF amplifier for any mimatch with the ource reitance. Due to the PVT variation, DC voltage and phae at the output of RF DFT may be changed. ) Cae Study I: Defect-free RF Amplifier Conider a defect-free RF amplifier with perfectly matched input impedance, i.e., 50 Ω. The theoretical value of the voltage acro the input impedance of the

3 00 WOO-CHAG CHOI et al : A PROGRAMMABLE COMPESATIO CIRCUIT FOR SYSTEM-O-CHIP APPLICATIO LA (Z ) and tet amplifier (Z ) i expreed by Z Vt = Vin. The gain of the tet amplifier (G Z + R ) i deigned to be three to ufficiently increae the output voltage wing. The DFT circuit monitor the DC voltage V T and phae difference Δθ T a hown in Fig.. Uing the meaured thee value, we can ue Eq. () to calculate the defect-free RF amplifier impedance, Z, K( RZ ) Z = [ Ω] K ( R Z ) + Z () where K i the multiplying contant obtained from the voltage gain. ) Cae Study II: Defective RF Amplifier We now conider PVT variation in RF circuit []. In thi cae, there i a certain variation in input impedance of RF amplifier due to change in it input matching condition. Thi condition provide a new value in V T and Δθ T. The input impedance of the RF amplifier in defective condition can be expreed a K( RZ ) Z = [ Ω] K ( R Z ) + Z where K i the multiplying contant obtained under defective condition. B. Other Expreion We have derived two additional mathematical equation for poible RF pecification for the RF amplifier by conidering defective and defect-free condition []. Thee mathematical equation are ummarized in Table. Table. Mathematical expreion for RF DFT circuit Parameter Defect-free Variation Input Impedance Voltage Gain oie Figure K( R Z ) Z = [ Ω] K ( R Z ) + Z R G0 + Z = G Z F = + R + Z α () K( RZ ) Z = [ Ω] K ( R Z ) + Z F R G0 + Z = G = Z + R + Z α 3. PCC Deign The propoed RF DFT circuit i hown in Fig. 4, and it i deigned uing 0.8 μm SiGe technology. It conit of TA, PD, PD and PHD circuit. The PD circuit i alo a part of the DFT circuit and it ha the ame topology a the PD circuit hown in Fig. 4(a). The tet amplifier i deigned with the input and output impedance of 50 ohm, repectively. The gain of the tet amplifier i deigned to be 3 to increae the output voltage level. The RF peak detector are ued to convert RF ignal to DC voltage. To detect phae difference (Δθ T ) an RF phae detector are ued. The output minimum voltage of phae detector provide 30 mv for phae difference of 80. The output maximum voltage of phae detector provide.8 V for phae difference of 0. When θ = θ ± 90, phae center point i 900 mv. The output current drive for ource/ink condition i 6 ma, and lew rate i 50 V/μ. The mall ignal envelope bandwidth i 30 MHz, and the repone time for 5 change condition (0% 90%) i 0 n. The bia tage utilize a band-gap reference circuit for a low-upply voltage and a low-power diipation. The inductor (L c0 ) i ued for matching input and output impedance. The bia reitor (R 05 and R 06 ) hown in Fig. 4 are ued to keep tranitor Q 04 in the active region o that the tranitor act a a rectifier. The diode connection have the advantage of keeping the bae-collector junction at zero bia [-]. To reduce the output-ripple voltage, large value were choen for R 07 and C 05. Fig. 5 how detail of the propoed RAB. It ha -bit reitor bank to accurately compenate an RF amplifier performance. In thi approach, we have deigned an 8- bit RAB conidering a chip area overhead. The reitor bank i controlled by uing digital ignal (D 8 D D ) from the digital ignal proceor (DSP). The input data tream of (D 8 D D ) = (0 0) for 8 and ( ) for have been ued to compenate RF amplifier performance, repectively. The i under defect-free value. It wa deigned with LA on a ingle chip uing 0.8 μm SiGe technology to demontrate thi idea. It i powered by.8-v upply voltage. It wa deigned to have eparate upplie for RF and digital ection of the chip to iolate the RF circuitry from the witching noie introduced by the digital upplie. The chip divided into

4 JOURAL OF SEMICODUCTOR TECHOLOGY AD SCIECE, VOL., O.3, SEPTEMBER, 0 0 R 0 R 0 Q 03 v L Q 0 R 03 C 06 R 04 Band-gap reference v L C B v B 0 Q 0 L c0 Tet Amplifier R 08 C 0 Q 05 C03 R 09 v C 04 (a) Schematic diagram Tet Amplifier R 05 Q04 R 06 R 07 GD Peak Detector + - R R 0 Phae Detector Phae Detector & Peak Detector Cla AB Control C 05 V CC V T Q 06 Q 07 C 06 Δθ T Q 08 RF and digital ection with different ubtrate ground i divided to attenuate noie coupling from one area of a chip to another. The ditributed gate reitance of the MOS device contribute to the thermal noie []. To minimize thi reitance, the tranitor M M 8 were laid out a a parallel combination of many narrower device. The tranconductance of the tranitor were minimized to reduce the input-referred noie voltage related to the thermal noie. Thee tranitor in MOS witche, are deigned for operating in the deep triode region o that they exhibit no dc hift between the input and output voltage. The reitor, R D R S8 were ued to control a dc bia voltage of MOS witche. To verify the performance of our propoed PCC, the two-tage LA wa deigned. It i deigned for a 5-GHz IEEE80.a wirele LA application. Fig. 6(a) and (b) how the chematic and chip micrograph of the 5- GHz LA, repectively. It i powered by a -V upply. The bia tage utilize band-gap reference circuit. It control bae current for the firt and econd tage. The complete deign conit of four HBT, five inductor, five capacitor and ix reitor, all on a V CC R L c C L c C 4 Phae Detector & Peak Detector R Q 3 Q 4 R 3 C 5 R 4 v LAin R B L b RAB Q L e Q L e C 3 v LAout (b) Chip micrograph GD Fig. 4. Schematic diagram of an RF DFT. Band-gap reference Amplifier (a) Schematic diagram v in R B R D R D R D V DD RAB & bia D D D M M M R B R S Fig. 5. -bit RAB circuit. R S b R S R GD v out (b) Chip micrograph Fig. 6. Schematic diagram of RF amplifier with RAB.

5 0 WOO-CHAG CHOI et al : A PROGRAMMABLE COMPESATIO CIRCUIT FOR SYSTEM-O-CHIP APPLICATIO ingle chip. The phyical chip area i approximately.5 mm.5 mm. 4. Development of Algorithm Fig. 7 how the flowchart of the PCC for the LA performance. Our approach ha three-tep proce to compenate LA performance. The firt tep i to meaure imple output V T, V T, and Δθ T uing propoed DFT. The econd tep i to compare meaured output V T, V T, and Δθ T with reference value, V T(ref), V T(ref), and Δθ T(ref) in look-up table (LUT), repectively. Finally, the programmable compenation tep i applied to adjut LA performance when the LA ha PVT variation. If meaured V T, V T, and Δθ T have more than ±% of the reference value, V T(ref), V T(ref), and Δθ T(ref), they are automatically compenated. It compenate pecific LA pecification uch a input impedance, gain and noie figure a lited in Table. Variation lit baed on the circuit Fault imulation baed on the variation lit Variation claification baed on the fault imulation Look-up table (LUT) Circuit Circuit Simulation Circuit Layout Circuit Meaurement V T, V T & Δθ T V T V T(ref), V T V T(ref) & Δθ T Δθ T(ref)? ye Calculate RF ytem pecification Accept DUT Compenated V T, V T & Δθ T no provide DC voltage (V T and V T ), which can be ued to find LA pecification through the mathematical expreion hown in previou ection. We were able to adjut RAB with the LA circuit by providing a combination of digital code to the reitor array bank. A proce variation, we identified the mot enitive inductor component L c hown in Fig. 6(a) that contributed to varying LA voltage gain. We alo conidered temperature variation of -0 C to 70 C that contributed to varying LA noie figure. A the wort cae, we invetigated coupled variation with all PVT variation. For thee four cae, our reult verify that the propoed PCC automatically adjut and compenate LA performance uch a gain and noie figure. The V T(ref), V T(ref), and Δθ T(ref) meaured at output of the DFT circuit are hown in Table. The reult how average value from 0 time experiment, and PVT variation of within le than ±% for defect-free value are accepted. Thee value are meaured after 40 nanoecond ettling time of the PD, PD, and PHD to enure teady-tate value. Thee reult are ued to obtain input impedance, voltage gain and noie figure of the LA a hown in Table. A can be expected from imulation reult, ince the V T(ref) i proportional to LA gain, the V T(ref) ha the highet value at the operating frequency of 5 GHz. The Δθ T(ref) howed mall difference at 5.5 GHz. Thi value mean perfect matching tatu at thi frequency. When the frequency i increaed, the V T(ref) i alo increaed. A hown in Table, the meaurement howed imilar difference compared to the imulation. However, the meaurement reult howed the maximum value at a lower frequency than the imulation. Thi frequency hift may be a reult of paraitic effect at high frequency [0-]. Table. V T(ref), V T(ref) and θ T(ref) meaured by the RF DFT circuit Fig. 7. The flowchart for the PCC. Frequency [GHz] V T( ref) [mv] T( ref) V [mv] Δ θ T(ref )[ ] Simulation Meaurement Simulation Meaurement Simulation Meaurement III. MEASUREMET RESULTS The PVT defect teting of RF amplifier involve expenive meaurement equipment. Our RF DFT circuit

6 JOURAL OF SEMICODUCTOR TECHOLOGY AD SCIECE, VOL., O.3, SEPTEMBER, Proce Variation and Compenation Fig. 8 how the compenation reult for a +0% proce variation of the mot enitive component (L c ) in LA hown in Fig. 6(a). Defect-free value are obtained uing the reult of Table. The gain compenation hown in thi figure wa done at the operation frequency of 5.5 GHz. We identified a variation of 0.43 db in the LA gain from the +0% proce variation. To compenate a 0.43 db LA gain, the input data tream of (D 8 D 4 D 3 D D ) = (0 0) providing R B = (8/3)( ) wa applied. The i under defect-free value. The noie figure compenation wa alo done at 5.5 GHz providing R B = (8/3)( ). The L c +0% proce variation howed a mall variation in the LA noie figure a hown in Fig. 8. We identified a variation of 0.0 db in the LA noie figure from the +0% proce variation. A hown in Fig. 8, the propoed PCC can compenate the gain and noie figure of LA due to the proce variation at 5.5 GHz. The impedance matching network at the LA input ha a ignificant effect on the noie figure []. Thi ignificant improvement reveal that the input impedance matching from the adjutment of after compenation i optimized. The noie figure can be minimized by chooing the optimum bae reitor,.. Voltage Variation and Compenation The compenation reult for a -0. V (V cc =.8 V) voltage variation in LA i hown in Fig. 9. The gain compenation hown in thi figure wa alo performed at 5.5 GHz. We identified a variation of 0.08 db in the LA gain from the -0. V voltage variation. To compenate a 0.08 db gain variation, the input data tream of (D 8 D 4 D 3 D D ) = ( ) providing R B = wa applied. The -0.V voltage variation howed 0.0 db variation in the noie figure. (a) Gain compenation (a) Gain compenation (b) oie figure compenation Fig. 8. Compenation for +0% proce variation of inductor, L c. (b) oie figure compenation Fig. 9. Compenation for -0. V variation of upply power, V cc.

7 04 WOO-CHAG CHOI et al : A PROGRAMMABLE COMPESATIO CIRCUIT FOR SYSTEM-O-CHIP APPLICATIO A can be een from Fig. 9, the propoed PCC can compenate the gain and noie figure of RF amplifier due to the voltage variation. 3. Temperature Variation and Compenation Fig. 0 how the gain variation and it compenation reult for the +0 C temperature variation. The gain compenation wa done at 5.5 GHz. We identified a variation of 0.0 db in the gain from the +0 C variation. The input data tream of (D 8 D D ) = (0 0) providing R B = (8/5)( ) wa applied to compenate a 0.0 db gain variation. The +0 C temperature variation howed 0.06 db variation in the noie figure. A hown in Fig. 0, the propoed PCC can compenate the gain and noie figure of LA for the temperature variation. 4. Coupled Variation and Compenation Fig. how the gain variation and it compenation reult for the L c +0% proce, -0. V voltage, and +0 C temperature variation. The gain compenation hown in thi figure wa alo done at 5.5 GHz. We identified a variation of 0.84 db in the gain from the coupled variation. To compenate a 0.84 db gain, the input data tream of (D 8 D 4 D 3 D D ) = (0 0) providing R B = (8/3)( ) wa applied. The variation of db in the noie figure for thee variation wa provided. A can be een from Figure, the propoed PCC can compenate the gain and noie figure of LA due to the coupled variation at 5.5 GHz. Thi ignificant improvement in the noie figure reveal that the input impedance matching from the adjutment of after compenation i optimized []. (a) Gain compenation (a) Gain compenation (b) oie figure compenation Fig. 0. Compenation for +0 C variation of temperature. (b) oie figure compenation Fig.. Compenation for coupled variation.

8 JOURAL OF SEMICODUCTOR TECHOLOGY AD SCIECE, VOL., O.3, SEPTEMBER, 0 05 Table 3. Comparion of parametric variation and their compenation Variation Compenation Component ΔG LA(dB) ΔF(dB) Data Code R B ΔG LA(dB) ΔF(dB) L c+0% (00000) 8/ L c+0% (000000) T+0 C (000) 8/ T+0 C (0000) T+30 C (0000) T+40 C (00000) 8/ V cc-0.v () V cc-0.4v (000) 8/ L c+0%&t+0 C (00000) 8/ (a) Coupled variation L c+0%&t+0 C L c+0%&t+30 C (000000) (000000) 8/ L c+0%&t+40 C (000000) L c+0%&t+0 C ( ) 8. L c+0%&t+0 C ( ) 8. L c+0%&t+30 C ( ) 8. L c+0%&t+40 C ( ) 8. L c+0%&t+0 C (00000) 8/ & V cc-0.v L c+0%&t+0 C ( ) 8. & V cc-0.4v thi coupled variation at 5.5 GHz. Thee circle are alo drawn in the Γ plane. After compenation, the (b) Compenation Fig.. G A and noie figure compenation for parametric variation (Smith Chart). The contant noie figure circle and contant available power gain (G A ) circle for L c +0% proce, - 0. V voltage, and +0 C temperature variation at 5.5 GHz are hown in Fig. (a). Thee circle are drawn in the Γ plane. For the proce variation, the Smith chart in the Γ plane i ueful to invetigate variation of both gain and noie figure. Maximum gain and minimum noie figure cannot, in general, be obtained imultaneouly []. A hown in Fig. (a), the noie figure circle i decreaed and the G A circle i increaed due to the coupled variation. Thee reult upport increae of noie figure and decreae of available power gain. Fig. (b) how contant noie figure circle and contant available power gain (G A ) circle after compenation for noie figure circle moved to clockwie. The phae of Γ opt i approximately 57. The available power gain circle moved to counterclockwie. Thee reult reveal decreae of noie figure and increae of available power gain. Table 3 ummarize the noie figure and gain variation and their compenation reult for the PVT variation. Data code ued for compenation are lited. A can be een in thi table, the propoed PCC howed good compenation reult for the variou variation of the gain and noie figure. IV. COCLUSIOS Thi paper propoed a new programmable compenation circuit (PCC) for a Sytem-on-Chip. The PCC wa fabricated with 0.8-μm BiCMOS SiGe technology. We uccefully proved that our PCC can help to compenate LA with unuual PVT (Proce, Voltage and Thermal) variation. Utilizing our new PCC, we meaured gain and noie figure, and it automatically adjuted performance of 5 GHz LA when it went out

9 06 WOO-CHAG CHOI et al : A PROGRAMMABLE COMPESATIO CIRCUIT FOR SYSTEM-O-CHIP APPLICATIO of the normal range of operation. The PCC alo provided ucceful meaurement reult for LA chip with Reitor Array Bank (RAB). We believe that thi new capability will provide indutry with a low-cot technique to tet and compenate RFIC chip. ACKOWLEDGMETS Thi work wa upported by the Baic Reearch of RF, Korea ( , Development of Dual- Band 4 GHz/77 GHz CMOS Sytem-on-Chip for Advanced Safety Vehicle Radar). REFERECES [] J.-Y. Ryu, S.-W. Kim, D.-H Lee, S.-H. Park, J.-H. Lee, D.-H Ha, and S.-U. Kim, Programmable RF Sytem for RF Sytem-On-Chip, 00 International Conference on Future Generation Communication and etworking, pp.3-35, 00. [] J.-Y. Ryu, B.C. Kim, Low-cot tet technique uing a new rf bit circuit for GHz low noie amplifier, Microelectronic Journal: Circuit and Sytem, Vol.36, pp , 005. [3] M. Pronath, V. Gloeckel, and H. Graeb, A Parametric Tet Method for Analog Component in Integrated Mixed-ignal Circuit, IEEE/ACM International Conference on Computer Aided Deign, pp , 000. [4] H. C. H. Liu and M. Soma, Fault Diagnoi for Analog Integrated Circuit baed on the Circuit Layout, Proceeding of Pacific Rim International Sympoium on Fault Tolerant Sytem, pp.34-39, 99. [5] J. Segura, A. Kehavarzi, J. Soden and C. Hawkin, Parametric Failure in CMOS IC - a Defectbaed Analyi, Proceeding of International Tet Conference, pp.90-99, 00. [6] J. Ferrario, R. Wolf and S. Mo, Architecting Milliecond Tet Solution for Wirele Phone RFIC, Proceeding of the 003 International Tet Conference, pp.35-33, 003. [7] E. P. Vandamme, M. P. Schreur and C. van Dinther, Improved Three-tep De-embedding Method to Accurately Account for the Influence of Pad Paraitic in Silicon on-wafer RF Tettructure, IEEE Tranaction on Electronic Device, Vol.48, pp.37-4, 00. [8] K. C. Craig, S. P. Cae, R. E. eee and C. D. DePriet, Current and Future Truting in Automated RF and Microwave Teting, IEEE Proceeding, pp.83-9, 994. [9] F. R. de Soua and B. Huyart, A Reconfigurable High-Frequency Phae-Locked Loop, IEEE Tranaction on Intrumentation and Meaurement, Vol.53, pp , 004. [0] J. Y. Ryu, and B. C. Kim, A ew Deign for Built-In Self-Tet of 5GHz Low oie Amplifier, Proceeding of IEEE International Sytem-On- Chip Conference, pp.34-37, 004. [] B. Razavi, RF Microelectronic: Prentice-Hall, Inc., ew Jerey, USA, 998. [] J.-Y. Ryu and S.-H. oh, ew Programmable RF DFT Circuit for Low oie Amplifier, Journal of the Intitute of Electronic Engineering of Korea, Vol.44, o.4, pp.8-39, April, 007. Woo-Chang Choi received the B.S., M.S, and Ph.D degree in electronic engineering from Pukyong ational Univerity, Buan, Korea, in 997, 999, and 00, repectively. He i currently with the MEMS/AO Fabrication Center, Buan Techno- Park, a a enior reearch engineer focuing on many apect of RF MEMS device, nano-cmos device, and low-voltage and low-power integrated circuit. Hi current reearch interet include 3-D tacked LSI and 3-D hybrid heterointegrated LSI-MEMS. Jee-Youl Ryu received the BS and MS degree in electronic engineering from Pukyong ational Univerity, Buan, Korea, in 993 and 997, repectively, and the PhD degree in electrical engineering from Arizona State Univerity, Tempe, in December 004. He i currently a profeor at Pukyong ational Univerity. Hi current reearch interet include the deign and teting of Sytem-on-Chip, the deign and teting of RF integrated circuit, and the deign of embedded ytem.