HIGH VOLTAGE DC-DC CONVERTER USING A SERIES STACKED TOPOLOGY

Transcription

1 HIGH VOLTAGE DC-DC CONVERTER USING A SERIES STACKED TOPOLOGY Author: P.D. van Rhyn, Co Author: Prof. H. du T. Mouton Power Electronic Group (PEG) Univerity of the Stellenboch Tel / Fax: nielvr@un.ac.za Abtract: A part of contructing a high power DC-AC inverter, a erie tacked DC-DC converter i analyed and imulated. The tack conit of a number of iolated, full-bridge topology converter. The lower input voltage rating of each individual converter i combined to form a new converter which ha a higher input voltage rating. The converter will be ued to charge a large battery bank a well a upplying power to a contant power aborbing load. It will have to operate in either contant current mode or contant voltage mode, depending on the tate of charge of the battery bank. Peak current mode control i implemented to give thi functionality to the converter. The erie tack topology alo allow interleaved witching which reduce the ize of filter component. Thi paper cover the baic concept behind thi erie tacked topology and ome control apect and conideration, a well a imulation of converter. 1 INTRODUCTION Even though witch voltage rating have greatly improved in recent year, it i till neceary in higher voltage application to connect witche in erie to meet the high voltage demand of ome ytem [1]. Thee high voltage demand could alo be met by connecting converter in erie or to make ue of one of the multilevel topologie [2, 3]. Thee topologie could be the flying capacitor or the diode clamp topology. In general thee multilevel topologie are ued in DC-AC or AC-AC inverter. The main advantage of thee topologie i there harmonic reduction property. By uing an appropriate modulation technique (like a quare wave reference) in thee topologie it could be poible to ue thee topologie in DC-DC converion. The cope of thi paper i to invetigate the ue of a erie tack of converter in order to create a high voltage DC-DC converter. Thi converter will form part of an indutrial power upply witch invert a DC upply of between 2 and 4kV into a 23V AC output. The output will be three phae and the inverter will have a power rating of 5kVA. The inverter will conit of two part a hown in figure 1. The upply voltage will firt be converted to 11V DC by a DC-DC converter and then inverted to a three-phae output voltage. The reaon for thi i that a 11V battery bank i tandard equipment in every Spoornet ubtation, where the converter will be intalled. The battery bank will be ued a a backup upply for the DC-AC converter if the ytem input upply i out. The function of the DC-DC converter i to charge the battery bank and upply power to the DC-AC converter if a load i preent. DC-DC Converter Battery Bank 2kV to 4kV DC 11V DC-AC Converter Fig 1: Sytem overview 23V AC Section 2 of thi paper look at the converter topology while ection 3 cover ome control apect. Section 4 will look at imulation and reult obtained from thee imulation. In the lat part of thi paper concluion are made and poible future work i dicued. 2 THE CONVERTER TOPOLOGY The output voltage of thi converter will be lower than the input voltage. It i thu a buck type converter. The individual converter that form the main converter could alo then be buck type converter but thi i not eential a a tranformer will be ued for electrical iolation. To decide which

2 of the many buck derived topologie to ue for the individual converter topology, the following factor are conidered. S11 S12 L f 1 A a deign pecification, the converter will have to be electrically iolated. The individual converter are alo high power converter (12.5kW each). Operation in contant current mode and contant voltage mode are eential. V IN C IN1 S13 S14 S21 S22 T 1 L f 2 The half-bridge and the full-bridge topologie are both uitable for handling the required power and uited for tranformer implementation. The deciding factor i that peak current control will have to be implemented to enable contant current and contant voltage control in the converter. The half-bridge topology i not uited for current mode control a light component and duty ratio mimatche could caue a bulk capacitor unbalance [5]. Another concern of the half-bridge topology i large ripple current through the bulk capacitor. The full-bridge topology i choen and will be ued a individual converter topology. One concern of uing the fullbridge topology i that, although current mode control i ued, the tranformer core might till aturate. Thi i becaue inductor current i meaured, on the econdary ide of the tranformer, and not the tranitor-emitter current on the primary ide of the tranformer [5]. The converter i hown in figure 2. The topology ha it origin from the Input-Serie-Output-Parallel- Connected converter propoed by Kim [6]. Thi idea of putting the input in erie and the output in parallel i ued. Figure 2 how a implified part of the converter. The individual full-bridge converter are connected in erie and the output are paralleled. Thi connection hold the following advantage: If n converter are connected in erie, the witch voltage rating can be reduced to V IN, a long a the bu capacitor are n balanced. The maximum voltage rating of all the emiconductor i reduced. The output current i hared among the converter. C IN 2 S23 S24 Fig 2: Converter topology The diadvantage of thi topology are: T 2 There are a larger number of emiconductor, which increae the chance of ytem failure. The witch voltage rating may be exceeded if the bulk capacitor do not balance. 3 CONTROL OF THE CONVERTER Controlling the converter i an eential part of the eventual ucceful operation of the converter. The converter will be expoed to change in input voltage, change in load and, a mentioned in ection 2, will have to operate in contant current mode a well a contant voltage mode. Lat mentioned will depend on the tate of charge of the battery bank. Peak current mode control [5] will be implemented to control the converter. In peak current control the witch or inductor current i meaured and compared to a reference value. The witch (or witche, depending on the converter topology) i turned on while the meaured current i le than the reference and then turned off a it reache the reference. Normally a clock pule will then turn the witche on again and the cycle repeat itelf. In thi converter bipolar voltage witching i ued [7]. Thi mean that witche S 11 and S 14, and witche S 12 and S 13 are witched together. The control ignal of one converter witch pair are 18 degree out of phae. To realie interleaved witching thee ignal are then hifted by 36 ( n i the number of converter in n the tack) and ued a control ignal for the ret of the converter in the tack. Thi will enure bulk capacitor balance [2]. C f

3 By uing peak current mode control we can directly control the current if the reference value of the comparator i kept contant. The voltage i controlled indirectly by changing the reference according to the output voltage (uing U v in figure 3). The witch in figure 3 i ued to elect between contant current mode (poition 1) and contant voltage mode (poition 2). Peak current mode control hold many advantage and ome diadvantage [5]. Some are lited below. Advantage: Fater cloed loop repone if current loop i fater than voltage loop. Automatic pule-by pule current limiting. Better line regulation due to feed-forward property. Diadvantage: Slope compenation i needed to enure tability. Noie immunity i wore becaue of hallower ramp. When the dc component of the meaured current i large, it become difficult to meaure the ac ripple uperimpoed on it. V IN Power Stage PWM L f - Comp C f Load 2 C V1 R V1 C 1 R V 2 Lag U v Lead - V OUT C V 2 R V 4 R V 3 V REF Fig 3: Simplified peak current mode control circuit Figure 3 how a implified current mode control circuit ued to control the converter. The circuit i motly elf-explanatory. Note that in contant current mode the load and battery bank contribute to the total output current. Thu a contant (C) i added to the meaured load current to accommodate both thee current. Compenation i done for the voltage loop and thu the preence of the lead and lag compenator. Control block diagram of the ytem are preented in figure 4. V ref 1 C K GLAG () GLEAD GLP () () d Fm T v (a) T i Fm d Gdv G di I Load Gdv (b) Fig 4: Control block diagram of ytem. (a) Contant voltage mode (b) Contant current mode In figure 4(a) G (), G () and K form the LAG LEAD 1 compenator for the voltage control loop. F m i the error ignal (voltage or current error, depending on the mode of operation) to duty cycle tranfer function, G the duty cycle to output voltage dv tranfer function and G the duty cycle to inductor di current tranfer function. repreent the tranfer function of the current meaurement and i contant in thi cae. =.78, The tranfer function were calculated for a reitive load ( R ) and uing the ame technique a preented in [4]. Note that G and G are the ame a for the ingle dv di full-bridge converter [7], except that the filter inductance, L, i replace by L. 4 Thi i a multi-loop ytem and conit of a inner T. To current loop ( ) i G di T, and a outer voltage loop ( ) gain any inight into the tability of the ytem the open loop gain of thee two loop are plotted, uing bode-plot. A lead and lag compenator are then deigned for the voltage loop to enure that the current loop i fater than the voltage loop, and that a good phae margin i preent in the voltage loop. Looking at i T and v T alone i not ignificant to enure ytem tability [8]. Two new loop gain are defined to gain more inight into the ytem behaviour. v o i L v v o i L

4 T1 = Ti Tv and T2 Tv = 1 T The loop gain are alo plotted uing the bode-plot technique and ued to verify ytem tability. Figure 4(b) how the control block diagram if the converter operate in contant current mode. The load current meaured i added to C and ued a a reference a explained earlier. Thi form a new feedback loop which could caue intabilitie if proper compenation i not implemented. The tranfer function of duty cycle to load current i not known and thu a compenator could not be deigned a in the contant voltage mode cae. A low pa filter G () i implemented to eliminate udden LP change in reference which could caue intabilitie. The control method implemented ue one meaured inductor current together with the output voltage reference to control the main converter. Another way of controlling the converter ytem i to control all the individual converter eparately uing the ame controller dicued earlier. An additional hare control loop could then be added to hare the current among the converter [9]. Thi control will unfortunately not guarantee capacitor balance. Thi problem could be olved by adding yet another control loop. 4 RESULTS FOR CONVERTER SIMULATION The two mode of converter operation were imulated uing Simplorer. The imulation wa done for a caled model of one tenth the voltage and current rating of the converter to be built practically. The converter parameter are a follow. Switching frequency f =5kHz Input voltage 2 < V in < 4. Output voltage V out = 13.4 V Filter inductance L f = 1mH Maximum output power P max = 6W Filter capacitance C f = 47uF Tranformer winding ratio N = 2:1 Number of converter in tack n = 4 Interleaved witching wa implemented in imulating the converter. 4.1 Contant voltage mode operation. The firt imulation wa done to look at the tep repone of the converter in contant voltage mode. Figure 5 how the output voltage and current (V out, I out ), a well a one of the filter inductor i current (I L1 ). Note that, a we expect, the total output current i four time the inductor current. For thi imulation the input voltage i fixed at 4V and the load reitor i equal to 1.34 Ohm (thu 1A output current). The ettling time appear to be good (le than 2m). The current overhoot i high. To better thi overhoot, the repone could be made lower by decreaing the gain in the voltage loop or to make the compenator lower. [V],, [A] Fig 5: Step repone in contant voltage mode Figure 6 how the inductor current of the four converter. A expected for interleaved witching, the inductor current are hifted by 5u with repect to 36 each other (correponding to ). The n conv. in tack um of thee current will form the total ripple current with n time the frequency. The amplitude of the ripple current will be le than 1/n % of one inductor current, but could be le depending on the duty cycle. /4,, IL2, IL3, IL4 [A] x 1-3 IL2 IL3 IL4 /4 Fig 6: Inductor current and output current Figure 7 how the capacitor voltage for a 3V input voltage. It i clear that they remain balanced at 3 75V n =.

5 85 5 Vc1, Vc2, Vc3, Vc4 [V[ [V], [A] x 1-3 Fig 7: Bulk capacitor voltage To ee what effect component tolerance will have on the converter, component were randomly choen and given a 1% tolerance. No ignificant difference were viible. Only a light offet in one of the inductor current (figure 8) wa viible., IL2, IL3, IL4 [A] IL2 IL3 IL x 1-3 Fig 8: Inductor current for component mimatche Fig 9: Output voltage and current repone to a load tep 4.2 Contant current mode operation. The tep repone of the converter operating in contant current mode i hown in figure 1. Thi imulation i done with the battery bank diconnected from the output. The reaon for thi i that we only want to look at the repone time of the contant current loop. The load voltage and current, one inductor current and battery current are hown. It i clear that the repone time i much lower than in the voltage loop. Thi i becaue of the low pa filter implemented in the contant current loop. In thi cae it i only important that output voltage and output current ettle and the exact value are not that important. Latly the line and load regulation were imulated. Figure 9 how the output voltage when the input voltage i tepped up from 2V to 4V. Good line regulation i viible a expected for current mode control. Load regulation i alo good. A load reitance tep from 1 Ohm to.29 Ohm wa imulated. The reult i hown in figure 9. The output current tep (1A to 45.4A) i hown a well a the output voltage which i regulated at 13.4V. [V] Fig 8: Output voltage repone to input voltage tep [V],, [A] Fig 1: repone in contant current mode Figure 11 and 12 how the repone of the converter to an input voltage tep and a load tep. In thi imulation the battery bank (modelled by a contant voltage ource in erie with a reitor) i connected to the output. The battery bank i not fully charged and in the battery model, the voltage ource i et to 12V. It can be een that the converter i table when load current and input voltage tep occur, while charging the battery with a contant current.

6 2 Future work will look at the practical implementation of the ytem. [V],, Ibat, [A] 1-1 Ibat 6 REFERENCES [1] Horowitz, Hill, The art of electronic, Second edition, Cambridge univerity pre, pp [V],, Ibat, [A] x 1-3 Fig 11: Repone with tep in input voltage x 1-3 Fig 12: Repone with tep in load current. A in contant voltage mode the bulk capacitor alo balance, but take longer to ettle becaue of the low reponding low pa filter preent in contant current mode control. Figure 13 how the voltage acro the bulk capacitor. Vc1, Vc2, Vc3, Vc4 [V] Fig 13: Bulk capacitor voltage in contant current mode 5 CONCLUSIONS Thi paper explained the concept of tacking multiple converter in erie to accommodate high input voltage. The converter operate in contant voltage and current mode. A control cheme i looked at to control the converter in thee two mode. The ytem wa imulated to enure that the bulk capacitor balance, inductor current hare equally, voltage regulation i good in contant voltage mode and that the battery charge current i contant in contant current mode. The reult obtained ugget that the ytem i table under all operating mode and condition. Ibat [2] H. du T. Mouton, Analyi and ynthei of a 2 MVA erie-tacked power-quality conditioner, PhD Thei, Univerity of Stellenboch, Stellenboch, South Africa, December [3] Peng, F. Z. (21). "A generalized multilevel inverter topology with elf voltage balancing." Indutry Application, IEEE Tranaction on 37(2): [4] Lload H. Dixon, Jr. Current-Mode Control of Switching Power Supplie, 24 [5] Mitchell, Mammano, Deigning Stable Control Loop, 24 [6] Kim, J.-W., J.-S. Yon, et al. (21). "Modeling, control, and deign of input-erie-output-parallelconnected converter for high-peed-train power ytem." Indutrial Electronic, IEEE Tranaction on 48(3): [7] Mohan, Undeland, Robbin, Power electronic, Second edition, Wiley, pp [8] Ridley, R. B., B. H. Cho, et al. (1988). "Analyi and interpretation of loop gain of multiloopcontrolled witching regulator [power upply circuit]." Power Electronic, IEEE Tranaction on 3(4): [9] Lin, C.-S. and C.-L. Chen (2). "Single-wire current-hare paralleling of current-mode-controlled DC power upplie." Indutrial Electronic, IEEE Tranaction on 47(4):