Comparative Study of PLL, DDS and DDS-based PLL Synthesis Techniques for Communication System

Transcription

1 International Journal of Electronic Engineering, 2(1), 2010, pp Comparative Study of PLL, DDS and DDS-baed PLL Synthei Technique for Communication Sytem Govind Singh Patel 1 & Sanjay Sharma 2 1 ECED, Lingaya Univerity, Haryana, INDIA 2 ECED, Thapar Univerity, Punjab, INDIA Abtract: The phae locked loop(pll) ha been widely ued in wirele communication ytem due to the high frequency reolution and the hort locking time. The Direct Digital Synthei(DDS) i alo an emerging and maturing ignal generation technology. But another advanced technique in which, DDS ignal i mixed with the voltage-control ocillator output in the PLL feedback path. Thi olution help in avoiding ome of the typical tradeoff in PLL. In particular, it i poible to achieve a very high-frequency reolution together with fat ettling and pectral purity. The propoed deign conit in decribing the mixed behavior of thi DDS-baed PLL architecture tarting from the pecification of each building block. The HDL model of critical PLL block have been decribed in VHDL-AMS to predict the different pecification of the PLL. The effect of different noie ource ha been efficiently introduced to tudy the ytem performance. The obtained reult are compoed with tranitor-level imulation to validate the effectivene of the propoed model. The comparative tudy howed the performance of different parameter. Finally, DDS- baed PLL architecture i better than other architecture. Keyword: Phae Locked Loop(PLL), Direct Digital Synthei(DDS) and Frequency Synthei. 1. INTRODUCTION A Phae Locked Loop i a cloed loop control ytem which i ued for the purpoe of ynchronization of the frequency and phae of a locally generated ignal with that of an incoming ignal. It i baically a nonlinear feedback loop. The PLL conit of a voltage controlled ocillator (VCO), a phae detector, a variety of divider, and a loop filter. DDS i an emerging and maturing ignal generation technology. DDS conit of Phae Accumulator, Lookup table and DAC converter. In a general PLL yntheizer, the diviion ratio become large if frequency reolution i increaed. Thi decreae the phae comparion frequency. Conequently, the PLL output phae tability i degraded. Becaue here the reference clock i converted once by the DDS, it i poible to make the PLL phae comparion frequency large enough. It i obviou that puriou component exit in the DDS output, but they can be uppreed by the PLL low pa characteritic. The DDS i intalled in the PLL feedback circuit. In thi cae, too, the PLL phae comparion frequency can be raied by adjuting the DDS output frequency. Thi alo improve the PLL phae tability[1]-[2]. 2. ARCHITECTURE 2.1. Phae Locked Loop A Phae Locked Loop i a cloed loop control ytem which i ued for the purpoe of ynchronization of the frequency *Correponding Author: govindpatel99@rediffmail.com 1, anjay.harma@thapar.edu 2 and phae of a locally generated ignal with that of an incoming ignal. It i baically a nonlinear (the phae detector i a nonlinear device) feedback loop, a hown in fig. 1. The PLL conit of a voltage controlled ocillator (VCO), a phae detector, a variety of divider, and a loop filter. The VCO i a device whoe output frequency depend on the input control voltage. The relation i nonlinear but monotonic. However, when locked, the VCO can be aumed to be linear; it i both practical and convenient for analytical purpoe. Figure 1: PLL Block Diagram. Variation in the VCO control characteritic (i.e., thi nonlinearity) affect the loop parameter, and loop linearization (or compenation) i ued extenively. Generally, the VCO output waveform i given by A out [t, ω(v)] = A(t, v) in [ω(v)t + j] (1) Where A i the ignal amplitude and ω i the angular frequency, both depending on time t, and control voltage v. A a firt approximation, we aume that A ha a contant

2 36 International Journal of Electronic Engineering envelope (doe not depend on t or v) and that ω i a linear function of v. Therefore we can write eq. (1) a A out (t) = A in[ω 0 + k ν v)t + ϕ] (2) Here K v i the VCO contant [rad/(v)]. Since we aume that the frequency i linearly dependent on v and i given by ω(v) = ω 0 + k ν v (3) A mentioned, the linearization i jutified and i aumed for the purpoe of impler analyi. In reality, when the loop i locked, frequency variation are tiny, and the contant-vco aumption i correct a a piecewie linearization of the graph in fig. 2. Since phae i the integral of the angular frequency, we can complete the approximation by writing that the VCO tranfer function, given by ϕ 0 () V = K v A the Laplace tranfer function of the VCO output phae. The phae detector produce an output voltage proportional to the difference in phae between it input and i alway a nonlinear function. Typical phae detector output tranfer function are hown in fig. 3. However, cloe to the locked poition thi function can be aumed to be linear (thi i alo jutified ince in the locked condition mot frequency yntheizer operate with a very high ignal-tonoie ratio and the phae detector therefore operate mainly at a fixed-phae poition). Hence (4) V d = K d (ϕ i ϕ 0 )V/rad (5) Where V d i the phae detector output voltage. Now the loop tranfer function can be decribed a Let V c = V d ()F() V d = Kd [()()] ϕi / rad ϕ0 V (6) control voltage Where F() i the loop filter tranfer function and V c i the VCO control voltage. Solving thee imple equation yield ϕ 0 () = ϕ ()() K K F i d v + K K F() and the tranfer function H()= ϕ o ()/ ϕ i () i given by H() = v d K K F() d v + K K F() v Alo, following thee equation will how that the error tranfer function, defined a i given by H e () = d ϕ ()() ϕ i ϕ () i o (7) (8) (9) H e () = K K F() + d v (10) Since we linearzed all component, given K v and K d, the feedback loop behavior depend mainly on F(). Alo note that the error function ha high-pa characteritic, and therefore a true direct-current (dc) modulation of a PLL circuit i not poible. Thi function, however, alo referred to a dc frequency modulation, i poible in other ynthei technique [3] Direct Digital Synthei DDS i an emerging and maturing ignal generation technology. Up to 10 year ago, thi technique wa rather a novelty and wa ued in very limited application. However, due to the enormou evolution of digital technologie (peed, integration, power, cot), digital ignal proceing (DSP), and data converion device, it i becoming increaingly popular, and it performance improve contantly [4]. There i a fundamental difference between DDS and PLL. Although both PLL and DDS technique ue digital device, but the PLL technique i fundamentally analog dicipline. The baic ignal generator in both technique i an ocillator, which i a feedback - tuned amplifier et to operate under pecific condition (controlled intability). The ocillator i manipulated to allow the generation of a range of frequencie. In DDS, the ignal i generated and manipulated digitally from the ground up, and after all the digital manipulation are completed, it i converted to an analog ignal via a digital-to-analog converter [5]. Figure 2: DDS Block Diagram and Waveform 2.3. DDS driven PLL Frequency Syntheizer Architecture Figure 3: Block Diagram of the DDS driven PLL Frequency Syntheizer

3 Comparative Study of PLL, DDS and DDS-baed PLL Synthei Technique for Communication Sytem 37 The block diagram of the DDS-driven PLL frequency yntheizer i hown in fig. 3. The reference frequency of DDS, f ref, i generated by a crytal ocillator. The output frequency of DDS, f DDS, i controlled by the frequency tuning word. The reference of the PLL i driven by the output of DDS, f DDS. The output of VCO i controlled by the output of Charge Pump (CP) of PLL. The output ignal of thi frequency yntheizer of obtained by multiplying f vco. The PLL module ha a dual-modulu precaler that ha the pule wallow function. Thi enable the large diviion ratio. The dual-modulu precaler make it poible for the frequency yntheizer to generate higher output frequency while the frequency reolution i improved. The equation for the VCO frequency i f f vco = () BP + A DDS (11) R The frequency of DDS i controlled by the frequency tuning word K, and K f DDS = CLK 2 N f (12) Where N i the phae accumulator reolution of DDS and f CLK i the internal clock of DDS. Then equation (11) can be written a f VCO = () BP + A K f N CLK R 2 (13) In the cheme hown in fig. 3, ince DDS module ha good frequency reolution, from (13) we can find that the output ignal ha a better frequency reolution than traditional cheme. K. The output of DDS can be decribed a f DDS = () K + K t f N CLK (14) 2 Where K i the changing rate of frequency tuning word Since the output of VCO i phae locked to the DDS, the output frequency of VCO change according to the change of DDS. The output frequency of VCO can be decribed a f VCO = ()() BP + A + K K t (15) N R 2 It determine the changing rate of the frequency of the output ignal. Thee parameter can be imulated / analyzed by VHDL-AMS[6]-[9]. 3. ANALYSIS AND SIMULATION In order to analyi and evaluate the performance of the frequency yntheizer we propoed in thi paper, we analyzed the frequency ettling time and yntheized ignal of PLL and pectrum analyi of NCO uing MATLAB. Figure 4: Phae Locked Loop

4 38 International Journal of Electronic Engineering Figure 5: Reference Signal of Input of PLL The reult howed yntheized ignal of PLL in fig. 6. The amplitude of Input ignal i 1v and time period i Figure 6: Reference Signal of PLL 1*10 5 ec. in fig. 5. Frequency ettling time i quite important for the frequency yntheizer to generate ignal. Here ettling time i 1*10 5 ec. in fig. 7. Figure 7: Control Signal of PLL

5 Comparative Study of PLL, DDS and DDS-baed PLL Synthei Technique for Communication Sytem 39 Figure 8: Numerically Controlled Ocillator The pectrum analyi of Sine wave input i howed in fig. 9, it how peak repone at frequency 0.29 KHz. The pectrum analyi of Coine wave input i howed in fig. 10, it how peak repone at frequency 0.3 KHz[10]. Figure 9: NCO Spectrum of Sine Wave.

6 40 International Journal of Electronic Engineering Figure 10: NCO Spectrum of Coine Wave. 4. CONCLUSION The propoed comparative tudy conit of PLL, DDS and DDS- baed PLL. A DDS- driven PLL frequency yntheizer architecture i given in thi paper. The reult of DDS- baed PLL architecture decribing the mixed behavior of thi DDSbaed PLL architecture tarting from the pecification of each building block. The HDL model of critical PLL block have been decribed in VHDL-AMS to predict the different pecification of the PLL. The effect of different noie ource ha been efficiently introduced to tudy the ytem performance. The comparative tudy howed the performance of different parameter. Finally, DDS- baed PLL ynthei technique i better than other technique. REFERENCES [1] Dan Morelli, Modulating Direct Digital Syntheizer in a FPGA, VP of Engineering Accelent Sytem Inc, QuickLogic, pp , Feb [2] Bar-Giora Goldberg, Digital Frequency Synthei Demytified, 6 th Edition, LLH, Publihing Technology, 1999, Ch. 1, pp [3] Roland E. Bet, Phae-Locked Loop: Deign, Simulation & Application, 4 th Edition, McGraw-Hill Profeional Engineering, June 1999, Ch. 5, pp [4] Pacal Nelon, Deign and Analyi Freq. Syntheizer uing FPGA a Reconfiguration Hardware, Analog Device Inc.(Greenboro, N.C.), EE Time Publication, pp , Sept [5] Martin T. Hill and Antonio Cantoni, A Digital Implementation of a Frequency Steered Phae Locked Loop, IEEE Tranaction on Circuit and Sytem: Fundamental Theory and Application, 47, No. 6, pp , June [6] A. Telba, J. M. Nora, M. Abou El Ela and B.AIMahaq, Simulation Technique for Noie and Timing Jitter in Phae Locked Loop, IEEE Tranaction on Simulation Technique, pp , Aug [7] Stefan Scheiblhofer, Stefan Schuter and Andrea Stelzer, Signal Model and Linearization for Nonlinear Chirp in FMCW Radar SAW-ID Tag Requet, IEEE Tranaction on Microwave Theory and Technique, 54, No. 4, pp , April [8] S. Walter and T. Troudet, Digital Phae-Locked Loop with Jitter Bounded, IEEE Tranaction on Circuit and Sytem, 36, No. 7, pp , July [9] Longjun Zhai, Yonghuna Jiang, Xiang Ling and Weilang, DDS-Driven PLL Frequency Syntheizer for X- band Radar Signal Simulation, IEEE Conference on Communcation in China, pp , Dec [10] A.Bonfanti, F. Amoroa, C. Samori and A. L. Lacaita, A DDS- baed PLL for 2.4 GHz Frequency Sythei, IEEE Tranaction on Circuit and Sytem-II : Analog and Digital Signal Proceing, 50, No.12, pp , Dec.2003.