A Feasibility Study on Frequency Domain ADC for Impulse-UWB Receivers

Transcription

1 A Feaibility Study on Frequency Domain ADC for Impule-UWB Receiver Rajeh hirugnanam and Dong Sam Ha VV (Virginia ech VLSI for elecommunication Lab Department of Electrical and Computer Engineering Virginia ech, Blacburg, VA 46 {thirugnr, Abtract A feaibility tudy of frequency domain ADC for an Impule-UWB receiver i preented. A frequency domain ADC conit of a ban of narrow band bandpa filter and integrator, followed by a conventional ADC. he filter ban produce the pectrum ample (Fourier erie coefficient at frequencie correponding to the center frequencie of the bandpa filter in the filter ban. he Fourier erie coefficient are ampled and quantized by a conventional time domain ADC. In the baeband of the I-UWB receiver, the digitized Fourier erie coefficient can be proceed in the frequency domain or the pule can be recontructed and proceed in the time domain. Sampling in the frequency domain, avoid the need for an ADC with a wide bandwidth and a high ampling rate for an I-UWB receiver. Simulation reult on a mathematical model of a frequency domain ADC how that pacing the center frequencie of the bandpa filter at MHz over the band of interet lead to a pule recontruction error of ~ % for a 5-bit ADC. Practical implementation iue in integrated circuit realization of the frequency domain ADC are decribed a well. Index erm ADC, Filter ban, Impule UWB, Receiver Architecture I. INRODUCION When compared to the traditional narrow band communication ytem, ultra wideband (UWB technology ha everal advantage uch a high data rate, low-radiated power, excellent immunity to multipath, and imple hardware. UWB uit many application uch a wirele home networing, enor networ communication, and through-the-wall ening. Realization of UWB ytem in CMOS technology i highly deirable for mot UWB application, but it poe a great challenge for VLSI deigner. here are two main flavor of UWB ytem, carrier-baed (MB-OFDM and DS-CDMA and impule-baed (I-UWB. Integrated circuit realization of I-UWB tranceiver in CMOS place extremely high requirement on the RF front end and the data converter []. he challenge tem from the fact that I-UWB i baed on extremely narrow pule which require high-peed and wide bandwidth circuit for ampling and recontruction of extremely narrow pule. Exiting CMOS analog-to-digital converter (ADC cannot meet the ampling rate neceary for ampling of thee UWB pule. In addition to the high ampling rate, timing jitter mae precie control of ampling time intractable. Many different technique have been propoed for implementing high peed ADC viz. the time-interleaved ADC [], uing bandpa filter to divide the band of interet into everal ub-band and digitizing ignal in the ub band [3]. o eae the requirement on the ADC, analog to digital converion in the frequency domain ha been propoed by the author group [4] [5] firt and then by Hoyo et. al [6] [7], independently. Although, there are ome parallel with our approach and the approach propoed in [6], the hardware implementation are vatly different. he method propoed in [6] ue mixer followed by integrator. he method require everal cloc generator, i power hungry and alo ha noie iue. In our approach, we ue narrow band bandpa filter and integrator to extract the Fourier erie coefficient at frequencie correponding to the center frequencie of the bandpa filter. he extracted Fourier erie coefficient are digitized uing an ADC for further digital ignal proceing. he digitized Fourier erie coefficient then can be proceed in the frequency domain or the ignal can be recontructed in the time domain by performing an Invere Fat Fourier ranform (IFF on the Fourier erie coefficient and then proceed in the time domain. Intead of mixer and multiple cloc generator, adoption of filter mae our architecture highly uitable for integrated implementation of I-UWB tranceiver. he ampling rate of the conventional ADC employed in the frequency domain ADC i independent of the frequency content of the impule ued for modulating the data and i limited only by the data rate and the number of bandpa filter. In thi wor, we explore the tradeoff between the number of bandpa filter and the reolution of the ADC through imulation. Some of practical implementation iue of the filter ban in integrated circuit are alo dicued. he ret of the paper i organized a follow. Section II review ignal analyi in the frequency domain and the overall architecture of the frequency domain ADC. Section III decribe the imulation tudy of the frequency domain ADC. he trade-off between the number of filter and the reolution of the time-domain ADC are tudied by calculating the pule recontruction error. Section IV dicue practical iue in implementing the frequency domain ADC. Section V conclude the paper. II. PRELIMINARIES hi ection review the theory behind extraction of Fourier erie coefficient from the time domain ignal uing bandpa filter and the architecture of the frequency domain ADC. A. Signal Analyi in the Frequency Domain A continuou time periodic ignal with a period can be expreed a = = + = j πft e x (t c ( /8/$5. 8 IEEE

2 j πft c = x(t e dt ( p where F = / i the fundamental frequency of the ignal x(t, and a Fourier erie coefficient c repreent the pectral component of the ignal [8]. Note that c are uually complex value, and c and c- are complex conjugate. he period i the obervation window of the received ignal, which i often a fraction of the data rate or Pule Repetition Interval (PRI. Oberve that c can be calculated by multiplying the time domain ignal with inuoidal ignal and integrating the reult over a time period. Direct implementation of ( require multiple cloc generator, mixer and integrator a hown in [6][7]. Noting that π ω = πf = and uing the periodic characteritic of a inuoidal function, ( lead to the relation given in (3. c = ω ω x(t co( t dt j x( t in( t p c dt = τ ω τ τ τ ω x( co( ( d j x( in( ( p = x(t co( t + jx(t in(t t = p τ dτ c (3 where i integer and * i the convolution operation. Noting, L{ co( ω t } =, { } L in( t = + ( + ( Where L {} repreent the Laplace tranform of x(t. (3 can be expreed a following. = L X( + ( + jl X( + ( c (4 t= where X( i the Laplace tranform of x(t. Our propoed implementation of frequency domain ADC which calculate and quantize c i baed on (4. Fig. how (4 in a bloc diagram form. he bloc repreenting the tranfer function can be thought of + ( a a narrow band bandpa filter by oberving that the tranfer function of a bandpa filter i repreented by + + ( Q Q [9]. Where the parameter Q i defined a in (5 = ω (5 3dB where i the center frequency of the bandpa filter and ω 3dB i the bandwidth of the filter. he term Q factor often occur in filter pecification a it define the relationhip of filter bandwidth to it center frequency. It can be noted that a the bandwidth goe down and the center frequency increae, Q factor increae. Extremely narrow bandwidth filter are ometime called infinite Q filter []. We ll follow imilar terminology in the ret of the paper. he bloc with the tranfer function with a pole at DC. x(t + ( Band pa filter ω repreent an ideal integrator, Integrator Figure : Fourier erie coefficient ampler Real(c Imag(c he output of the infinite Q bandpa filter ampled at give the real part of the Fourier erie coefficient c. he output of the infinite Q bandpa filter integrated by an ideal integrator with a gain of and ampled at give the imaginary part of the Fourier erie coefficient c. Implication for realization of thee bloc in integrated circuit will be dicued in ection IV. B. Frequency Domain ADC Conider a train of pule at a receiver a hown in Figure. Our goal i to obtain ampled value of the individual pule uing an ADC. Let τ be the obervation window of each pule and i the PRI. Aume that pule require over-ampling by a factor of N. he conventional method, which over-ample a pule by factor of N during τ with a ingle ADC, require the ADC to ample at a rate of N/τ. For example, the ampling rate i an impractical 3 GHz for N=8 and τ = 5 p. Fig. : Received input pule he architecture of the frequency domain ADC i given in Fig. 3. he received ignal x(t i applied to a ban of filter tructure hown in Fig.. he center frequencie of the infinite Q bandpa filter are paced equally within the band of interet ued for I-UWB communication. he filter ban output the Fourier erie coefficient c correponding to the center frequencie of the bandpa filter. he output of the filter are ampled at the end of the obervation period τ. A ingle ADC weep through the filter bac output from *N ample and hold once every econd, where N i the number of filter in the filter ban and i the PRI. Sampled Fourier erie coefficient are then digitized by a conventional ADC. he digitized fourier erie coefficient can be proceed in the

3 frequency domain for a fully frequency domain I-UWB receiver or the original pule can be recontructed by performing IFF on the Fourier erie coefficient and then the time domain ample of the pule can be proceed. ampling rate of GHz. he effective ampling rate can be increaed (decreaed by increaing (decreaing the number of zero. For example, conider 5 MHz frequency pacing with 5 filter ban. o meet a target ampling rate of GHz, ample (GHz/5MHz + are required to recontruct the frequency pectrum from DC ( Hz to half the ampling rate ( GHz. hu, 5 zero are inerted to cover the pectrum from to.5 GHz followed by 5 frequency ample obtained from the frequency domain ADC in the band from 3 GHz to 5 GHz and then zero are inerted to cover the pectrum from 5.5 GHz to GHz. ABLE I. NUMBER OF FILERS VS. FREQUENCY SPACING Fig. 3: Frequency domain ADC architecture III. SIMULAION RESULS WIH IDEAL FILER BANKS hi ection decribe the imulation etup for evaluation of our frequency domain ADC and impact of the number of filter and the ADC reolution on the pule recontruction. A. Simulation Setup In order to verify the performance of the frequency domain ADC, we modeled equation (4 in Matlab. he input pule wa a Gauian mono-pule. he lower band of UWB communication (3-5 GHz band wa choen for imulation. he pule wa band-limited to 3-5 GHz with a 8-tap Ramez digital filter. he band-limited pule wa normalized to have a Vp-p of V and i hown in Fig Frequency Spacing (MHz Number of Filter Ban he frequency pectrum ample or the Fourier erie coefficient output by the filter ban are then digitized by an ADC modeled in Matlab. he IFF operation i performed on the quantized pectrum ample and the recontructed frequency pectrum. he pule and recontruction error are illutrated in Fig. 5 for two different combination of number of filter and ADC reolution..5 No. of Filter = ADC reolution = 8 Original pule Recontructed pule.5 No. of Filter = 5 ADC reolution = 5 Original pule Recontructed pule ime(n ime(n 5a: Recontructed Pule 5c: Recontructed Pule Error. Error ime (n Fig. 4: Band-limited pule (3-5 GHz band he center frequency of the bandpa filter wa paced equally in the 3-5 GHz band. he number of filter for correponding frequency pacing in the 3-5 GHz band i hown in able I. For example, a frequency pacing of MHz in the 3-5 GHz band correpond to GHz/ MHz + = filter becaue the frequencie at the band edge viz. 3 GHz and 5 GHz have to be covered a well. he pectral component correponding to other frequencie are filled with zeroe to recontruct the entire pectrum with the effective target ime(n ime(n 5b: Recontruction Error 5d: Recontruction Error Fig. 5: Recontructed pule and error he recontructed pule i hown in Fig. 5a when the filter ban had filter and the ADC reolution wa 8. he error between the original pule and the recontructed pule i hown in Fig. 5b. From the two figure, one can oberve that thi cae correpond to the near-perfect recontruction with the maximum recontruction error being le than.. he recontruction error increae a the number of filter i

4 decreaed and a the reolution of the ADC i decreaed. Figure 5c how the recontructed pule for 5 filter and ADC reolution of 5 bit. he recontructed pule in thi cae deviate largely from the original pule and the maximum recontruction error i.4 for an input pule with Vp-p of. In order to quantify the recontruction error, we defined a parameter called the RMS Error Percentage (RMSEP given by (6. RMSEP RMS( OriginalPule RecontructedPule x% V of OrginalPule = (6 pp B. Impact of number of filter and the ADC reolution he variation of the RMSEP for different number of filter and the ADC reolution i hown in Fig. 6. he number of filter i determined by the frequency pacing of the center frequencie of the bandpa filter ( F. he recontruction error curve for different number of filter follow the imilar trend. A the number of filter decreae, the error percentage increae. he bigget increae i oberved when the frequency pacing i changed form MHz to MHz. Note that in thi cae, the number of filter i halved from to. he increae in error percentage i more gradual a the number of filter i decreaed and a the pacing between center frequencie of filter i increaed. RMS Error (% F = MHz F = MHz F = 3MHz F = 4MHz F = 5MHz ADC Reolution (No. of Bit Fig. 6: Recontruction Error v. ADC reolution An intereting trend oberved i that the RMSEP pretty much aturate around 5 bit of ADC reolution except for the cae when F = MHz. herefore, we conclude that an ADC reolution of 5 bit i ufficient for minimum recontruction error from the frequency domain ADC. Alo, we noted in ection., that the ampling rate of thi conventional ADC i only a fraction of the PRI (determined by the number of filter to be ampled. For example, for a PRI of 5 n and filter, the ampling rate for the conventional ADC i = 44 MHz 9, 5 which i eaily realizable with current CMOS technologie. Further, a 5-bit, 44 MHz ADC will only conume a mall fraction of the overall frequency domain ADC power. For the cae when F = MHz, the error percentage decreae ignificantly a the ADC reolution increae and aturate around 7 bit. However, when F = MHz, we need filter and RMSEP of the order of % correpond to near perfect recontruction a hown in Fig. 5a which may not be required in every application. We conclude that an optimal filter pacing would be F = MHz ( filter for our band of interet and an ADC reolution of 5 bit. IV. PRACICAL FILER BANK DESIGN ISSUES A practical implementation of the filter tructure given in Fig. i hown in Fig. 7. he infinite Q bandpa filter hown in Fig. i replaced by a conventional bandpa filter with the tranfer function, but Q in thi cae i aumed + + ( Q to be very high. So that, the overall tranfer function tend to be + ( a in Fig.. Filter tructure for implementing infinite Q filter have been tudied nearly two decade ago [] and thee tructure can be ued for implementing infinite Q filter without having to reinvent the wheel. Implementing, an ideally infinite Q filter ha practical limitation, however, thee tructure can readily achieve very high Q factor (of the order of ~3. Since the unity gain frequency (f of the current CMOS technologie are in the order of GHz [3], bandpa filter with center frequencie in the GHz range can be eaily realized. In order to counter the extreme proce variation in deep ubmicron technologie, the filter center frequency and the bandwidth mut be tunable. + + Q ( + ω Fig. 7: Practical implementation of a Fourier erie coefficient ampler he ideal integrator integrator + ωp p in Fig. i replaced with a practical. A pole at DC would require infinite output impedance. However, output impedance in the order of MΩ can be obtained with current CMOS technologie operating at very low voltage through cacoding or gain-booting technique [4]. he gain in the numerator correpond to the center frequency of the bandpa filter. For our cae, ince the band of interet i from 3 to 5 GHz, the required amplifier gain will alo be in thi range i.e. 3 x 9 5 x 9. Open loop gain of CMOS op-amp are uually in the range of 5 [5] o the gain of thi range can be obtained by cacading open loop op-amp. he main iue i to maintain the tability of the amplifier when operating at uch high gain a well a the variability of the gain. Again, ome tunability hould be

5 introduced into the integrator gain, to counter the proce variation. V. CONCLUSION A imulation tudy of the frequency domain ADC for ampling I-UWB ignal i preented. For the imulation tudy, the pule i recontructed from the pectrum ample and the recontruction error i calculated. Optimum pacing of the center frequencie of the filter ban and the reolution of the ADC i determined by conidering hardware complexity and an acceptable pule recontruction error. Although the ideal integrator and infinite Q bandpa filter may not be realizable in practice, circuit that realize nearly infinite Q filter a well a nearly ideal integrator have been invetigated previouly, and ome of thee tructure can be reued. Baed on our imulation and invetigation on the practical implementation iue, we conclude that frequency domain ampling ADC provide a mean for proceing narrow pule for I-UWB tranceiver without relying on extremely high ampling rate and a large number of bit. ACKNOWLEDGMEN hi material i baed upon wor upported by the National Science Foundation under Grant No REFERENCES [] J. H. Reed (Editor, An introduction to ultra wideband communication ytem, Prentice Hall, 5. [] I. D. O Donnell, and R. W. Broderen, An ultra-wideband tranceiver architecture for low power, low rate, wirele ytem, IEEE ranaction on Vehicular echnology, vol. 54, no. 5, pp September 5. [3] L. Feng, and W. Namgoong, An overampled channelized UWB receiver with tranmitter reference modulation, IEEE ranaction on Wirele Communication, vol. 5, no. 6, pp , June 6. [4] H. J. Lee, D. S. Ha, and H. S. Lee, A frequency-domain approach for all-digital CMOS ultra wideband receiver, IEEE Conference on Ultra Wideband Sytem and echnologie, pp. 86-9, November 3. [5] H. J. Lee, and D. S. Ha, Frequency domain approach for CMOS ultra-wideband radio, IEEE Computer Society Annual Sympoium on VLSI, pp , February 3. [6] S. Hoyo, and B. M. Sadler, UWB mixed-ignal tranform-domain direct-equence receiver, IEEE ranaction on Wirele Communication, pp , Augut 7. [7] S. Hoyo, B. M. Sadler, and G.R. Arce, Analog to digital converion of ultra-wideband ignal in orthogonal pace, IEEE Conference on Ultra Wideband Sytem and echnologie, pp. 47-5, November 3. [8] John G. Proai, Digital communication, McGraw-Hill Higher Education, 4th Ed.. [9] R. Schaumann, and M. E. Van Valenburg, Deign of Analog Filter, Oxford Univerity Pre,. [] R. J. Van de Plache, Integrated analog-to-digital and digital-to-analog converter, Kluwer Academic Publiher, 994. [] A. A. Stocer, Compact integrated tranconductance amplifier circuit for temporal differentiation, Proceeeding of IEEE Conference on Circuit and Sytem, vol., pp. I- I-4, May 3. [] J. C. Mouly, and J. Neiryn, Exhautive earch of infinite Q biquad cell by a PROLOG program, Proceeding of IEEE Conference on Circuit and Sytem, pp , May 986. [3] H. Haan, M. Ani, M. Elmary, Impact of technology caling on RF CMOS, Proceeding of International SOC Conference, pp. 97-, September 4. [4] P. R. Gray, P. J. Hurt, S. H. Lewi, and R. G. Meyer, Analyi and Deign of Analog Integrated Circuit, John Wiley & Son, Inc., 4 th Ed. [5] G. N. Lu, and G. Sou, A CMOS low voltage, high-gain op-amp, Proceeding of European Deign and et Conference, pp. 5-55, Mar 997.