Chapter 5 CONTROL OF CASCADED-MULTILEVEL CONVERTER-BASED STATCOM. 5.1 Control Analysis and Design

Transcription

1 Chapter 5 CONTROL OF CASCADED-MULTILEVEL CONVERTER-BASED STATCOM Thi chapter propoe a new control technique for the CMC-baed STATCOM. The propoed STATCOM model, which wa derived in Chapter 4, i employed in the deign proce. Baed on it characteritic, the propoed control technique i named power decoupling control. Real and reactive power exchanged between the STATCOM and the power network can be controlled independently by the propoed control technique, which i practical in both reactive and real power compenation application. Thi diertation, however, mainly focue on the reactive power compenation. Due to the imbalance problem among DC capacitor voltage in the CMC topology, a DC capacitor voltage balancing-technique, which i named cacaded PWM, i propoed. Theoretically, thi technique can be applied in CMC with any number of voltage level; additionally, it i a ingle-phae approach, and can be realized by a field-programmable gate array (FPGA). The number of controlled capacitor voltage i olely limited by the calculation peed of the DSP and the clock peed of the FPGA. Combining the propoed DC-link-balancing technique with the propoed modeling technique, cacaded-multilevel VSC with any number of voltage level can be modeled a three-level cacaded VSC. The performance and tability of the propoed control technique i validated by both computer imulation and experiment. A caled-down even-level cacaded-baed STATCOM prototype i implemented. A DSP aociated with an FPGA i ued a the main controller. 5. Control Analyi and Deign The three-level cacaded-baed STATCOM i ued a a tarting cae. The control of the STATCOM i deigned in DQ coordinate. The modeling accuracy and control performance are verified by computer imulation and experiment. To validate the propoed DC bu voltage-balancing technique, a even-level cacaded converter i employed a the VSC in the STATCOM ytem. Each phae of the cacaded even-

2 level converter conit of three H-bridge converter whoe DC bue are regulated by the propoed balancing technique. I. Control Law for the Cacaded-Multilevel Converter-Baed STATCOM The propoed STATCOM ytem, a hown in Figure 5-, i compoed of a generic CMC, which i coupled to a power ytem via coupling reactor at the PCC. In the cae of the STATCOM connected to a tranmiion network, the coupling reactor may be repreented by the leakage inductance of the tep-up power tranformer. Figure 5-2 illutrate a ingle-line diagram of the generic CMC-baed STATCOM ytem. The power network i modeled a three ideal voltage ource aociated with their Thevenin impedance. In general, the voltage profile at the PCC varie with network operation, fault and protection cheme. The STATCOM can operate properly and effectively a long a the following two et of key electrical parameter are watchfully controlled: three-phae output current and multiple DC capacitor voltage. The output current determine the amount of reactive power exchanged with the power network. A ingle-line diagram of the STATCOM hown in Figure 5-2 i ued a an example. At thi point, the CMC i aumed to be lole. The STATCOM behave a an adjutable capacitive load, which inject reactive power into the power network, when it output voltage i controlled to be greater than that of the power network. Figure 5-3(a) illutrate phaor diagram of the output voltage, V o, voltage at the PCC, V pcc, and output current, I o, when the STATCOM operate in the capacitive mode. In contrat, a hown in Figure 5-3(b), the output voltage of the STATCOM i controlled to be le than that of the power network in order to aborb reactive power from the network. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM

3 R L V pcca R p L p i pa i a i b R V L pccb R p L p i pb V a N V b v an v bn v cn i c R L V pccc R p L p V c S an S an2 E an _ S v _ a3 an S bn S bn2 E bn _ v _ b3 S an E cn S cn S cn2 _ S an _ v cn Point of Common Coupling i pc S an3 S an4 S bn3 S bn4 S cn3 S cn4 S a2 S a22 E a2 _ v a2 _ S b2 S b22 E b2 _ v b2 _ E c2 S c2 S c22 _ v c2 _ S a23 S a24 S b23 S b24 S c23 S c24 S a S a2 E a _ v a _ S b S b2 E b _ v b _ E c2 S c S c2 _ v c _ S a3 S a4 S b3 S b4 S c3 S c4 Cacaded Multilevel Converter n Figure 5-. Schematic of the propoed cacaded-multilevel converter-baed STATCOM ytem. C Lo Cacaded Multilevel Converter V o i o PCC i p V pcc Power ~ X Sytem X p Figure 5-2. Single-line diagram of cacaded-multilevel converter-baed STATCOM ytem. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM

4 From the phaor diagram of the STATCOM in both operation mode, the amount of average reactive power exchanged at the PCC can be expreed a follow: Q pcc 2 pcc V = 3 X M ( M tan dby ), and Equation 5- M V = 2 N E pcc tan dby, Equation 5-2 where V pcc i the phae voltage at the PCC, X i the coupling impedance, E i the individual DC capacitor voltage, N i the number of H-bridge converter per phae, M i the modulation index, and M tandby i the modulation index for the STATCOM in the tandby mode. In practice, however, the CMC i not lole. Real power imported from the network i required; otherwie, the voltage acro the DC capacitor eventually collape. To regulate the DC capacitor voltage, a mall phae hift or power angle, δ, i introduced between the converter output voltage and the voltage at the PCC, a hown in Figure 5-4. The average regulating power i then derived a a function of the power angle, a follow: P req V pcc M N E = in( δ ), 2 X Equation 5-3 where V pcc i the phae voltage at the PCC, X i the coupling impedance, E i the individual DC capacitor voltage, N i the number of H-bridge converter per phae, M i the modulation index, and δ i the power angle. In ummary, two key control law for the cacaded-multilevel VSC utilized in the STATCOM application are a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 2

5 . the amount of the tranferred reactive power (Var, Q) can be controlled by adjuting the magnitude of the converter output voltage, and 2. the amount of the tranferred real power (Watt, P) can be controlled by adjuting the phae diplacement of the converter output voltage with repect to the voltage at the PCC. Im V pcc V o X i o Re i o (a) Im i o V pcc V o X i o Re (b) Figure 5-3. Operating phaor diagram of the lole three-level converter-baed STATCOM: (a) capacitive mode and (b) inductive mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 3

6 Im V pcc V o δ X i o Re i o Figure 5-4. Operating phaor diagram of non-ideal three-level converter-baed STATCOM. II. Three-Level Cacaded-Baed STATCOM Control Deign The control deign tart with the three-level cacaded converter, which ha the leat number of output voltage level. With only one H-bridge converter per phae, voltage-balancing problem doe not exit in thi cae. The purpoe of tarting with the three-level converter i to verify the correctne and accuracy of the output current and ingle DC capacitor voltage regulation. Thi particular STATCOM ytem, a hown in Figure 5-5, i formed by a three-level cacaded converter that i coupled to a power ytem by the coupling reactor at the PCC. C Lo Three-level Cacaded Converter V o i o PCC V pcc ~ X Power Sytem Figure 5-5. Single-line diagram of a STATCOM ytem utilizing the three-level cacaded converter. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 4

7 The chematic of the completed power tage of the three-level cacaded-baed STATCOM i hown in Figure 5-5. Each phae of the cacaded converter conit of an H-bridge converter, which can generate three level of output voltage, i.e., E, and E. R L V pcca R p L p i pa i a i b R V L pccb R p L p i pb V a N V b v an v bn v cn i c R L V pccc R p L p V c S a S a2 E a _ v _ a S an S b S b2 E b _ S an v b _ S c S c2 E c _ v _ c S an Point of Common Coupling i pc S a3 S a4 S b3 S b4 S c3 S c4 n Cacaded Three-level Converter Figure 5-6. Schematic of the three-level cacaded-baed STATCOM ytem. R E /3 E ~ _ ~ i E R L /3 3C ~ ~ Dd id dd Id ~ ~ D i d I q q q q ~ D d E ~ D d E ~ D q E ~ D q E ~ i d v ~ d _ ~ i q v ~ q _ R R L L ωl i ~ q ωl i ~ d v ~ pccd v ~ pccq Figure 5-7. Small-ignal model of the three-level cacaded-baed STATCOM. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 5

8 Baed on the propoed HBBB dicued in Chapter 3, the electrical parameter of the cacaded three-level converter and the power network are deigned a hown in Table 5-. TABLE 5-. SPECIFICATION OF THE STUDIED SYSTEM. Three-Level Cacaded Converter Individual DC Bu Voltage 2 V ± % Total DC Bu Voltage 2 V ± % Rated RMS Reactive Current 25 A Capacitor Impedance Individual Switching Frequency/ Equivalent Switching Frequency Power Sytem Configuration Coupling Reactor Impedance PCC Line Voltage (2.5m-j/(ω.5mF)) Ω khz/ 2 khz Balanced Three-Phae Three-Wire (3m-jω 35µH) Ω 2 V A. Sytem Tranfer Function From the generic CMC-baed STATCOM model derived in Chapter 4, with one H-bridge converter per phae, the implified mall-ignal model for the three-level cacaded-baed STATCOM can be depicted a hown in Figure 5-7. Due to the three-phae three-wire configuration, the -channel i omitted in thi cae. Baed on the mall-ignal model of the three-level cacaded-baed STATCOM, five key tranfer function ued for control deign are derived a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 6

9 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 7 Control-to-Output-Current Tranfer Function, G idd and G iqq ) ( ~ ~ 2 = = P P Z idd d d idd Q S S S K d i G ω ω ω, Equation 5-4 where ( ) 2 2 idd L R NER K ω =, ( ) R L R Q ω =, ( ) P L L R 2 2 ω ω =, and z L R = ω, and ) ( ~ ~ 2 = = P P Z iqq q q iqq Q S S S K d i G ω ω ω, Equation 5-5 where ( ) 2 2 iqq L R NER K ω =, ( ) R L R Q ω =, ( ) P L L R 2 2 ω ω =, and z L R = ω.

10 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 8 Control-to-Cro-Coupling-Output-Current Tranfer Function, G iqd and G idq ~ ~ 2 = = P P iqd d q iqd Q S S K d i G ω ω, Equation 5-6 where ( ) 2 2 iqd L R LNE K ω ω =, ( ) R L R Q ω =, ( ) P L L R 2 2 ω ω =, and z L R = ω. Likewie, ~ ~ 2 = = P P idq q d idq Q S S K d i G ω ω, Equation 5-7 where ( ) 2 2 idq L R LNE K ω ω =, ( ) R L R Q ω =, ( ) P L L R 2 2 ω ω =, and z L R = ω.

11 Output-Current-to-DC-Bu-Voltage Tranfer Function, G Eid G Eid = ~ E ~ i d K = S ω P Eid 2 S ( ω Z S Qω ) P, Equation 5-8 where K Eid = D ωl q D d D D q N d R D D NL Q =, dj qj, 2 3CR ω P = D d D q 3CL N D qω R, and ω z =. D L d Baed on the deigned electrical parameter, Bode plot of the three key ytem tranfer function, i.e., G idd, G iqq, and G ied, are hown in Figure 5-8 and Figure 5-9. Very high peak appear at 6 Hz in G idd and G iqq becaue of the inignificant tray reitance in the coupling inductor and DC capacitor. Thi ytem i conidered a a high-q or a very-low lo ytem. The tranfer function G ied behave a the integration due to the capacitive dominance in the DC link. From thee three Bode plot, their phae are contant at the high-frequency range becaue the non-ideal factor are not taken into account. Three major non-ideal factor include the witching frequency and the delay of the control and data-acquiition ytem. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 9

12 8 8 ( ) gain G idd ( fi ( )) 6 4 ( ) gain G iqq ( fi ( )) f( fi) f( fi) 5 5 ( ) phae G idd ( fi ( )) ( ) phae G iqq ( fi ( )) ffi ( ) f( fi) (a) (b) Figure 5-8. Ideal open-loop tranfer function of the control-to-output current in the (a) D-channel, G idd, and (b) Q-channel, G iqq. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 2

13 5 ( ) gain G Eid ( fi ( )) f( fi) 5 ( ) phae G Eid ( fi ( )) ffi ( ) Figure 5-9. Ideal open-loop tranfer function of the D-channel current-to-dc-capacitor voltage, G ied. B. Effect of Variou Delay on the Tranfer Function In practice, three important delay embedded in both the power tage and the controller mut be conidered: the witching, the calculation and the tranducer delay. Switching Delay Limited by the ytem operation condition and it thermal capability, the recent high-power emiconductor device can witch in a range of everal hundred to a few kilohertz. The witching delay i, therefore, the mot important factor of concern in the high-power electronic control deign. To further explain how to determine the witching delay for the CMC, an H-bridge converter, a hown in Figure 5-, i ued a an example. An H-bridge converter baically conit of two phae leg. Each phae leg comprie two complementary witche. The relationhip of the total output voltage and individual phae-leg voltage i imply expreed a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 2

14 V LR ( t) = V ( t) V ( t). LN RN Equation 5-9 Figure 5- how the digital PWM ynthei for an H-bridge converter. The command duty cycle i compared to a linear lope; the interection determine the witching event. Each phae leg i aumed to witch at /T Hertz. The left phae leg i controlled by the poitive duty cycle, wherea the right phae leg i controlled by the negative duty cycle, which i out of phae with the poitive duty cycle. The duty cycle i updated every half-cycle. In other word, each phae leg repond to the duty cycle every half-cycle and ha a half-cycle delay time. In Figure 5-, the duty cycle i updated at time T and.5 T. Although V LR (t) ha twice the witching frequency compared to each phae leg, the duty cycle i till updated every half-cycle. The double witching frequency provide improvement in the yntheized output waveform, but it doe not horten the delay time. Since the output of the CMC i the ummation of N individual H-bridge converter, it witching delay i then: T d _ w ( t). N f = 2 Equation 5- E - V LN (t) V RN (t) V LR (t) - N Figure 5-. Two phae leg forming an H-bridge converter. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 22

15 D(t) V LN (t) D T D. 5T V RN (t) t() D T V AN (t) D. 5T t() t() T.5T 2T Figure 5-. PWM-generation technique for the H-bridge converter. Calculation Delay Thi delay i baically a function of the proceor ued in the controller. Due to it highpeed arithmetic unit, the recent floating-point DSP i widely employed in real-time control application. In thi diertation, a 33MHz DSP from Texa Intrument (TI), TMS32D67, which can perform 8 mega floating-point operation per econd (MFLOPS), i programmed to finih each feedback calculation in µ. The calculation delay i thu: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 23

16 T d _ cal ( t) = µ. Equation 5- Tranducer Delay In general, feedback parameter in a digital-baed control ytem are acquired by analog-todigital converter (ADC). The tranducer delay i alo known a the ampling delay, which i indirectly proportional to the ampling frequency of the ADC. An ADC from TI, THS26, i ued a the data converter in thi diertation. It ha 2 bit of reolution and a converion rate of 6 megaample per econd (MSPS). The tranducer delay i therefore 67 n. T d _ ADC ( t) = 67 n. Equation 5-2 Total Delay Baically, the total delay i the ummation of thee three previouly dicued delay. Due to the dominance of the witching delay, the total delay time can be approximated by the witching delay, a hown in Equation 5-3. T d = T T T T. d _ w d _ cal d _ ADC d _ w Equation 5-3 Thi delay mainly affect the phae delay of the loop gain, and can be modeled in Laplace form a follow: ( ) T d S τ S = e. Equation 5-4 By taking into account the ytem delay, the new open-loop tranfer function, G idd, can be plotted a hown in Figure 5-2. With a witching frequency of khz, the phae of G idd rapidly roll off at above 7 Hz. Obviouly, thi ignificantly limit the bandwidth of the feedbackcurrent loop gain. Baed on the controller proceor and power tage of the converter, the witching delay ha the mot ignificant effect on the control deign. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 24

17 8 ( ) gain G idd ( fi ( )) ( ) gain G idd_delay ( fi ( )) f( fi) 2 ( ) phae G idd ( fi ( )) ( ) phae G idd_delay ( fi ( )) f( fi) Figure 5-2. Comparion of the tranfer function, G idd, without and with delay. C. Cro-Coupling Effect To how the cro-coupling component between the D-channel and the Q-channel, the differential equation of the output current of the STATCOM i rewritten in Equation 5-5: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 25

18 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 26 = ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ i i i L R L R L R v v v L D D D L E d d d L E i i i dt d q d vpcc vpccq vpccd q d q d q d ω ω. Equation 5-5 From Equation 5-5, in the D-channel, a current-controlled voltage ource i a function of the current i q, while, in the Q-channel, a current-controlled-voltage ource i a function of crocoupling current, i d. The amplitude of both dependent voltage ource can be expreed in Equation 5-6: dq i q L v = ω, and qd i d L v = ω. Equation 5-6 To how the cro-coupling effect, the Bode plot of G idd and G iqd are illutrated in Figure 5-3. Obviouly, at frequencie lower than the corner frequency, which i roughly 6 Hz, the gain of G iqd dominate that of G iqd. In other word, by controlling duty cycle d, the Q-channel current tend to react more than the D-channel current doe, which i undeirable. In order to alleviate the cro-coupling effect, the deigned croover frequency of the current cloed-loop gain hould be kept higher than the corner frequency, where the gain of G idd i higher than that of G iqd. To further improve the loop repone, the decoupling technique i applied in the current loop gain, a dicued in the following ection.

19 ( ) gain G idd ( fi ( )) ( ) gain G iqd ( fi ( )) f( fi) 2 5 ( ) phae G idd ( fi ( )) ( ) phae G iqd ( fi ( )) f( fi) Figure 5-3. Bode plot of control-to-output current, G idd and G idq. D. Control Strategy In general, the PCC i a critical voltage bu in the power network that require the pecial attention. The voltage at the PCC are, therefore, monitored and aigned a the reference for the propoed control ytem. Normally, a three-phae parameter in the ABC coordinate can be repreented by a vector in the ABC pace. A poitive-equence phae voltage at the PCC, V pcc (t), for example, i repreented a a voltage vector expreed in Equation 5-7. Figure 5-4 illutrate an intantaneou vector of the voltage at the PCC at time t, (t), in the ABC pace. For a balanced three-phae ytem, the phae-voltage vector at the PCC rotate along the dotted V pcc Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 27

20 line with an angular velocity of ω. Baed on the plane created by the (t) rotation, a new coordinate called αβγ i defined a follow:. the α-β plane i aligned with the urface A vpcc, and 2. the γ-axi i perpendicular to the urface A vpcc. V pcc V pcc ( t) = v v v pcca co( ωt) 2π co( ωt ) 3 2π co( ωt ) 3 pccb pccc Equation 5-7 To be clearly hown, the pace a hown in Figure 5-4 i depict in Figure 5-5 by viewing it perpendicularly to urface A vpcc. Since the αβγ coordinate i tationary with repect to the ABC coordinate, the projection of vector (t) in the αβγ coordinate i till time-variant. To achieve V pcc a time-invariant vector, another new coordinate i then introduced, and i named DQ. In general, the αβγ and DQ coordinate are identical except that the DQ coordinate rotate around the -axi at the peed of the reference vector. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 28

21 γ C A vpcc (,,) ω β α B V pcc (t) A Figure 5-4. PCC voltage vector of a balanced three-phae ytem, plotted in the ABC pace. C Q β V pcc (t) D ω γ,o θ α A B Figure 5-5. Vector of PCC voltage aligned with the D-axi in the DQ pace. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 29

22 From Figure 5-5, if the DQ coordinate rotate with the ame angular velocity of that of V pcc (t), vector V pcc (t) then become tationary in the DQ pace. In other word, the behavior of balanced, three-phae, time-variant parameter in the ABC coordinate can be imply repreented by two time-invariant parameter in the DQ coordinate. Park tranformation matrix,, i a tool for tranferring parameter in the ABC into DQ coordinate. T dq / abc To make a phyical meaning for the control ytem, V pcc (t) i aligned with the D-axi (direct axi). By multiplying Park tranformation matrix with (t), the v pccq and v pcc become zero, while v pccd i roughly.225 time the peak voltage at the PCC in the ABC coordinate. V pcc v v v pccd pccq pcc = T dq / abc v v v pcca co( ωt) 2π co( ωt ) = 3 2π co( ωt ) 3 pccb pccc 3 2 v pcca Equation 5-8 By applying thi rule, the parameter in the DQ coordinate in line with the D-axi provide real component, wherea the quadrature component repreent the reactive component. Therefore, the relationhip between the intantaneou three-phae power component in the DQ coordinate can be expreed in Equation 5-9. The amount of real power exchanged between the STATCOM and the power grid i the product of the D-channel voltage at the PCC and the D- channel output current of the STATCOM. Thi fraction of real power i uually ued to regulate the DC capacitor voltage. On the other hand, the amount of reactive power exchanged between the STATCOM and the power grid i the product of the D-channel voltage at the PCC and the Q- The Park tranformation matrix derivation i hown in Appendix A. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 3

23 channel output current of the STATCOM. Thi reactive power i the key component to be controlled. P( t) = 2 V pccd I d, and Q( t) = 2 V pccd I q, or Equation 5-9 P( t) = 2 V pcc I O co( ξ ), and Q( t) = 2 V pcc I O in( ξ ). Equation 5-2 i q (t) Q i O (t) ω ξ i d (t) v pcc (t) D Figure 5-6. Phaor diagram of the alignment of key control parameter. Thi obviouly complie to the control law preented earlier, i.e., the amount of tranferred reactive power (Var, Q) can be controlled by adjuting the magnitude of the converter output voltage, and the amount of tranferred real power (Watt, P) can be controlled by adjuting the phae diplacement of the converter output voltage with repect to the voltage at the PCC. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 3

24 E. Feedback-Controller Deign Figure 5-7 how the complete propoed control block diagram for the three-level cacadedbaed STATCOM ytem. The main objective of the feedback controller i to regulate the Q- channel current following it command a fat a poible. E * Σ _ H Ed i d * Σ _ H id ωl/e Σ _ d d * G idd Σ I d Controller G idq G Eid E G iqd i q * Σ _ H iq Σ ωl/e G iqq d * q Σ Cacaded Three-Level STATCOM Model I q Cacaded Three-Level Baed STATCOM Sytem Figure 5-7. Control block diagram. Thi dicuion will begin with the D-channel. In the D-channel, there are two main control loop: the internal output current loop (I d -loop) and the external voltage loop (E-loop). The output of the voltage loop i the reference for the I d -loop. In the E-loop, the three DC capacitor voltage are averaged and compared to the reference, which i fixed at 2 V. The error i compenated by the voltage compenator, H E. The output of H E i then ued a the command for the I d -loop. For the I d -loop, the I d command i compared with the feedback I d, and it error i the input of the current regulator, H id. Finally, the output of the current regulator i the D-channel duty cycle command. In the Q-channel, the I q command i generated by an external control, which i obtained either from the control peron or the automatic controller. The I q command i compared with the Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 32

25 feedback I q, and the error i compenated by the current compenator, H iq, whoe output i the Q- channel duty cycle command. The control proce tart with the internal control loop. The current compenator H id and H iq are firt deigned to meet the croover frequency and phae margin requirement. In the D- channel, the voltage compenator H Eid i then deigned baed on the new current-loop gain. Deign of Current Compenator, H iq and H iq Baed on the deigned power tage parameter, the Bode plot of the open-loop tranfer function G idd and G iqq, aociated with the delay, are hown in Figure 5-8. Becaue the characteritic of G idd and G iqq are identical, only G idd i ued throughout the current-compenator deign proce gain( G idd ( fi ( ))) f( fi) gain( G iqq ( fi ( ))) f( fi) 2 ( ) phae G idd ( fi ( )) ( ) phae G iqq ( fi ( )) f( fi) f( fi) (a) (b) Figure 5-8. Open-loop control-to-output-current tranfer function aociated with delay in the (a) D-channel, G idd (b) Q-channel, G iqq. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 33

26 Due to the Nyquit criteria, the deigned croover frequency of the current loop hould not be higher than half of the effective witching frequency, which equal twice the individual phae-leg witching frequency or 2 khz in thi cae. Baically, an average model i capable of predicting the behavior of it witching model from DC up to half of the effective witching frequency. By deigning the croover frequency above thi pecific witching frequency, the tability prediction of the ytem i theoretically invalid. From the Bode plot hown in Figure 5-8, the loop gain of the compenated G idd at the low-frequency range hould be a high a poible, uch that the output i well regulated at DC and at frequencie below the croover frequency. Among well-known compenator, the lag compenator or the proportional-plu-integral (PI) i the bet candidate baed on it implicity and reliability. A general tranfer function of the PI compenator H PI (S) i given in Equation 5-2, and it magnitude and phae aymptote are hown in Figure 5-9. To achieve a zero teady-tate error for the current-loop gain, an inverted zero of the PI compenator i added at frequency f L. Moreover, if f L i ufficiently below the loop croover frequency, the original phae margin i not diturbed by the PI compenator. H PI ω = L ( S) H PI S Equation 5-2 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 34

27 ( ) gain H PI ( fi ( )) db/decade f L H PI ( ) phae H PI ( fi ( )) f( fi) f L / f L 45 /decade f( fi) Figure 5-9. Bode plot of the PI compenator tranfer function. Alternatively, the PI compenator can be expreed by it two ub-function, i.e., proportion and integral, a follow: H Ki ( S) = K p, S PI Equation 5-22 where K p = H PI, and Ki = H PI ωl. According to the Bode plot of G idd, a hown in Figure 5-8, a couple of undeirable factor complicate the deign of compenator H id (S), i.e., very high Q in the gain and that the phae quickly roll off in the vicinity of the deigned croover frequency. With the compenator, the cloed-loop tranfer function of the D-channel current can be expreed a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 35

28 T id ( S) = H ( S) G ( S). id idd Equation 5-23 After the optimization proce, the bet-deigned parameter for the PI compenator are given in Table 5-2. The current-loop gain i plotted, a hown in Figure 5-2, to verify it tability. The deired croover i elected to be a high a poible, but mut be le than khz, which i half of the effective witching frequency. Due to the evere witching delay, the deigned croover frequency i 2 Hz, with reaonably large phae margin of 5 degree. The characteritic of current loop gain T id (S) are lited in Table 5-2. Due to having a tranfer function identical to that of the D-channel current, the Q-channel-current loop compenator H iq (S) i deigned, and it cloed-loop magnitude and phae are plotted in Figure 5-2. TABLE 5-2 DESIGNED PI COMPENSATOR PARAMETERS AND CURRENT LOOP GAIN CHARACTERISTICS. Parameter Value PI Compenator, H id (S) K p K i Loop Gain T id (S) Characteritic Croover Frequency (Hz) 2 Phae Margin (degree) 5 Gain Margin (db) 7.7 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 36

29 5 ( ) gain T d ( fi ( )) ( ) gain G idd ( fi ( )) -7.7 db 5 ( ) phae T d ( fi ( )) ( ) phae G idd ( fi ( )) 2 Hz ffi ( ) ffi ( ) Figure 5-2. Bode plot of the open-loop control-to-d-channel-current tranfer function (dahed line) and the D-current loop gain (olid line). Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 37

30 5 ( ) gain T iq ( fi ( )) ( ) gain G iqq ( fi ( )) 5 ( ) phae T iq ( fi ( )) ( ) phae G iqq ( fi ( )) ffi ( ) f( fi) Figure 5-2. Bode plot of the open-loop control-to-q-channel-current tranfer function (dahed line) and the Q-current loop gain (olid line). Deign of DC Capacitor Voltage Compenator, H Ed With the D-channel current loop cloed, the new tranfer function, i.e., the reference currentto-dc-voltage tranfer function, T Eid (S), i a follow: T Eid E Tid ( S) ( S) = = GEid ( S), i * T ( S) d id Equation 5-24 where G Eid (S) i open-loop output-current-to-dc-bu-voltage tranfer function, and T id (S) i the D-channel current-loop gain. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 38

31 E * Σ _ H E i d * T id /( T id ) I d G Eid E Figure Block diagram of the DC voltage loop. The Bode plot of tranfer function T Eid (S) i hown in Figure A compenator i needed to improve the croover frequency of T Eid (S), which i too low. Again, the PI compenator i capable of doing o. The D-channel voltage loop gain, T Ed (S), can be expreed a follow: T Ed ( S) = H ( S) T ( S), Ed Eid Equation 5-25 where H Ed (S) i the PI compenator for the D-channel voltage loop. The croover frequency hould be a high a poible; however, it need to be limited at a frequency that i reaonably lower than the croover frequency of the current-loop gain in order to avoid interference between thee two control loop. In thi deign, the croover frequency of the voltage-loop gain i placed at 2 Hz, which i ten time lower than that of the current-loop gain. The correponding phae margin i 57 degree. Thi large phae margin i achieved due to relatively large capacitance of the DC capacitor. The compenated voltage-loop gain T Ed (S) i plotted in Figure In ummary, the deigned compenator parameter and characteritic of the DC voltage-loop gain are lited in Table 5-3. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 39

32 5 ( ) gain T Eid ( fi ( )) 5 ( ) phae T Eid ( fi ( )) f( fi) ffi ( ) Figure Bode plot of the reference current-to-dc voltage tranfer function, T Eid (S). TABLE 5-3. DESIGNED PI COMPENSATOR PARAMETERS AND VOLTAGE-LOOP GAIN CHARACTERISTICS. Parameter Value PI Compenator, H Ed (S) K p.75 K i 55 Loop Gain T Ed (S) Characteritic Croover Frequency (Hz) 2 Phae Margin (degree) 58 Gain Margin (db) 53.8 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 4

33 5 5 ( ) gain T Ed ( fi ( )) db f( fi) 2 2 Hz ( ) phae T Ed ( fi ( )) ffi ( ) Figure Bode plot of cloed-loop D-channel voltage loop, T Ed (S). F. Simulation Reult of the Average Model with the Deigned Control To verify the tability and performance of the propoed control parameter, the average model of the three-level cacaded-baed STATCOM with the deigned feedback control i imulated. At the PCC, the power exchange between the STATCOM and the power network i defined, and i divided into the following three mode for the particular imulation:. tandby mode i the mode in which the STATCOM generate zero real and reactive power (P = Watt and Q = Var), Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 4

34 2. inductive mode i the mode in which the STATCOM aborb the reactive power from the power network (at full inductive mode, P = Watt and Q = -.5 MVar), and 3. capacitive mode i the mode in which the STATCOM inject the reactive power into the power network (at full capacitive mode, P = Watt and Q =.5 MVar). In thi imulation, the STATCOM i commanded to operate in the following four mode:. at time to 2 m, the STATCOM operate in the tandby mode, I q = A, 2. at time 2 m to 4 m, the STATCOM operate in the full inductive mode, I q = 265 A, 3. at time 4 m to 6 m, the STATCOM till operate in the inductive mode, except with a voltage ag at the PCC of 3% intead of the normal voltage, and 4. after 6 m, the STATCOM operate in the full capacitive mode, I q = -265 A. The command I q at the full load i calculated from the full-load output current in the ABC coordinate. The relationhip between the AC parameter in the DQ and ABC coordinate yield the following: i Q 3 ( t) = ia _ pk ( t), 2 Equation 5-26 where i A-pk (t) i the peak of the output-phae current. Figure 5-25 how the imulation reult of the STATCOM operating in thee four mode. The reult indicate that the STATCOM tably operate for the entire range. The Q-channel output current cloely follow the command. The average DC capacitor voltage i alo regulated fairly well. At each tranition period, the detail of the imulation reult are dicued and verified. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 42

35 Figure Tranient and teady-tate repone of the propoed average model of three-level cacaded-baed STATCOM with the deigned feedback control operating in tandby mode, full inductive mode, inductive mode under 3% voltage ag at the PCC and capacitive mode. Tranition : from Mode to Mode 2 At time 2 m, the STATCOM i commanded to abruptly change it operation mode from tandby to full inductive mode by adjuting the I q command from to 265 A. Due to the aigned current direction during the modeling procedure, the output current lead the V PCC by 9 in the inductive mode and lag the V PCC by 9 in the capacitive mode. In mode 2, the imulation reult verifie that phae-a output current, i a, lead V PCC by 9. The overhoot of I q i 32%. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 43

36 Figure The STATCOM repond to the tep change from tandby mode (mode ) to full inductive mode (mode 2) at.2 S. Tranition 2: from Mode 2 to Mode 3 At thi particular tranient, while the STATCOM i commanded to aborb full reactive power from the power grid, at 4 m, the three phae voltage at the PCC drop to 7% of the rated line-to-line voltage, which i 47 V RMS. Figure 5-27 illutrate the imulated tranient of the STATCOM. The command I q i et at the full inductive mode for the entire tranition. The current I q very fat repond to the tranient in the PCC voltage, and ettle in the 5%-error range in 5 m. The imulation reult alo how that the phae-a output current indicate the tranient and goe to teady tate very quickly. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 44

37 Figure At.4 S, the STATCOM operate in full inductive mode (mode 2) and repond to the 3% ag in the voltage at the PCC (mode 3). Tranition 3: from Mode 3 to Mode 4 Thi tranition i conidered a the wort-cae operation. Figure 5-28 how the imulation reult. The STATCOM i commanded to abruptly witch from aborbing full inductive current to generating full capacitive current. The current I q follow it command with 32% overhoot, and ettle down to the 5%-error command in le than 5 m, which i about one-third of a line cycle. Since the ame feedback parameter are ued, the magnitude of the overhoot matche that in tranition. In other word, no matter how much the tep command i changed, the percentage of overhoot i alway contant. The imulation reult confirm thi. Moreover, the phae-a output current lead the voltage V PCC in mode 3 and lag V PCC in mode 4; thee are conitent with the STATCOM operating in the inductive and capacitive mode, repectively. Due to the witching delay introduced in the control ytem, phae lag are noticed in both i q and i a. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 45

38 Figure The STATCOM repond to the tep change from full inductive mode (mode 3) to full capacitive current (mode 4). G. Propoed Control Sytem for Three-level Cacaded-Baed STATCOM After being verified by the average model, the feedback-parameter acquiition mut be modified before being applied in the real electrical circuit of the STATCOM in which all parameter are in the ABC coordinate. Figure 5-29 preent the completed block diagram of the propoed controller for the three-level cacaded-baed STATCOM. Addition to the control deigned for the average model of the three-level cacaded-baed STATCOM are a follow: a Park tranformation, an invered Park tranformation, a PWM generator and a phae lock loop (PLL). All feedback parameter are meaured by uing the ignal tranducer. Originally, thee feedback ignal are in ABC coordinate. With the propoed control technique, all ignal are real-time tranferred into DQ domain by Park tranformation matrix 2. The PLL i the tool 2 Derivation of the pecific verion of the Park tranformation matrix ued in thi diertation i hown in Appendix A. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 46

39 that i ued to acquire the information for ytem ynchronization, which i important for the ynchronou-control technique. The input of the PLL are the three-phae voltage at the PCC, and the PLL output i the phae information of the voltage at the PCC in the form of coine and ine function. The Park and it invered tranformation matrice are baed on the poitiveequence, three-phae ytem. Meaurement Parameter E c E b E a i a i b V pcca V pccb V pccc E Σ /3 _ Σ E ref co(θ) - abc H E dqo in(θ) PLL i dref i d i q H id H iq ωl /E ωl /E d d _ d q dqo abc d a d b d c co(θ) in(θ) Three-level SPWM Switching Signal for the power tage i qref Command Figure Completed block diagram of the propoed controller for the three-level cacadedbaed STATCOM. Since an average DC voltage-control technique i propoed in the control ytem, the threephae DC capacitor voltage, E a, E b and E c, are intantaneouly averaged, and thi average value i ued a the feedback-control parameter. After all DQ parameter are calculated, the control proce i what wa preented in the feedback-control deign ection. Yet again, the main objective of the control ytem are to make the STATCOM repond to the reactive current command, i q, a well a to regulate all three DC capacitor voltage. To alleviate the crocoupling effect between the D and Q channel, the decoupling technique i adopted. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 47

40 The product of the feedback control are the duty cycle in the DQ coordinate: D d, D q and D. Since the STATCOM i connected to the three-phae, three-wire power network, the zero channel can therefore be omitted. Conequently, D i et to zero. To be able to control the power tage of the STATCOM, the duty cycle mut be tranferred back into the ABC coordinate. Once the duty cycle in ABC coordinate, which are D a, D b and D c, are calculated, thee three duty cycle are ued a the input of the PWM generator in order to produce the proper witching ignal for the power tage. H. Simulation Reult of the Cacaded Three-Level STATCOM with the Deigned Controller Baed on the mall-ignal model of the three-level cacaded-baed STATCOM, the feedback-control parameter are deigned, a dicued in the feedback-control deign ection, and are applied in the completed electrical model of the propoed STATCOM in which the ideal witch and diode model are utilized. In addition, all paraitic component and power-tage loe are taken into account in the circuit. Comparion of Simulation Reult of the Average and Electrical Model To verify the accuracy of the average model and the performance of the propoed control ytem, a et of imulation, which ue the STATCOM power electronic model a the reference, i performed. In the firt imulation, the STATCOM i commanded to abruptly go from the tandby mode to the full capacitive mode, and it imulation reult are hown in Figure 5-3. Three major parameter are compared between the reult from the average model and thoe from the electrical model: the Q-channel output current, I q, the average DC capacitor voltage, e_avg, and the output current of phae A, I a. Due to the witching action in the electrical model, the witching ripple appear in the imulation reult. In thi cae, the inignificant error of the overhoot in I q and e_avg are.7% and.25%, repectively. In Figure 5-3(c), the reult how that by neglecting the witching ripple, the dynamic repone of the phae-a output current can be very well repreented by that of the average output current of phae A. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 48

41 .7% error (a).25% error (b) (c) Figure 5-3. Comparion between average model and electrical model of the STATCOM operating in the tandby to full inductive mode: (a) I q repone, (b) average DC capacitor voltage, and (c) output current. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 49

42 2.5% error (a).7% error.2% error (b) (c) Figure 5-3. Comparion between average model and electrical model of the STATCOM operating in the full capacitive to full inductive mode: (a) I q repone, (b) average DC capacitor voltage, and (c) output current. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 5

43 The econd imulation i for the wort-cae operation in which the STATCOM i controlled to repond to the tep command from full capacitive to full inductive mode. The imulation reult are hown in Figure 5-3. In thi cae, the error of the overhoot in of I q and e_avg are 2.5% and.2%, repectively. Again, the reult how that, by neglecting the witching ripple, the dynamic repone of the phae-a output current can be predicted by that of the average output current of phae A. In concluion, the reult indicate that the propoed average model i very accurate and can very cloely predict the dynamic behavior of the three-level cacaded-baed STATCOM. Simulation Reult of the Electrical Model with the Propoed Controller To further verify the tability and performance of the propoed STATCOM controller, more continuou operation mode are imulated. The STATCOM i commanded to operate in the following ix mode:. at time to m, the STATCOM operate in the tandby mode, I q = A, and Ia = A RMS, 2. at time m to 3 m, the STATCOM operate in the full inductive mode, I q = 265 A, and Ia = -25 A RMS, 3. at time 3 m to 5 m, the STATCOM operate in the full capacitive mode, I q = -265 A and Ia = 25 A RMS, 4. at time 5 m to 7 m, the STATCOM again operate in the full inductive mode, I q = 265 A, and Ia = -25 A RMS, 5. at time 7 m to 9 m, the STATCOM operate in the half inductive mode, I q = 83 A, and Ia = -625 A RMS, and 6. after 9 m, the STATCOM finally return to the tandby mode. The imulation reult of the STATCOM operating in thee ix mode are illutrated in Figure A hown, the STATCOM tably operate for the entire range. In general, the Q- channel output current, i q, very cloely follow it command. The average DC voltage i alo Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 5

44 regulated fairly well. Five intereting tranition occur in thi imulation. Detailed imulation reult are dicued and verified. Figure Tranient and teady-tate repone of the three-level cacaded-baed STATCOM with the propoed feedback controller, operating in tandby mode, full inductive mode, full capacitive mode, full inductive mode, half capacitive mode and tandby mode. The detail of the tranition from mode 2 to 3 i hown in Figure 5-33(a). The STATCOM operation tranfer from the full inductive to the full capacitive mode. The current i q very quickly follow the command. The current i a imultaneouly tranfer from 9 leading to 9 lagging Vpcc in le than half a line cycle. The reult alo how that all three DC capacitor voltage are very well regulated during the tranient and teady tate. The detail of the STATCOM repone to the command to go from full capacitive to full inductive mode i Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 52

45 illutrated in Figure 5-34(b). From the imulation reult, the voltage ripple of the DC capacitor in the inductive mode i lightly le than that of the capacitive mode due to the different amount of average current flowing into the DC capacitor. A mentioned in the converter modeling proce, the capacitor current i a product of the output current and the duty cycle of the converter. Baically, the duty cycle in the inductive mode i le than that in the tandby mode, wherea the duty cycle in the capacitive mode i greater than that in the tandby mode. In other word, the duty cycle of the converter during the inductive mode i alway le than that in the capacitive mode. A a reult, with the ame amount of output current, the average amount of the DC capacitor current during the inductive mode i alway le than that of the capacitive mode. Therefore, the capacitor need to be deigned to handle the wort-cae voltage ripple, which occur when the STATCOM operate in the capacitive mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 53

46 (a) (b) Figure The STATCOM repond to the tep change (a) from full inductive mode (mode 2) to full capacitive mode (mode 3) at.3 S, and (b) from full capacitive mode (mode 3) to full inductive mode (mode 4) at.5 S. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 54

47 (a) (b) Figure The STATCOM repond to the tep change (a) from full inductive mode (mode 4) to half capacitive mode (mode 5) at.7 S, and (b) from half capacitive mode (mode 5) to tandby mode (mode 5) at.9 S. At.7, the STATCOM i commanded to generate a half-rated reactive current in mode 5 following mode 4. The imulation reult for thi tranition are hown in Figure 5-34(a). The Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 55

48 current i decreaed from full to half rating following the command. All three capacitor voltage go to the teady tate in about.2. The lat tranition at.9 i hown in Figure 5-34(b). The STATCOM i finally commanded to go back to the tandby mode in which it exchange no power with the power network. The average STATCOM output current become zero, although the witching ripple in the current till exit. The three capacitor voltage go back to the reference with no ripple, which indicate that there i no reactive power circulating in the capacitor. Figure 5-35 how voltage and current waveform for a tranient period of the STATCOM tranferring from full capacitive to full inductive mode. The phae-a output voltage of the STATCOM i almot alway in phae with the voltage at the PCC. A mall phae hift i, however, applied when the capacitor voltage need to be adjuted. In addition, the reult verify that all three capacitor voltage and three output current are very well regulated. According to the control deign criteria, the repone of the DC-voltage loop i about time lower than that of the output-current loop. A a reult, the DC capacitor voltage go to the teady tate approximately time later than the output current do. Full Capacitive Full Inductive Figure Waveform of the STATCOM ytem tranitioning from the full capacitive to full inductive mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 56

49 I. Experimental Validation To firmly verify the propoed STATCOM model and feedback controller, a real-time IGBTbaed STATCOM tetbed 3 i implemented. The STATCOM tetbed i baically compoed of three part: the IGBT-baed CMC, the DSP-baed controller, and the paive component. The chematic of the tetbed i hown in Figure The reactive current command i fed into the controller though the uer interface. The feedback parameter are meaured by the analog tranducer, and are converted to digital domain by the ADC. The feedback-control routine i coded and downloaded to the program memory of the DSP. AC Source X P V pcc Auto tranformer X S I out Cacaded Multilevel Converter DSP-Baed Controller E Uer Interface Figure The chematic of the STATCOM tetbed. Tetbed Power Stage Operating Parameter The operating point of the tetbed i elected baed on the limitation of the laboratory facilitie. The main witching device i the IGBT in which a freewheeling diode i internally connected in parallel. To properly verify the propoed model, the contraint of the tetbed 3 Detail of the STATCOM tetbed are given in Appendix B. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 57

50 power tage are kept identical to thoe of the high-power ytem. Thoe parameter are a follow:. the witching frequency, 2. the dead-time, and 3. the percentage of the DC capacitor voltage ripple. Table 5-4 how the final parameter of the tetbed operating point. The three-phae AC input voltage are tranformed from 28 V to V by the autotranformer. The witching frequency i kept at khz. The DC capacitor voltage ripple at the full capacitive load i %. The coupling reactor impedance i the combination of the leakage inductance of the autotranformer and the additional inductor. TABLE 5-4. SPECIFICATIONS OF THE TESTBED AT THE OPERATING POINT. Three-Level Cacaded Converter Individual DC Bu Voltage V ± % Total DC Bu Voltage V ± % Rated RMS Reactive Current A Capacitor Impedance Individual Switching Frequency/ Equivalent Switching Frequency Power Sytem Configuration Coupling Reactor Impedance PCC Line Voltage (.5m-j/(ω 2.mF)) Ω/Phae khz/ 2 khz Balanced Three-Phae Three-Wire (72m-jω 2.mH) Ω/Phae V Control Sytem Parameter Beide the ame contraint of the power tage, the control parameter are alo deigned in uch a way that the ame bandwidth and phae margin are achieved for both the current and the voltage loop. A a reult, the percentage of the tetbed repone are identical to thoe in the high-voltage STATCOM ytem. Baed on the ame approach ued in the imulation, the deigned control parameter for the tetbed at the propoed operating point are given in Table 5-5. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 58

51 TABLE 5-5. DESIGNED PI COMPENSATOR PARAMETERS AND CURRENT AND VOLTAGE- LOOP GAINS CHARACTERISTICS OF THE TESTBED. Parameter Value Current Loop PI Compenator, H id (S) K p.2 K i 6. Loop-Gain T id (S) Characteritic Croover Frequency (Hz) 2 Phae Margin (Degree) 5 Gain Margin (db) 8.7 Voltage Loop PI Compenator, H Ed (S) K p.477 K i 5 Loop-Gain T Ed (S) Characteritic Croover Frequency (Hz) 2 Phae Margin (Degree) 56 Gain Margin (db) 5. To verify the deigned loop-gain characteritic hown in Table 5-5, the Bode plot of both current and voltage loop gain are illutrated in Figure 5-37 and Figure 5-38, repectively. The croover frequency of the current loop i deigned at 2 Hz, with a phae margin of 5, while that of the voltage loop i at 2 Hz, with a phae margin of 56. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 59

52 5 ( ) gain T id ( fi ( )) ( ) gain G idd ( fi ( )) -8.7 db 5 ( ) phae T id ( fi ( )) ( ) phae G idd ( fi ( )) 2 Hz ffi ( ) ffi ( ) Figure Bode plot of the open-loop control-to-d-channel-current tranfer function (dahed line) and the D-current loop gain (olid line) of the tetbed at the operating point. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 6

53 5 5 ( ) gain T Ed ( fi ( )) 5-5. db f( fi) 2 2 Hz ( ) phae T Ed ( fi ( )) ffi ( ) Figure Bode plot of the reference current-to-dc voltage tranfer function, T Ed (S). Experimental Reult The propoed feedback routine i digitally coded and downloaded to the program memory of the DSP. The tetbed ytem, a hown in Figure 5-36 i et up. Several experiment are conducted. Steady-State Compenation The experimental reult of the teady-tate compenation in both capacitive and inductive mode are hown in Figure 5-39(a) and (b), repectively. To how the capacitor and inductor characteritic of the STATCOM, the direction of the STATCOM current in thee experimental Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 6

54 reult i from the power network to the STATCOM, which i oppoite to that in the imulation. From Figure 5-39(a), the %, 2Hz ripple i noticed on top of the DC capacitor voltage, E A. Again, to minimize the DC capacitance, an expectable voltage ripple mut be allowed. The output current of phae A, i A, lead the line voltage V pcc AB by 6. In other word, the phae-a voltage at the PCC lag the current i A by 9, which i conitent with the imulation reult. In the inductive mode, a hown in Figure 5-39(b), the current i A lag the line voltage V pcc AB by 2, which agree with the imulation reult. A explained in the imulation reult, the experimental reult indicate that the voltage ripple of the DC capacitor in the inductive mode i le than that in the capacitive mode. 6 E A ( V/DIV) i A ( A/DIV) V pcc AB (5 V/DIV) 2 E A ( V/DIV) V pcc AB (5 V/DIV) i A ( A/DIV) (a) (b) Figure Steady-tate compenation in: (a) full-capacitive mode and (b) full-inductive mode. Tranition from Standby to Full Capacitive Mode The experimental reult of the STATCOM reponding to the tep command from tandby to full capacitive mode i hown in Figure 5-4. The DC capacitor voltage, E A, i very well regulated during the tranient. After the tranient, a hown in Figure 5-4(a), the current i A lag the line voltage V pcc AB by 2. In other word, the phae-a voltage at the PCC lead the current i A by 9, which i conitent with the imulation reult. In Figure 5-4(b), the DC Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 62

55 voltage E A i hown in detail. The peak-to-peak ripple voltage i about V, which i % of the DC voltage etting of V. Tranition from Full Capacitive to Full Inductive Mode and Vice Vera The imulation reult, a illutrated in Figure 5-4, validate the tability and the performance of the propoed control ytem reacting to the wort-cae command. The STATCOM i commanded to go from full capacitive to full inductive mode and vice vera, a hown in Figure 5-4(a) and (b), repectively. The voltage E A i very finely regulated during both tranition and teady tate. The output current i A repond very quickly to the tep command, and goe moothly to the teady tate. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 63

56 E A (2 V/DIV) V pcc AB (5 V/DIV) i A ( A/DIV) I q * m/div (a) E A (5 V/DIV) V AB (2 V/DIV) m/div (b) Figure 5-4. Experimental reult of the tetbed reponding to a tep command from tandby to full capacitive mode: (a) DC capacitor voltage of phae A (E A ), the voltage at the PCC between phae A and B (V pcc AB ), phae A output current (i A ) and the reactive current command (Iq*) and (b) the detail of E A and the output line-to-line voltage of the cacaded three-level converter (V AB ). Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 64

57 E A (2 V/DIV) V pcc AB (5 V/DIV) i A (5 A/DIV) I q * m/div (a) E A (2 V/DIV) V pcc AB (5 V/DIV) i A (5 A/DIV) I q * m/div (b) Figure 5-4. The experimental reult of the DC capacitor voltage of phae A (E A ), the voltage at the PCC between phae A and B (V pcc AB ), phae A output current (i A ) and the reactive current command (Iq*) of the tetbed reponding to a tep command: (a) from full capacitive to full inductive mode and (b) from full capacitive to full inductive mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 65

58 Periodic Tranition from Standby Mode to full capacitive Mode and Vice Vera In thi experiment, the STATCOM i commanded to generate the pulating reactive power, which i generally required in the flicker-mitigation application. The frequency of the pulating power i et at 5 Hz. A hown in Figure 5-42(a), the STATCOM inject the full capacitive current for m and no current for another m. The capacitor voltage, E A, i kept contant by the feedback voltage loop. Figure 5-42(b) illutrate the detail of the DC capacitor voltage and the output voltage of the converter. The % voltage ripple of voltage E A can be noticed during the full capacitive compenation. From full capacitive to tandby mode, voltage E A goe back to the etting value. Due to the lack of compenated current, there i no ripple acro the capacitor during the tandby mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 66

59 E A (2 V/DIV) V pcc AB (5 V/DIV) i A ( A/DIV) I q * 2 m/div (a) E A ( V/DIV) V AB (2 V/DIV) 4 m/div (b) Figure The STATCOM generate pulating reactive power: (a) the DC capacitor voltage of phae A (E A ), the voltage at the PCC between phae A and B (V pcc AB ), phae A output current (i A ) and the reactive current command (Iq*) and (b) the detail of E A and the converter output voltage (V AB ). Convergence of Three DC Capacitor Voltage, E A, E B and E C Thi experiment i to verify the convergence of all three DC capacitor voltage, E A, E B and E C. The experimental reult, a hown in Figure 5-43, demontrate that during both full Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 67

60 capacitive and tandby mode, all three DC capacitor voltage are well regulated and converge to the reference, which i V in thi cae. Moreover, the extreme cae i hown in Figure 5-44, in which the STATCOM periodically operate between full capacitive and full inductive mode. Again, all three DC capacitor are well regulated and converge to the reference. i A ( A/DIV) E A, E B, E C ( V/DIV) Figure The STATCOM goe from full capacitive to tandby mode. I A (A/DIV) E A, E B, E C V Full Inductive Full Capacitive Figure The STATCOM goe from full capacitive to full inductive mode and vice vera. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 68

61 J. Summary Baed on the aumption of the effective DC voltage-balancing technique, the accuracy of the propoed model of the CMC-baed STATCOM wa initially validated by both imulation and experimental reult obtained by the STATCOM utilizing the cacaded three-level converter. The experimental reult are conitent with the imulation reult. In the high-voltage STATCOM ytem, due to the limitation of the recent power emiconductor device technology, a higher number of voltage level i required in the CMC topology. Beide improving the voltage capability, everal other advantage can be achieved by utilizing the CMC in STATCOM application. With the knowledge acquired from the cacaded three-level converter reult, the performance of the STATCOM ytem can be greatly improved by the following factor: higher witching frequency, fater dynamic repone, better outputwaveform quality, and better redundancy and tability. However, it i not poible to achieve thee advantage in the CMC-baed STATCOM, unle an effective voltage-balancing technique i applied to it DC capacitor voltage. III. DC Capacitor Voltage-Balance Control Approache A. Imbalance of DC Capacitor Voltage in the Cacaded-Multilevel Converter-Baed STATCOM Obviouly, the primary attraction of the CMC topology i it modularity. However, thi topology require an exceive amount of DC voltage ource. The mot important factor cauing the voltage imbalance among thee DC capacitor are the difference in the DC-link utilization, the power tage loe and the component tolerance. Figure 5-45, for example, how a phae leg of a cacaded even-level converter. The reitor R LA, R LA2 and R LA3, repreented the internal loe in the H-bridge converter in level, 2 and 3, repectively. The internal loe may be differently influenced by the witching and conduction activity and the component tolerance. Firtly, thee H-bridge converter are aumed to be lole, and their capacitor voltage have the ame initial value. To achieve teady-tate, balanced voltage, thee DC capacitor mut have the ame amount of real power utilization in a given period of time. Due to haring the ame output current, the difference in the capacitor current are caued by the different duty cycle, becaue a capacitor current i a product of a duty cycle and an output Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 69

62 current. Therefore, the average witching function or duty cycle in thee H-bridge converter mut be identical or ele different in the DC voltage will be introduced. A couple of uitable modulation technique can olve thi problem. E A3 _ i Eb3 R LA3 C HB A3 _ v A3 i A A i Eb2 E A2 _ R LA2 C HB A2 _ v A2 v AN i Eb E A _ R LA C HB A _ v A N Figure One phae leg of a even-level cacaded converter. The firt technique, a hown in Figure 5-46(a), i called the rotating-pule taircae, which i uitable to be applied with high number of voltage level. A even-level cae i ued a an example. Theoretically, the average amount of current flowing into and out of the capacitor i equal after N/2 cycle, where N i the number of the H-bridge converter per phae. In a higher number of voltage level, thi proce, therefore, take a longer time and introduce a voltage ripple, whoe frequency i 2/N Hz for the cae of line frequency of 6Hz. Figure 5-46(b) illutrate the econd technique, called the phae-hifted carrier SPWM [], which wa propoed to improve the quality of the output waveform of the multi-converter module in highvoltage direct current (HVDC) application. In the even-level cae, three carrier are 2 apart Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 7

63 from each other. Becaue of the ue of equally ditributed carrier ignal, the fundamental component of the waveform in different level are theoretically identical; therefore, the amount of charge moving into and out of the capacitor in a period of time are equal. V AN t V A3 t V A2 t V A t (a) For level For level 2 For level 3 Modulating ignal (b) Figure PWM technique equally utilizing the DC capacitor voltage: (a) rotating-pule taircae and (b) phae-hifted carrier SPWM. By applying one of thee two technique, the capacitor voltage can be balanced in the lole STATCOM ytem. Thi i, however, not true in the cae of the real STATCOM ytem, becaue the H-bridge converter are not identical. The internal loe and the component Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 7

64 tolerance are, for example, different. To proof thi, a even-level cacaded-baed STATCOM, a hown in Figure 5-47, i ued a an example. The pecification of an example STATCOM ytem are hown in Table 5-6. The internal loe in the phae-a H-bridge converter are lightly different. Loe in the H-bridge converter in level, 2 and 3 are.%,.5% and % of it full power rating, repectively. The control propoed in the cae of the three-level cacaded-baed STATCOM i ued in thi tudy. The phae-hifted carrier SPWM i ued to generate the witching ignal for the cacaded even-level converter. Baically, the ame duty cycle i ued for all three H-bridge converter in the ame phae leg, regardle to the amplitude of their DC capacitor. R L V pcca R p L p i pa i a i b R V L pccb R p L p i pb V a N V b v an v bn v cn i c R L V pccc R p L p V c S a3 S a32 E a3 _ S v _ a3 an S b3 S b32 E b3 _ v _ b3 S an S c3 S c32 E c3 _ S v _ c3 an Point of Common Coupling i pc S a33 S a34 S b33 S b34 S c33 S c34 S a2 S a22 E a2 _ v a2 _ S b2 S b22 E b2 _ v b2 _ E c2 S c2 S c22 _ v c2 _ Meaurement S a23 S a24 S b23 S b24 S c23 S c24 S a S a2 E a _ v a _ S b S b2 E b _ v b _ E c2 S c S c2 _ v c _ Switching Signal Decoupling Power Controller S a3 S a4 S b3 S b4 S c3 S c4 I q * n Seven-level Cacaded Converter Figure The chematic of the even-level cacaded-baed STATCOM. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 72

65 TABLE 5-6. SPECIFICATIONS OF THE STUDIED SEVEN-LEVEL CASCADED-BASED STATCOM SYSTEM. Seven-Level Cacaded Converter Individual DC Bu Voltage 7 V ± % Total DC Bu Voltage 2 V ± % Rated RMS Reactive Current 25 A Capacitor Impedance Individual Switching Frequency/ Equivalent Switching Frequency Power Sytem Configuration Coupling Reactor Impedance PCC Line Voltage Phae-A Loe Level. % Level 2.5 % Level 3. % (.8m-j/(ω 3.5mF)) Ω khz/ 6 khz Balanced Three-Phae Three-Wire (3m-jω 35µH) Ω 2 V The firt cae tudy i that only the voltage of the phae-a level-one capacitor, E a, i regulated by the voltage loop of the controller. The ret of them are unregulated. The econd cae tudy i the ame a the firt cae except that the average voltage of all three capacitor voltage i regulated. In both cae, the STATCOM i commanded to operate in the tandby mode from tartup, and, at time 3 m, the STATCOM i commanded to operate in the full capacitive mode. The imulation reult of the firt and econd cae are hown in Figure 5-48(a) and (b), repectively. In the firt cae, the voltage E a i very well regulated, wherea the other two are decreaing. Thi i becaue only E a i ued a the feedback parameter. Since the other two H-bridge converter have more loe, they need more real power from the capacitor to compenate thoe loe. In the econd cae, none of capacitor voltage i well regulated, becaue their average voltage i ued a the feedback parameter. Due to the amount of loe, the voltage E a2 eem to be better regulated than the other, becaue it lo i cloe to the mean of the average loe. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 73

66 (a) (b) Figure The DC capacitor voltage of the three-level cacaded-baed STATCOM without the voltage-balancing technique: (a) uing phae-a capacitor voltage a the feedback and (b) uing the average of all three capacitor voltage a the feedback. From both imulation cae, it can be verified that the DC capacitor voltage cannot be balanced by olely applying uitable PWM technique. Either an individual voltage control loop or newly deignated PWM technique mut be included in the feedback-control ytem. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 74

67 5.2 Propoed DC Capacitor Voltage-Balancing Technique The previou work on the DC capacitor voltage-balancing technique baically add individual DC voltage loop into the main control loop. The compenator of each individual loop are very difficult to deign becaue of the complexity of the voltage-loop tranfer function. Baically, trial and error provide the implet way to achieve a good compenator. Thi proce i very time-conuming. Moreover, the greater number of voltage level, the more complex the control deign. The main controller, which i the DSP-baed, mut perform all of thoe feedback control. A a reult, thi approach potentially reduce the reliability of the controller. Thi reearch, therefore, propoe an effective technique, which ha the following feature:. it i uitable for any number of H-bridge converter, 2. it offer hardware-baed realization, 3. modularity, and 4. it complexity i not affected by the number of voltage level. Since the propoed technique can be realized by hardware circuitry, the calculation time in the DSP i jut lightly increaed when more voltage level are employed. The baic tructure of the propoed technique i modular; therefore, it i uitable for any number of H-bridge converter. With thee feature, the complexity of the DSP programming for the control loop i not affected by increaing the number of voltage level. I. Redundancy in the Cacaded-Multilevel Converter The CMC yntheize it output voltage by adding many individual voltage together. In the cacaded even-level converter, for example, even output-phae voltage level can be generated by even combination of the three H-bridge converter voltage, a hown in Figure However, conidering Figure 5-49(b), (c), (e) and (f), more than one combination can generate the ame output voltage. Redundancie to generate level 2, and voltage are hown in Figure 5-5, Figure 5-5 and Figure 5-52, repectively. Even though the ame output voltage are generated, the current flowing in the circuit have different path. Thi mean that different DC capacitor ee different current waveform. Conequently, the DC capacitor have different Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 75

68 voltage profile. Ironically, thee redundancie can be ued to adjut the individual capacitor voltage and help balance thee voltage. The redundancie, a hown in Figure 5-5, are ued a an example. If the DC voltage of the middle H-bridge converter i the lowet, then, for the given current direction, to generate the output voltage of 2E V, the combination hown in Figure 5-5(b) i ued, becaue the middle DC capacitor i diconnected from the output; with the large capacitor, it voltage i baically maintained. Due to the dicharge procee, the DC capacitor voltage of the top and bottom H-bridge converter are decreaed. Sytematically, if thi proce i kept going, the capacitor voltage of thee three H-bridge converter will become equal. To achieve minimal operating loe, not all of the redundancie can be ued. To generate the output voltage of E V, for example, circuit (e) through (g), a hown in Figure 5-5, generate three time a much conduction loe a circuit (a) through (c) do. Therefore, circuit (e), (f) and (g) are not uitable to be ued in either very high-power application or the propoed-voltage balancing technique. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 76

69 E _ E _ E _ E _ V an E _ V an E _ V an E _ E _ E _ (a) (b) (c) E _ E _ V an E _ (d) E _ - E _ - E _ - E _ V an E _ - V an E _ - V an E _ E _ E _ - (e) (f) (g) Figure Seven yntheized output voltage for the ingle-phae cacaded even-level converter: (a) 3 V, (b) 2 V, (c) V, (d) V, (e) V, (f) 2 V and (g) 3 V. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 77

70 E _ E _ E _ E _ V an E _ V an E _ V an E _ E _ E _ (a) (b) (c) Figure 5-5. Redundancy of voltage at level 2. E _ E _ E _ E _ V an E _ V an E _ V an E _ E _ E _ (a) (b) (c) E _ E _ E _ - E _ V an E _ - V an E _ V an E _ - E _ E _ (d) (e) (f) Figure 5-5. Redundancy of voltage at level. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 78

71 E _ E _ V an E _ (a) E _ - E _ E _ - E _ V an E _ - V an E _ V an E _ E _ E _ (b) (c) (d) E _ E _ E _ E _ - V an E _ V an E _ V an E _ E _ - E _ - (e) (f) (g) Figure Redundancy of voltage at level. Regarding the optimization concern, the elected operation mode ued to generate the poitive and zero output voltage for a even-level cacaded converter are hown in Figure The redundancy combination ued to generate the output voltage of 3, 2,, and are one, three, three, and one, repectively. Thi alo applie for the negative output voltage. Therefore, the total number of operation mode for the even-level cacaded converter i 5, which break down a even for the poitive voltage, even for the negative voltage, and one for the zero voltage. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 79

72 E _ Level 3 E _ V an E _ Mode 7 E _ E _ E _ Level 2 E _ V an E _ V an E _ V an E _ E _ E _ Mode 6 Mode 5 Mode 3 E _ E _ E _ Level E _ V an E _ V an E _ V an E _ E _ E _ Mode 4 Mode 2 Mode E _ Level E _ V an E _ Mode Figure The redundancy combination and mode aignment ued to generate the poitive and zero output voltage for a cacaded even-level converter. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 8

73 TABLE 5-7. NUMBER OF REDUNDANCY MODES IN EACH OUTPUT VOLTAGE LEVEL FOR DIFFERENT NUMBERS OF H-BRIDGE CONVERTERS PER PHASE. N 2N Number of redundancie at level Total no. of operation mode 3 3= = = = = = =2 8 - Table 5-7 how the number of redundancie for each output-voltage level with different value of N, where N i the number of H-bridge converter per phae. The number of phae voltage level i 2N. The total number of operation mode, which i the ummation of all redundancie, i 2 N -. The redundancie for each-output voltage level can be imply calculated by adding together the redundancie of the lower N. N equal to 7 i ued a an example. From Table 5-7, the arrow point out the two number ued to calculate the number of redundancie. For example, with an output level of 6, a redundancy of even i the ummation of 6 and from the cae of N = 6. For a high number of N, the number of the redundancy can be found by thi ytematic calculation. II. Cacaded Pule-Width Modulation Technique Given the troubleome previou work and the redundancy of the CMC, a new PWM technique, which i pecially deigned for the CMC-baed STATCOM, i propoed in thi ection. Figure 5-54 how the propoed block diagram of the CMC-baed STATCOM controller, which i baically identical to that of the three-level cacaded-baed STATCOM except that the voltage loop i different. The propoed PWM i called the cacaded PWM in Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 8

74 which the DC capacitor voltage, the output current and the three-phae multilevel duty cycle command are ued a it input. E A E AN E B E BN E C E CN i A, i B, i C D A * i Q * Decoupling Power Controller D B * D C * Cacaded PWM Switching Signal Cacaded-Multilevel Converter-Baed STATCOM Controller Figure Propoed cacaded-multilevel converter-baed STATCOM controller. The detail of the propoed cacaded-pwm block diagram are hown in Figure The diagram i compoed of ix different block: the boundary and duty cycle aignment, the direction and polarity check, the orting network, the index generator, the combined witching table, and the PWM. Thee ix block can be imply realized by programmable integrated circuit uch a the FPGA. To avoid confuion, the clock ignal for each block are not included in the block diagram. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 82

75 D A * Boundary and Duty Cycle Aignment D T * S C Pule Width Modulator S F Switching Signal for Phae A D C J C D F i A Direction And Polarity Check Pol Dir Index Generator Combined Switching Table E A E AN Sorting Network X orted J F Cacaded Pule Width Modulator Figure Block diagram of the propoed cacaded pule width modulator. A. Boundary and Duty Cycle Aignment To produce a clear explanation, a cacaded even-level VSC i ued a an example. Baed on the 2N formula, each phae of the converter conit of three identical H-bridge converter. Seven voltage level, a hown in Figure 5-56, can be yntheized, i.e., 3, 2,,, -, -2, and - 3. In the CMC, the relationhip between the modulation index and the duty cycle can be expreed a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 83

76 D = M co( ω t φ), and Equation 5-27 M V = N j= pk E j, Equation 5-28 where D i the duty cycle, M i the modulation index, ω i the angular velocity, φ i the diplacement angle, V pk i the peak output voltage, E j i the j th DC-link voltage, and N i the number of H-bridge converter per phae. From the plane hown in Figure 5-56, vector M A i defined a the phaor of the reference modulation index of the phae-a output voltage of the converter. In general, the modulation index for the CMC, a hown in Equation 5-28, i defined a a ratio of the converter output peak voltage to the total DC-link voltage. N i equal to 3 in thi example. Phaor M rotate with the angular velocity of ω or 2 πf, where f i the line frequency. From Equation 5-27, the duty cycle phaor, D A, i baically the projection of M A to the y-axi. The magnitude of D A determine the level of the ynthei voltage. Three circle on the xy plane hown in Figure 5-56 repreent the ix different combination of the level of the yntheized voltage. The poitive y i where the poitive half cycle of the output voltage i, wherea the negative y i where the negative half-cycle of the output voltage i. For example, M A i aumed to equal 2.34 and lay in the level between 2 and 3, a hown in Figure At that moment, the vector D, which repreent the intantaneou output voltage of the A converter, i equal to.5 in the boundary between the and the 2. A Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 84

77 y V an (t) M A θ D A x 2 t() T 2T 3T 4T 5T 6T Figure Multilevel voltage ynthei. D* Boundary and Duty Cycle Aignment D T * D C D F Figure Input and output ignal of the boundary and duty cycle aignment. The boundary and duty cycle aignment (BDCA) block i ued to determine the level of the output voltage and the normalized duty cycle. The input of the BDCA block i the command multilevel duty cycle, D A *, from the decoupling power controller, and it output are the normalized duty cycle, D T *, the ceiling duty cycle, D C, and the floor duty cycle, D F. The duty Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 85

78 cycle D C and D F are integer from to N, where N i the number of H-bridge converter per phae. The relationhip between duty cycle D C and D F i a follow: D < and D D. F D C F = C Equation 5-29 The duty cycle D C and D F are determined from the duty cycle D A * by the following relationhip: D < D * < D. F A C Equation 5-3 Then, the duty cycle D T * can be calculated by D * = D *. T D F Equation 5-3 For example, a given even-level duty cycle of the phae-a output voltage i D * = 2.34 A. Then, by applying Equation 5-29 through Equation 5-3, the other variable can be determined, a follow: D F = 2, D C = 3, and D T * =.34. B. Direction and Polarity Check The direction and polarity check (DPC) block i ued to determine the direction of the capacitor current, a well a the polarity of the duty cycle. The input of the DPC block are the Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 86

79 multilevel duty cycle D A * and the output current of the converter. The output of the DPC block are the polarity of the duty cycle, Pol, and the direction of the capacitor current, Dir. D T * i A Direction and Polarity Check Pol Dir Figure Input and output ignal of the direction and polarity check block. i a i a i a V - i c V a - V - i c V a - V a i a i a V - i c V a - V - i c V a - Figure Capacitor current in the four-quadrant operation of an H-bridge converter. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 87

80 The polarity of the duty cycle, Pol, i defined a follow:, when DA* < Pol =., when DA* Equation 5-32 The direction of the capacitor current, Dir, i a function of the direction of the output voltage and current. Figure 5-59 demontrate the direction of the capacitor current in all four quadrant of the I a -V a plane. The capacitor i dicharged when the polarity of the current I a and voltage V a are the ame, while the capacitor i charged when the polarity of the current I a and voltage V a are different. A a reult, to determine the direction of the capacitor current, the logic operator excluive OR can be applied to the direction of the output voltage and current a follow: Dir = i Pol, a Equation 5-33 where i a i the direction of the output current, which equal when flowing out of the converter and when flowing into the converter, and Dir i the direction of the capacitor current, which equal when dicharged and when charged. C. Sorting Circuit The orting network (SN), a hown in Figure 5-6, i ued to perform decending orting on the DC capacitor voltage. The input of the SN are N capacitor voltage in the ame phae leg of the CMC. After orting, the reult i a regiter containing N indice, which repreent the orting information of the capacitor voltage. The heart of the SN i the orting algorithm. Referring to the data architecture, among well-known orting algorithm, Bubble orting how the following feaibilitie to be ued in thi tak: it i very imple, and it provide modularity and high fault tolerance. The propoed SN for a general cacaded N-level converter i preented in Figure 5-6. The baic unit of the SN i the comparator (CP). The CP block diagram i hown in Figure 5-62, and it tranfer function i a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 88

81 H = max( a, b), L = min( a, b) Equation 5-34 where max i the maximum function, and min i the minimum function. E A E AN Sorting Network X orted Figure 5-6. Input and output of the orting network. X orted E A E A2 CP (,) CP (2,) CP (3,) CP (N-,) X X 2 X 3 X N- X N E A2 E A3 E A3 E A4 CP (,2) CP (,3) CP (2,2) CP (2,3) C CP (3,2) CP (3,3) CP (N-,2) CP (N-,3) E A(N-) E AN CP (,N-) CP (2,N-) CP (3,N-) CP (N-,N-) Sorting Network Figure 5-6. The propoed N-level orting network. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 89

82 A B H L Figure Input and output of a comparator unit. The index X i the number repreenting the capacitor poition in the phae leg, and i aigned a hown in Figure i A X N = 2 N- E AN _ R LAN C HB AN A X 2 = 2 E A2 _ R LA2 C HB A2 v AN X = E A _ R LA C HB A N Figure The embedded indice to repreent the capacitor poition. Figure 5-64 demontrate how the propoed SN work. The SN read the voltage content of the capacitor voltage of phae A of a cacaded even-level converter-baed STATCOM. Then, the embedded indice are aigned and are paed through the orting algorithm. After three clock cycle, the orted reult i achieved, and the regiter X orted can be acceed by the other function block. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 9

83 E A X E A X E A3 7V X orted E A2 76V E A 65V Sorting Network Figure Operation of the propoed orting network for a cacaded even-level converter. D. Index Generator The index generator (IG) i ued to calculate the ceiling and floor indice, which are ued to point to the ceiling and floor witching ignal from the combined witching table. The input of the IG are the two output of the BDCA block: DC and DF, the two output of the DPC block: Pol and Dir, and the output of the SN: E orted. For a given multilevel duty cycle, baed on the content of their capacitor voltage, the IG identifie it output by which H-bridge converter are ued to generate the output voltage. The output J C correpond to the input D C ; likewie for J F and D F. Therefore, the explanation of the J C cae will alo be applied in the cae of J F. Uing the ceiling index a an example, in the IG, the duty cycle D C repreent the number of H-bridge converter ued to generate the output voltage. The polarity of the output voltage i baed on the parameter Pol. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 9

84 D C J C D F J F Pol Dir Index Generator X orted Figure Input and output of the index generator. For Dir = and Pol =, D C H-bridge converter whoe DC capacitor voltage are the highet are ued to generate the poitive output voltage. In contrat, for Dir = and Pol =, D C H-bridge converter whoe DC capacitor voltage are the lowet are ued to generate poitive output voltage. In the cae of Pol =, for Dir =, D C H-bridge converter whoe DC capacitor voltage are the highet are ued to generate the negative output voltage. In contrat, for Dir = and Pol =, D C H-bridge converter whoe DC capacitor voltage are the lowet are ued to generate the negative output voltage. Baed on thi logic, Dir indicate whether the H-bridge converter with the highet or lowet DC voltage are ued to yntheize the output voltage. When Dir =, the IG perform the ummation of the X orted content from the left to the right-hand ide and from the right to the left-hand ide when Dir =. Parameter Inx L contain the ummation reult. The direction of the ummation i illutrated in Figure 5-66(a). The following algorithm i ued a an example for the cae of the ceiling parameter, D C : if Dir = ele Inx Inx L L = = D C i= X N orted X [ i] orted i= ( N ) D C [ i], Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 92

85 and the final format of the IG output J C i hown in Figure 5-66(b). Dir = X orted X X 2 X 3 X N- X N Dir = (a) Pol Inx L (b) Figure (a) The direction of the ummation of the indice, which i directed by the parameter Dir and (b) the final format of the generated index. E. Combined Switching Table After achieving the ready ignal from the IG, the indice J C and J F are ued to point to the deirable witching ignal for all main emiconductor device. Table 5-8 i an example for the even-level cacaded converter cae. The table conit of the index (the firt and econd column), correponding hex (the third column), and the tatu of the top witche of the level-3 H-bridge converter (the fourth column), the level-2 H-bridge converter (the fifth column), and the level- H-bridge converter (the ixth column). The and in the fourth though ixth column repreent the top witche turned off and on, repectively. Due to complementary witching, the top and bottom witching tatue derived from the four poible combination of the two top witche are given in Table 5-9. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 93

86 TABLE 5-8. COMBINED SWITCHING TABLE FOR THE CASCADED SEVEN-LEVEL CONVERTER. Pol Inx L Hex S A3,S A32 S A2,S A22 S A,S A2,,,,,, 2,,, 3,,, 4,,, 5,,, 6,,, 7,,,,,,,, 2,,, 3,,, 4,,, 5,,, 6,,, 7,,, TABLE 5-9. SWITCHING STATUSES OF FOUR POSSIBLE COMBINATIONS OF TOP AND BOTTOM SWITCHES. S A,S A2 S A S A2 S A3 S A4,,,, F. Pule-Width Modulator Baically, the PWM tranform the average witching function or the duty cycle into the twotage witching action for the individual witch. The input and output of the PWM are hown in Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 94

87 Figure Due to the relatively low witching rate of the high-power emiconductor device, the double-updated PWM, a hown in Figure 5-68, i employed to minimize the delay time. Figure 5-68 illutrate the PWM waveform of the phae-a voltage generated from the given even-level duty cycle command between time and T, where T i the witching period. The PWM read the duty cycle command twice every witching cycle at and.5t, in order to generate the waveform in the -.5T and the.5t-t duration, repectively. D T * Pule Width Modulator Switching Signal S C S F Figure Input and output of the pule-width modulator. y V an (t) D C D C E D A_ DA _. 5 T lp2 D F D F E lp.5t T t() Figure Double-updated pule generated by the pule-width modulator. A general PWM waveform yntheized by the propoed PWM, a hown in Figure 5-68, i ued a an example. In the period between T and.5t, the duty cycle i read. The D A _ T witching ignal correponding to the index J F are ent to the main witche. At the moment that the negative lope lp interect, the main witche are witched to the witching ignal D A _ T Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 95

88 correponding to the index J C. In the econd half-cycle, the duty cycle i updated to DA _. 5 T. The tatu of the main witche i, however, till unchanged. Until the moment at which the poitive lope lp2 interect, the main witche are witched back to the witching ignal DA _. 5 T correponding to the index J F. Thi complete a witching cycle. E _ i E 3C RLN /3 d d i d d q i q d i d d NE i d V d _ R L L ωi q V pccd E _ i E 3C R L2 /3 d d i d d q i q d i d q NE i q V _ q R R L L L ωi d V pccq E _ i E 3C R L /3 d d i d d q i q d i d NE i V V pcc Cacaded-Multilevel Converter Figure The average model for the CMC-baed STATCOM with the propoed PWM. III. Simplified Model for the Cacaded-Multilevel Converter-Baed STATCOM Utilizing the Cacaded Pule-Width Modulator By applying the propoed cacaded PWM, the model for the CMC-baed STATCOM can be further implified. Baed on the generic average model of the CMC-baed STATCOM, a hown in Figure 4-4, it implified model i depicted in Figure Mathematically, on the DC ide, the DC capacitor can be connected in parallel, a hown in Figure 5-7. The capacitor current can be expreed a follow: Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 96

89 de N 3C = N ( d i d i d i d d q q ), or dt de 3C = d d id d qiq d i. dt Equation 5-35 From Equation 5-35, due to the cancellation of N on both ide, the number of H-bridge converter per phae i not a factor. Thi lead to the concluion that if the cacaded PWM i utilized, the DC ide of the CMC can be modeled a that of the three-level cacaded converter, a hown in Figure 5-7. However, the difference in the AC ide from that of the cacaded threelevel converter i the multiplier N of the voltage-controlled voltage ource. R L L ωi q d d NE i d V d V pccd E _ i E 3NC Nd d i d Nd q i q Nd i d q NE i q V _ q R L L ωi d V pccq R L Cacaded-Multilevel Converter d NE i V V pcc Figure 5-7. The implified average model for the CMC-baed STATCOM with the propoed PWM. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 97

90 R L L ωi q d d NE i d V d V pccd E _ i E 3C d d i d d q i q d i d q NE i q V _ q R L L ωi d V pccq R L Cacaded Multilevel Converter d NE i V V pcc Figure 5-7. The average model for the CMC-baed STATCOM with the propoed PWM. IV. Feedback Deign for the CMC-Baed STATCOM To evaluate the performance of the propoed cacaded PWM, the cacaded even-level converter-baed STATCOM, a hown in Figure 5-47, i ued a an example. The power tage parameter of the converter are given in Table 5-6. The implified average model of the evenlevel converter-baed STATCOM, from which the mall-ignal model i derived, i hown in Figure Baed on the ame approach ued in the three-level cae, the key tranfer function are determined, and the control parameter are then deigned, a given in Table 5-. Due to the horter delay in the cacaded even-level converter, the bandwidth of the current and voltage loop can be increaed. A a reult, the fater ytem repone i achieved. The control-to-current tranfer function and the current-loop gain are hown in Figure 5-73(a). Figure 5-73(b) how the D-channel current-to-dc-capacitor-voltage tranfer function and the main voltage-loop gain. From the reult, the main current-loop bandwidth i 2 Hz, and the main voltage-loop bandwidth i 8 Hz. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 98

91 R L L ωi q i E d d 3E i d V d V pccd E _ 3C d d i d d q i q d q 3E i q V _ q R L L ωi d V pccq Cacaded Seven-Level Converter Figure The implified average model for the even-level cacaded-baed STATCOM. TABLE 5-. CONTROL PARAMETERS FOR THE SEVEN-LEVEL CASCADED CONVERTER- BASED STATCOM. Parameter Value Current Loop PI Compenator, H id (S) K p.398m K i. Loop-Gain T id (S) Characteritic Croover Frequency (Hz) 4 Phae Margin (Degree) 66 Gain Margin (db) 2.2 Voltage Loop PI Compenator, H Ed (S) K p 79.6 K i 2.5k Loop-Gain T Ed (S) Characteritic Croover Frequency (Hz) 4 Phae Margin (Degree) 95 Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 99

92 2 ( ) ( ( ( ))) gain T id ( fi ( )) gain G idd fi 5 ( ) ( ( ( ))) gain T Ed ( fi ( )) gain T Eid fi -2.2 db 4 Hz 4 Hz ( ) ( ( ( ))) phae T id ( fi ( )) phae G idd fi f( fi) f( fi) ( ) ( ( ( ))) phae T Ed ( fi ( )) phae T Eid fi f( fi) f( fi) (a) (b) Figure (a) Bode plot of the control-to-current tranfer function and the current-loop gain; (b) Bode plot of the D-channel current-to-dc-voltage tranfer function and main voltage-loop gain. A. Simulation Reult Figure 5-74 how the reult of the dynamic repone of the STATCOM operating in tandby, full capacitive and full inductive mode. The reult include the command Iq and it repone, the phae-a converter output current and voltage at the PCC, and the DC bu voltage of each level. The detail are hown in Figure 5-75, in which the STATCOM receive the tep command from the full capacitive to full inductive mode. According to the defined current direction, the converter current lag the PCC voltage by about 9 in full capacitive mode, while the converter current lead the PCC voltage by about 9 in full inductive mode. However, converter current and voltage at the PCC are not exactly 9 becaue of the real power exchange. The reult how that the STATCOM react to the tep command in the order of a Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 2

93 ub-line cycle, even though the witching frequency of each H-bridge converter i only khz. Figure 5-76 how all three phae output voltage and current, and the voltage at the PCC. To verify the DC bu voltage-balancing, all nine DC voltage waveform acro the bu capacitor are hown in Figure 5-77 and Figure In Figure 5-77, the DC voltage are grouped in the ame phae. The reult how that the DC voltage in each phae are well balanced. The wort cae of DC repone i for phae B ; however, the controller i able to bring the voltage back to the etting, which i 7 V. Figure 5-78 how the DC voltage in group of the ame level. Baed on the average DC voltage control cheme, the DC voltage of all three level are identical, a expected. I q and I q * i a V pcca Three DC capacitor voltage of phae A Figure The STATCOM operate in tandby mode (zero reactive power injection), full capacitive mode (Q) and full inductive mode (-Q). Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 2

94 I q and I q * i a V pcca Three DC capacitor voltage of phae A Figure Step repone of the STATCOM from full capacitive mode (Q) to full inductive mode (-Q). Phae C Phae B Phae A Figure Output current and voltage of the converter and the voltage at the PCC. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 22

95 Phae A Phae B Phae C Figure All nine capacitor voltage in group of the ame phae. Level Level 2 Level 3 Figure All nine capacitor voltage in group of the ame level. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 23

96 B. Experimental Reult To validate the performance of the cacaded PWM technique, a ingle-phae, even-level cacaded-baed STATCOM with the DSP-baed controller i et up in the mall-cale tetbed. Two experiment are conducted to demontrate the balanced DC capacitor voltage through the tranient to the tep command and the DC capacitor voltage diturbance. The pecification for the experimental etup of the even-level cacaded-baed STATCOM are given in Table 5-. TABLE 5-. SPECIFICATIONS FOR THE STUDIED SEVEN-LEVEL CASCADED-BASED STATCOM TESTBED SYSTEM. Seven-Level Cacaded Converter Individual DC Bu Voltage 7 V ± % Total DC Bu Voltage 2 V ± % Rated RMS Reactive Current A Capacitor Impedance Individual Switching Frequency/ Equivalent Switching Frequency Power Sytem Configuration Coupling Reactor Impedance PCC Line Voltage (.8m-j/(ω 2mF)) Ω 333 Hz/ 2 khz Balanced Single-Phae Three-Wire (64m-jω 4mH) Ω 28 V DC Voltage-Balancing during the Tranient In thi experiment, the STATCOM operate in the wort-cae tranient, which i either from the full capacitive to full inductive mode or vice vera. From the experimental reult a hown in Figure 5-79, at time t, the STATCOM i commanded to abruptly tranfer from the full inductive to the full capacitive mode. Before time t, the output current i A, which i leading the voltage at the PCC, V pcca, by 9, indicate that the STATCOM operate in the inductive mode, while the output current i A lagging V pcca by 9 after time t indicate that the STATCOM operate in the capacitive mode. The reult how the fat repone of i A to the tep command. During the full capacitive mode, the 2Hz voltage ripple acro the DC capacitor i at it Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 24

97 maximum, which i approximately 7 V peak-to-peak or % of the DC voltage etting of 7 V, and which i conitent with the E A waveform, a hown in Figure Since three H-bridge converter are ued in one phae leg, the output voltage V A then ha even level. Although the lower individual witching frequency of 333 Hz i ued, the ame current-loop bandwidth a that of khz in the three-level cae can be achieved. V pcca (3 V/DIV) i A (2 A/DIV) E A (2 V/DIV) V A (2 V/DIV) t (2 m/div) Figure The tranient from the full inductive to the full capacitive mode of the even-level cacaded-baed STATCOM operation: (from the top) the voltage at the PCC, the converter output current and the firt-level DC capacitor voltage and the converter output voltage. Figure 5-8(a) how the repone of the three DC capacitor voltage of the even-level cacaded converter during the ame tranient at time t 2, which i from the full inductive to full capacitive mode. The reult how that thee three DC capacitor voltage, E A though E A3, are very well regulated to the etting value in the teady tate. A hown in Figure 5-8(b) E A though E A3 are aligned with the ame reference in order to how their balance. The reult indicate that all three voltage have the ame voltage ripple and are very well balanced in both the teady tate and the tranient. Again, the maximum peak-to-peak voltage ripple acro the DC capacitor are about 7 V during the full capacitive operation mode. Chapter 5 Control of Cacaded-Multilevel Converter-Baed STATCOM 25