Control Design of a Neutral Point Clamped Converter Based Active Power Filter for the Selective Harmonic Compensation

Transcription

1 Control Deign of a Neutral Point Clamped Converter Baed Active Power Filter for the Selective Harmonic Compenion Joé Lui Monroy Morale, Máximo Hernández Ángele Programa de Graduado e Invetigación en Ingeniería Eléctrica Intituto Tecnológico de Morelia Morelia, Michoacán México jlmonroy m@itmorelia.edu.mx, mhernand it@yahoo.com.mx David Campo-Gaona, Rafael Peña-Alzola Department of Electrical and Computer Engineering The Univerity of Britih Columbia 33 Main Mall. Vancouver, BC Canada V6T 1Z4l davidcg@ieee.org, rafapeal@gmail.com Abtract Thi paper preent the control of an active power filter APF) baed on a 3-phae, 3-level neutral point clamped NPC) converter with elective harmonic compenion. To achieve the elective harmonic compenion, the APF ue everal ynchronou rotatory frame, which are rotating at the angular frequency and equence of their repective harmonic, to detect and control the magnitude and angle of each individual harmonic uing d and q variable. A three dimenional pace vector modulator 3D-SVPWM) i ued to generate the compenion current. Due to it multilevel topology, the propoed active power filter can be ued in high voltage power quality application, uch a ub-tranmiion and ditribution level. Simulation reult are hown to validate the propoed olution and corroborate the proper function of the multilevel active power filter. Keyword: Active Power Filter, Neutral Point Clamped, Selective Harmonic Compenion, Overall Harmonic Compenion. I. INTRODUCTION Energy quality iue are an important apect in the electrical energy conumption. That way, the harmonic in power ytem reult in everal problem due to the wide application of power electronic equipment and nonlinear load. Harmonic ditortion caue everal problem uch a increaed power loe, exceive heating in rotating machinery, electromagnetic interference in communication ytem and operation failure of protection device and electronic equipment [1]. Additionally, non-inuoidal current produce low power factor and high total harmonic ditortion. Becaue of thi, the modernization on tranmiion and ditribution grid require new ytem baed on power electronic converter, with favorable characteritic uch a, high efficiency, high power denity, and low harmonic ditortion, to uitable into the ditributed generation and mart-grid concept. A multilevel NPC converter topology can be ued at higher power application a APF. Thu, it can be applied in tranmiion, ub tranmiion, wind, photo-voltaic and mining ytem. The APF performance depend on it controller which i divided in two part. The firt part determine the fundamental and harmonic reference current of the APF and maintain a table DC bu voltage. Due to, everal harmonic current detection method, uch a intantaneou reactive power theory, ynchronou reference frame method, and upplying current regulation can be ued [ ]. Thee method meaure the harmonic current either from the load or from the main current to generate a reference harmonic current that will cancel out the grid current at the point of common coupling. The econd part i related to generate the compening current into the AC main. Therefore, everal modulation technique are implemented for driving the inverter. Among thee method, the pule wih modulation PWM) technique have been employed in APF for harmonic elimination [6]. With the development of high peed microproceor, pace vector modulation SVM) ha become one of the mot important PWM method for three phae converter. The SVM baed PWM method have everal advantage over carrier baed one uch a lower total harmonic ditortion THD) and higher efficiency and higher available DC-link [7, 8]. The 3D-SVPWM i an ueful algorithm ued in multilevel level converter. Thi modulation technique optimize the number of commutation and the number of calculation to get the witching equence and the duty cycle [9 11]. Thi paper preent the control of an active power filter APF) baed on a 3-phae, 3-level neutral point clamped NPC) converter with elective harmonic compenion. Figure 1 how the APF with three level converter topology. To achieve the elective harmonic compenion, the APF ue everal ynchronou rotatory frame, which are rotating at the angular frequency and equence of their repective harmonic, to detect and control the magnitude and angle of each individual harmonic uing d and q variable. A 3D-SVPWM i ued to generate the compenion current. The multi level

2 topology ha the advantage to be ued in high voltage power quality application, uch a ub-tranmiion and ditribution level. Simulation reult are hown to validate the propoed olution and corroborate the proper function of the multilevel active power filter. V grid i abc_grid i abc_conv i abc_load PWM Generator Three Level NPC Converter m abc_1 m abc_h C R Non Linear Load P, Q and Harmonic Current Fig. 1. Active power filter with three level inverter topology. II. THREE LEVEL CONVERTER In a multilevel NPC converter topology, the voltage tre acro the witche are lower and there are more available control vector. Thu, the harmonic content of the converter i reduced if appropriate witching vector are elected [1]. A three-phae three-level NPC converter i hown in Figure. The three phae have a common DC bu, divided by two capacitor into three level. The voltage acro each capacitor i /; and the voltage tre acro each witching device i limited to / through the clamping diode. A threelevel NPC converter i able to produce five level of line to line voltage and three level of phae voltage. Thi NPC converter reduce harmonic in both voltage and current output. D1a Da S1a Sa S3a S4a D1b Db S1b Sb S3b S4b N D1c Dc S1c Sc S3c S4c Ia Ib Ic Fig.. Three-level NPC inverter topology. Table I give the witch tate for phae a. Similar witching equence will be derived for other phae by according the phae angle diplacement. Here, S 1a and S 3a are complement of each other and S a and S 4a are complement of each other. TABLE I SWITCHING STATES OF THREE-LEVEL NPC CONVERTER State of witche Voltage S 1a S a S 3a S 4a Level V an Vdc/ Vdc/ State condition 1 mean witch ON and 0 mean witch OFF. Now, it i clear that an m-level diode clamped converter conit of m-1) capacitor on dc bu, output phae voltage ha m-level and output line voltage ha m-1)-level. Each active witching device ha to withtand a blocking voltage of Vdc/m-1), even then clamping diode mut have different voltage rating for revere voltage blocking. The number of diode required will be m-) and the number of witching required will be m-1) for each phae. Where m i the number of level of the converter [8]. III. HARMONIC DETECTION DQ USING SYNCHRONOUS REFERENCE FRAME In the ynchronou reference frame SRF) algorithm, ynchronou harmonic d q frame rotate at a frequency and equence equal to the elected harmonic. Thu, in the harmonic d q frame, only the repective harmonic will be a dc-ignal and all other frequencie including the fundamental will be ac-component. The detection of the repective harmonic reult in removing the ac-ignal with low pa filter ). A een in Fig. 3, the load current i abc load i meaured and fed to the multiple ynchronou reference frame. Each frame provide the d q component of each harmonic plu an ac ignal. The ac ignal of the harmonic d q component i filtered by a low pa filter baed on the moving average architecture. The current of the inverter i abc inv i alo fed to the multiple ynchronou frame and the reulting d q ignal are alo filtered by a low pa filter with the ame characteritic and delay a the d q load harmonic current. The filtered d q harmonic current from the load and the inverter are then fed to a controller. The controller generate, a a control action, a modulator ignal that would produce harmonic current of magnitude that match thoe of the load, but in oppoite polarity. In conequence, the load harmonic current would cancel out with the inverter harmonic current at the point of common coupling [, 13]. In addition, a limiter i added after every regulator in order to enure that the harmonic current never increae beyond their allowed range. Otherwie, inverter voltage reference may become greater than the maximum voltage allowed by the DC capacitor. Thi produce uration in the modulator

3 ignal which in turn produce unwanted harmonic content. The main advantage of a elective harmonic compenion SHC) mode over an overall harmonic compenion OHC) mode i the ability to elect individual harmonic to compene. Therefore, SHC ytem can be intalled in parallel to cancel individual harmonic from eparate unit. DC Voltage meaurement AC Current meaurement ref I abc DC Voltage controller Outer Control Loop) abc to dq tranformation ref I d Current controller Inner Control Loop) PWM d PWM q PWM generator PWM converter V abc i abc_inv DC voltage/active power and reactive power control PLL meaurement ref I q i abc_load i q_load_ m abc abc_ h 7 7 i d_load_ i q_inv_ i d_load_7 i q_inv_7 i d_inv_ i d_inv_7 i q_load_7 7 m abc_7 Fig. 4. Overall Scheme of Vectorial Control active and reactive power and a fat dynamic, it make the realization of ytem control in form of cacade tructure poible, with two control loop in cacade. Meaning thi, an outer control loop and inner current control. The control ytem i baed on a fat inner current control loop controlling the ac current. The ac current reference are upplied by outer controller. The inner and outer controller are decribed below. A. Inner and Outer The inner current control loop can be implemented in the d q frame, baed on the baic relationhip of the ytem model. A general inner current control block i repreented in Figure. n n i d_load_n i q_inv_n i d_inv_n i q_load_n n m abc_n Fig. 3. Selective harmonic compenion baed ynchronou reference frame. IV. ACTIVE POWER FILTER CONTROLLER The overall APF elective harmonic controller i hown in Figure 4. A vectorial control i carried out to achieve the elective APF controller, three phae current and voltage are decribed a vector in a complex reference frame, called α-β frame. A rotating reference frame ynchronized with the acgrid i alo introduced. A the d q frame, i ynchronized to the grid, the voltage and current occur a contant vector in the d q reference frame in teady tate. The value of the angle θ i calculated by uing a ynchronization technique phae locked loop PLL). The PLL information i ued to ynchronize the turning on/of f of the power device, calculate and control the active/reactive power flow by tranforming the feedback variable to a reference frame uitable for control purpoe [14]. A the vector control technique offer decoupled control of I ref - V conv PWM V conv Sytem I Converter Tranfer Function Fig.. General block diagram of inner current control. Inide the current control block, there are two P I regulator, repectively for d and q axi current control. They tranform the error between the comparion of d and q component of current into voltage value. In order to have a detail overview of the control ytem, each block of the control ytem i dicued a below. The repreentative equation of the P I regulator i: R) = K p K ) i 1 = K Ti. p. T i. conidering the I) and I ref ) and P I controller block, {I ref ) I)} K p K ) i = V conv). ) The PWM converter block i conidered a an ideal power tranformer with a time delay. Thu the PWM block i given a, V conv). 1 1 T a. = V conv) 3) where T a = T witch /. 1)

4 Conidering the converter ytem connected to grid, a een in Figure 1, the phae voltage and current are given by the equation, V abc = R.i abc L di abc V abc,conv 4) Hence the ytem tranfer function i: G) = 1 R. 1 1.τ Where the time contant i defined a τ = L/R. 13) where V abc and i abc, are ac voltage and current repectively, and v abc,conv i the voltage converter. R and L are the reitance and filter inductance between the converter and the ac ytem. Uing the abc to d q tranformation, the 3-phae current and voltage converter are expreed in -axi d q reference frame, ynchronouly rotating at given ac frequency w a V d = R.i d L di d ωli q onv ) V q = R.i q L di q ωli d V qconv 6) Similarly on the output ide, I dc = C. d I L 7) A een from equation ) and 6) the equation in d and q axi have a imilar form, for thi reaon only the d- axi equation i ued for further analyi and control rule derivation. The inner loop current controller for i d, give the output of V d voltage reference ignal, which fed to the converter. Uing Equation ), onv = i dref i d ). K p K ) i 1. 8) 1 T a The tranformed d q voltage equation have the frequency induced term, wli d and wli q, that produce a cro coupling between the d and q current. Thi cro coupling term can be cancelled out algebraically in the control loop, enabling an independent control in d and q axi, repectively. With the compenion term ued for decoupling, the ytem input from converter i defined a onv = i dref i d ). K p K ) i wli q V d 9) Equation 9) when ubtituted in Eqn. 3) and equated to equation ), it give, L di d Ri d = onv 10) by Laplace tranformation the equation become: Thu,.I d ) = R L.I d) 1 L.onv). 11) I d ) = 1.L R.onv) 1) Since the control of the inverter fundamental current and harmonic i carried out by dc ignal, the modulu optimum tuning criteria can be ued to elect the contant of the P I controller. If conidering the cro coupling term the d q current equation and the grid voltage component are diturbance, not preent during the calculation of the d q current control, but intead being numerically compened by a feed-forward loop in the main harmonic current control loop, then, the plant for d q fundamental and harmonic current i: G) = i d h) onv h ) = i q h) V qconv h ) = i h) V convh ) 14) where onv h and V qconv h are the d q component of the average voltage generated by the inverter for the harmonic h, i d h and i q h are the d q component of the current between the inverter and the grid for the harmonic h. From 13) it can be een that the ytem ha a table pole at R/L. Thi pole can be cancelled with the zero provided by the P I controller, where Kp conv h and Ki conv h are the proportional and integral contant of the h harmonic P I current controller. Thu, chooing Ki conv h /Kp conv h = R/L and Kp conv h /L = 1/τ conv h, where τ conv h i the time contant of the cloed-loop ytem. The power balance in the ytem i achieved through the dc voltage controller. The general diagram for the outer controller i hown in Figure 6. The diagram conit of a P I controller, the inner controller and the power tranfer function of the capacitor. ref - I dref Inner Current I d Sytem Tranfer Function Fig. 6. General block diagram of outer dc voltage control. The repreentative equation of the P I voltage regulator i: R) = K pv K ) iv 1 Tiv. = K pv. 1) T iv. where the ubcript v denote the voltage regulator. For the P I controller block for outer voltage control, {ref ) )} K pv K ) iv = i dref ) 16)

5 The power balance relationhip between the ac input and dc output i given a, P = 3 V d.i d V q.i q ) =.I dc 17) where and I dc are dc output voltage and current repectively. Uing the condition V q = 0, the relation between i d and I dc can be written a, I dc = 3. V d.i d 18) Thi define the value of the current gain to be ued from dc current to input current or vicevera. Subtituting thi value in 7), we get, C d = 3. V d.i d I L 19) It i poible to oberve that the dc link current equation i a nonlinear equation. For analyzing the tability of a nonlinear ytem in the neighbourhood of a teady tate operating point, it i neceary to linearize the ytem model around the operating point and perform linear tability analyi. The reference point for linearization i found by pecifying reference input,,ref for the nonlinear model.conequently the linear expreion become, C d By Laplace tranformation it i: = 3. V d,0,ref. i d 0) ) i d ) = 3. V d,0 1.,ref.C 1) The dc link voltage controller control the capacitor current o a to maintain the power balance. Hence under balanced condition, Ic = 0. That i, I dc = I L. Thu, the reference value of i d hould be, i d = 3. V d.i dc ) The overall control block diagram of the dc voltage controller baed on equation 16)-) i a hown in Fig. 7. The inner ref - K pv 1T. iv T iv. 3..I DC V d I L Idref I d T 3. V I DC I C d 1 eq.1.c Inner Current Loop B. 3D-Space Vector Modulator The 3D-SVPWM algorithm optimize the commutation equence uing four tate vector, which are adjacent to the reference vector, and determine the repective commutation time of the three-level converter witching device. The reference vector i repreented by mean of four vertice of a tetrahedron which are the tate vector of the equence witching. Figure 8 how a tetrahedron in a ub-cube with correponding tate vector. The computational load i independent of the number of level of the converter. In addition, the algorithm provide the witching equence that minimize the total harmonic ditortion T HD) and the number of witching of the emiconductor device. U c a,b,c) U b a1,b1,c1) a1,b,c1) a1,b,c) U a Fig. 8. Tetrahedron in a ub-cube with correponding tate vector. Figure 9 how the complete block diagram of the algorithm. Thi algorithm i well uited due to the good performance t V ref V ref V ref_nor V S comm ref_nor Seq Normalization 3D-SVPWM Sequence Seq Fig. 9. Block diagram of 3D-SVPWM algorithm. Control Pule for multilevel converter and it can be ued for converter with more level applying a minimum of change in it programming. The matrix with four commutation vector and the correponding witching time are defined by: Fig. 7. Cloed loop control diagram of dc voltage controller control time repone i elected in 1m, hence, the outer control i elected 10 time thi value in order to get a good performance of the controller. Sec = S 1 a S a S 3 a S 4 a S 1 b S b S 3 b S 4 b S 1 c S c S 3 c S 4 c 3)

6 t = S 1 S S 3 S 4 4) % Total Harmonic Ditortion No compenion, THD=.% th Compeion, THD=10.% 7th Compeion, THD=6.6% 11th Compenion, THD=.3% 13th Compeion, THD=.0% 17th Compenion, THD=4.44% 0.0 V. SIMULATION RESULTS The imulation reult of the propoed APF are decribed in thi ection. A three-phae rectifier a nonlinear load ha been connected to a 100 V, 60 Hz grid through filtering inductor. The APF operate at a witching frequency of 10 khz and regulate it internal DC voltage to 0 V. Figure 10 how the grid current effect in phae a when the compenor i enable in 0.. Applying thi elective harmonic compenor the total harmonic ditortion THD) ha been reduced from.% to 4.3%. Ampere Before Compeion Grid Current Phae a After Compeion Time econd) Fig. 10. Grid current in phae a before and after compenion. In Figure 11 i hown the three phae current, before and after the compenion. Ampere Before Compeion Grid Current After Compeion Time ec) Fig. 11. Grid three phae current before and after compenion. In order to ee the reult of the individual harmonic control capability of the APF, Figure 1, how the effect of each harmonic compened and the correponding THD when thi i activated. Ia Ib Ic Time ec.) Fig. 1. Total harmonic ditortion for each harmonic elected. VI. CONCLUSION Thi paper preent the deign and control of an active power filter baed on 3-level NPC converter for elective harmonic compenion uing ynchronou reference frame. The controller for the elective harmonic compenion ue ynchronou reference frame and a low pa filter in order to enable the control of individual harmonic uing d q ignal. Therefore, the derive control rule can be elected and applied, and the harmonic compenion i carried out without teady tate error. The ue of three level converter and 3D-SVPWM provide an accurate generation of the harmonic current with a lower harmonic content. Thank to thi, the active power filter baed on the three level converter i an attractive application for power quality improvement application in ditribution and ub tranmiion ytem. REFERENCES [1] B. Singh, K. Al-Haddad, and A. Chandra, A review of active filter for power quality improvement, IEEE Tranaction on Indutrial Electronic, vol. 46, no., pp , Oct [] H. Akagi, Y. Kanazawa, and A. Nabae, Intantaneou reactive power compenor compriing witching device without energy torage component, IEEE Tranaction on Indutry Application, vol. IA-0, no. 3, pp , May [3] S. Bhattacharya and D. Divan, Synchronou frame baed controller implementation for a hybrid erie active filter ytem, in Indutry Application Conference, 199. Thirtieth IAS Annual Meeting, IAS 9., Conference Record of the 199 IEEE, vol. 3, Oct 199, pp vol.3. [4] J. C. Wu and H. L. Jou, Simplified control method for the ingle-phae active power filter, IEE Proceeding - Electric Power Application, vol. 143, no. 3, pp. 19 4, May [] D. Campo-Gaona, R. Peña-Alzola, J. L. Monroy Morale, and M. Ordonez, Dynamic mitigation of grid current harmonic uing the power phere concept in voltage ource inverter, in 016 IEEE 7th International Sympoium on Power Electronic for Ditributed Generation Sytem PEDG), June 016, pp [6] H. H. Kuo, S. N. Yeh, and J. C. Hwang, Novel analytical model for deign and implementation of three-phae active power filter controller, IEE Proceeding - Electric Power Application, vol. 148, no. 4, pp , Jul 001. [7] K. Zhou and D. Wang, Relationhip between pace-vector modulation and three-phae carrier-baed pwm: a comprehenive analyi [threephae inverter], IEEE Tranaction on Indutrial Electronic, vol. 49, no. 1, pp , Feb 00.

7 [8] D. P. Dorante, J. L. Monroy Morale, and M. Hernández- Ángele, 3dvpwm vector control of a vc-hvdc tranmiion ytem, in 013 IEEE International Autumn Meeting on Power Electronic and Computing ROPEC), Nov 013, pp [9] J. I. Leon, R. Portillo, L. G. Franquelo, M. M. Prat, and W. Kolomyjki, New tate vector election uing pace vector modulation in three dimenional control region for multilevel converter, in 006 IEEE International Sympoium on Indutrial Electronic, vol., July 006, pp [10] J. I. Leon, S. Vazquez, R. Portillo, L. G. Franquelo, J. M. Carraco, P. W. Wheeler, and A. J. Waton, Three-dimenional feedforward pace vector modulation applied to multilevel diode-clamped converter, IEEE Tranaction on Indutrial Electronic, vol. 6, no. 1, pp , Jan 009. [11] J. L. Monroy Morale, M. Hernández-Ángele, and F. H. V. Varga, A digital control for a three-dimenional v-pwm multilevel converter, in 014 IEEE International Autumn Meeting on Power, Electronic and Computing ROPEC), Nov 014, pp [1] J.-H. Suh, C.-H. Choi, and D.-S. Hyun, A new implified pace-vector pwm method for three-level inverter, in Applied Power Electronic Conference and Expoition, APEC 99. Fourteenth Annual, vol. 1, Mar 1999, pp. 1 0 vol.1. [13] S. Bhattacharya, T. M. Frank, D. M. Divan, and B. Banerjee, Active filter ytem implementation, IEEE Indutry Application Magazine, vol. 4, no., pp , Sep [14] J. L. Monroy-Morale, M. Hernández-Ángele, D. Campo-Gaona, R. Peña-Alzola, M. Ordonez, and W. Mérida, Modeling and control deign of a vienna rectifier baed electrolyzer, in 016 IEEE 7th International Sympoium on Power Electronic for Ditributed Generation Sytem PEDG), June 016, pp. 1 8.