PID WITH PLL SYNCHRONIZATION CONTROLLED SHUNT APLC UNDER NON-SINUSOIDAL AND UNBALANCED CONDITIONS

Transcription

1 PID WITH PLL SYNCHRONIZATION CONTROLLED SHUNT APLC UNDER NON-SINUSOIDAL AND UNBALANCED CONDITIONS Karuppanan P and Kamala kanta Mahapatra National Intitute of Technology, Rourkela, India-7698 ABSTRACT Thi paper preent Shunt Active Power Line Conditioner (APLC) for compenating reactive power and harmonic current drawn by the load beide power factor correction. The hunt APLC i implemented with three phae PWM current controlled voltage ource inverter and i connected to the point of common coupling for compenating the current harmonic. The compenation proce i baed on phae locked loop (PLL) ynchronization and proportional integral derivative (PID) controller. Thee control trategie for hunt APLC make certain that ource current i inuoidal even when the load i non-inuoidal and unbalanced. The PWM-VSI inverter witching i done according to gating ignal derived from hyterei band current controller and the capacitor voltage i maintained contant uing PID controller. The propoed hunt APLC i invetigated uing extenive imulation and i found to be effective in term of THD, active filtering, reactive power compenation and V DC ettling time under variou balanced and unbalanced load condition INTRODUCTION Active power filter (APF) or active power line conditioner (APLC) have become ignificant for olving power quality problem [-]. In recent time power quality iue in indutrial a well a manufacturing utilitie ha become a matter of eriou concern due to the intenive ue of power electronic equipment. Continuing proliferation of nonlinear load i creating diturbance like harmonic pollution and reactive power problem in the power ditribution line [3-4]. The APLC can be connected in erie or in parallel with the upply network for compenating harmonic and reactive power. The erie active power filter i applicable to voltage harmonic compenation. Mot of the indutrial application need current harmonic compenation, o the hunt active filter i popular than erie active filter. Shunt APLC attempt to compenate the current harmonic of the load current by injecting oppoite harmonic. The APLC i connected in parallel with the load at the point of common coupling (PCC). The APLC ha the ability to keep the main current balanced and inuoidal after compenation regardle of whether the load i linear/non-linear and balanced or unbalanced [5]. The controller i the heart or primary component of the APF topology. Conventional PI and PID controller are ued to extract the fundamental component of the load current thu facilitating reduction of harmonic and imultaneouly controlling dc capacitor voltage of the hunt APLC [6-8]. The phae locked loop (PLL) controller can operate atifactorily under highly ditorted and unbalanced ytem [3]. However, remarkable progre in the capacity and witching peed of power emiconductor device uch a inulated-gate bipolar tranitor (IGBT), development in the field of microelectronic technology ha purred interet in thi area of APLC. Thi paper preent proportional integral derivative (PID) with phae locked loop (PLL) ynchronization controller baed hunt active power filter for the harmonic and reactive power mitigation due to the non-inuoidal and unbalanced load. The PLL can operate atifactorily under highly ditorted and unbalanced ytem. The hunt APLC implemented with three phae PWM current controlled voltage ource inverter and i connected to the ac main for compenating the current harmonic by injecting equal but oppoite current. The reference current() for the ource are generated uing PID controller and PLL controller algorithm. The PWM-VSI gate control ignal are brought out from the hyterei band current control technique. The capacitor voltage on the dc ide of the inverter i continuouly maintained contant with the help of PID controller. The propoed concept for hunt APLC i validated through extenive imulation under both balanced and unbalanced load condition.

2 DESIGN OF SHUNT APLC SYSTEM Shunt APLC i connected to the point of common coupling (PCC) through filter inductance with power converter and operate in a cloed loop. The three phae active filter comprie of ix power tranitor with diode, a dc capacitor, filter inductor and the compenation controller (contain the PLL with PID controller and hyterei current controller) hown in the fig. 3-Phae Source A B C Va,Vb,Vc Voltage Senor ia,ib,ic PLL Synchronization Current Senor R,L Hyterei Current Controller Non-inuoidal Load PCC A R L B L L C ica,icb,icc R L, L L Filter N 6-pule gate drive Fig Shunt APLC implemented with PWM-VSI for the ditribution ytem The filter inductor uppree the higher order harmonic caued by the witching operation of the power tranitor. The filter provide moothing and iolation for high frequency component and the deired current obtained by accurately controlling the witching of the inverter. Control of the current wave hape i limited by witching frequency of inverter and by the available driving voltage acro the interfacing inductance [4]. Current upplied by hunt APLC: The three phae intantaneou ource current can be written a i = il( ic () Source voltage i given by v = Vm inωt () If a nonlinear load i applied, then the load current would have a fundamental component A B C G PWM-VSI ia*,ib*,ic* Reference current generator Unbalanced load C DC V DC,ref Vdc Senor V DC PID Controller and harmonic component, which can be written a i = L n n= I in( nωt + Φ ) n = I in( ωt + Φ) + in( ) In nωt + Φn (3) n= The intantaneou load power can be multiplied from the ource voltage and current and the calculation i given a p = i * v L = V m in ωt * coφ + V I m + V in t * m ω In in( nωt + Φ n= = p + p + p f r h inωt * coωt *inφ n ) (4) Thi load power contain fundamental or active power, reactive power and harmonic power. From thi equation only the real (fundamental) power drawn by the load i p f = VmI in ω t * coφ = v * i (5) From thi equation the ource current upplied by the main ource, after compenation the ource current hould be inuoidal i written a i = p f / v( = I coφ inωt = Im inωt (6) where, I m = I coφ (7) The total peak current upplied by the ource i I p = Im + Il (8) If the active power filter provide the total reactive and harmonic power, i ( will be in phae with the utility voltage and would be inuoidal. At thi time, the active filter mut provide the compenation current: ic = il( i( Therefore the APLC extract the fundamental component of the load current and compenate for the harmonic and reactive power. PROPOSED CONTROL SCHEME The propoed control cheme include reference current extraction control trategy uing PLL ynchronization technique with proportional integral derivative controller and PWM VSI with inner current control uing hyterei current modulator. PID Controller Fig. how the block diagram of the propoed Proportional Integrator Derivative (PID) control

3 cheme of an APLC. The DC ide capacitor voltage i ened and compared with a reference th value. The error e = V dc, ref Vdc at the n ampling intant i ued a input for PID controller. The error ignal allow only fundamental frequency with the help of low pa filter (LPF). The LPF filter (Butterworth) ha a cutoff frequency et at 5 Hz ; the fundamental power frequency. The PID controller i ued to control the PWM-VSI input (dc ide capacitor) voltage. Vdc,ref Vdc Va LPF Vb Vc Proportional Gain Integrator Gain Derivative Gain PID-Controller PLL Synchro nization Circuit Fig PID with PLL Controller block diagram The PID controller i a linear combination of the P, I and D controller. It tranfer function can be repreented a K I H ( ) = K P + + K D ( ) (9) where, KP i the proportional contant that determine the dynamic repone of the DC-bu voltage control, K I i the integration contant that determine it ettling time and K D i the derivative of the error repreenting the trend. The controller i tuned with proper gain parameter [ K P =.7, K I =3, K D =.]. The output of the PID controller i the magnitude of peak reference current I max. The peak reference current multiplied with PLL output determine the deired reference current. PLL Synchronization The PLL circuit track continuouly the fundamental frequency of the meaured ytem voltage ( Va, Vb, Vc). The PLL deign hould allow proper operation under ditorted and unbalanced voltage waveform [3] [6]. I a I b I c I max X X X i a * Va i b * i c * Vab Vcb ia ( ω ic ( ω Sin (ω p ω 3φ PI Controller Sin (ωt+π/3) Fig 3 ynchronizing PLL circuit The PLL-ynchronizing circuit hown in fig 3 determine automatically the ytem frequency and the input are line voltage Vab ( Vab = Va Vb) andvcb ( Vcb = Vc Vb). The output of the PLL ynchronizing circuit are i a, ib, ic the three phae current. Thi algorithm i baed on the intantaneou active three-phae power expreion, it written by p = v i + v i + v i 3φ a a b b c c ω t ib Sin (ωt - π/-π/3) ic Sin (ωt - π/+π/3) () The current feedback ignal ( ω = in( ω and i c ( ω = in( ωt + π / 3) i obtained by the PLL circuit and time integral of output ω i calculated from the PID-Controller. It i having unity amplitude and i c ( ω lead to i a ( ω thee repreent a feedback from the frequencyω. The PLL ynchronizing circuit can reach a table point of operation when the input p 3φ of the PI controller ha a zero average value ( p 3 φ = ) and ha minimized low-frequency ocillating portion in three phae voltage. Once the circuit i tabilized, the average value of p i zero and the phae angle of the upply ytem voltage at fundamental frequency i reached. At thi condition, the current become orthogonal to the fundamental phae voltage component. The PLL ynchronizing output current are defined a i a = in( ωt π / ) () i b = in( ωt π / π / 3) () i c = in( ω t π / + π / 3) (3) Therefore the PLL output current ignal ia, ib, ic and the ditorted/unbalanced ource voltage Va, Vb, Vc of the power upply are meaured and which are in phae with the fundamental component. The PLL output multiplied with PID controller output determine the deired reference current. i a Sin (ωt - π/) 3φ ia

4 Hyterei Current Modulator i actual ( e ( i ref ( e max e min +Vdc/ -Vdc/ Fig 4 Diagram of hyterei current control The hyterei current control (HCC) i the eaiet control method to implement [7]. Thi error i the difference between the deired current i ref ( and the current being injected by the inverter i actual ( hown in fig 4. If the error current exceed the upper limit of the hyterei band, the upper witch of the inverter arm i turned off and the lower witch i turned on. A a reult, the current tart decaying. If the error current croe the lower limit of the hyterei band, the lower witch of the inverter arm i turned off and the upper witch i turned on. A a reult, the current get back into the hyterei band. The range of the error ignal emax emin directly control the amount of ripple in the output current from the PWM-VSI. RESULT AND ANALYSIS The performance of the propoed control trategy i evaluated through imulation uing SIMULINK toolbox in the MATLAB. The ytem i invetigated under balanced and unbalanced condition. The ytem parameter ued are; Line to line ource voltage i 4 V; Sytem frequency (f) i 5 Hz; Source impedance of R S, L S i Ω;. mh; Filter impedance of R c, L c i Ω; mh repectively; Diode rectifier R L, L L load: Ω; mh repectively; Unbalanced three phae R L, L L load impedance: R = Ω, R = 5 Ω, R3 = 9 Ω and mh repectively; DC ide capacitance (C DC ) i μf; Reference voltage (V DC, ref ) i V; Power device ued are IGBT with diode. Non-inuoidal load condition: The non-inuoidal or non-linear RL load i a ixpule diode Rectifier Bridge and i connected to main ac network. The parameter R L of the load are ohm and mh repectively and the imulation time i T= to T=.. The waveform of ource current after compenation i v out L i out preented in fig. 5 ; that clearly indicate that the current i inuoidal. The ix-pule diode rectifier load current or ource current before compenation i hown in fig 5. The actual reference current for three-phae are hown in fig. 5(c); thi wave i obtained from our propoed PLL ynchronization controller with PID controller. The hunt APLC upplie the compenating current that i hown in fig. 5(d). Thee current waveform are for a particular phae (phae a). Other phae are not hown a they are only phae hifted by (c) (d) Fig.5 Simulation reult for three-phae APLC under Non-inuoidal load condition Source current after APLC, Load current or ource current before compenation, (c)reference current by the PID with PLL control algorithm and (d) Compenation current by APLC Non-inuoidal with Unbalanced load condition: The three phae unbalanced RL load connected parallel with diode rectifier non-inuoidal load in the three phae main network. The unbalanced load condition i alo invetigated and imulated without and with active power line conditioner. Unbalanced three phae RL load impedance are R= Ω, R=5 Ω, R3=9 Ω and mh repectively and the imulation time i T= to T=.. The unbalanced RL load current or ource current before compenation i hown in 6. The ource current after compenation i preented in fig. 6 that indicate that the current become inuoidal. The hunt APLC upplie the compenating current baed on the propoed controller that i hown in fig. 6(c). We have additionally achieved power factor correction a hown in fig. 6(d), a-phae voltage and a-phae current are in phae. ia ila ia,ref ica

5 RL load a-phae current RL load b-phae current RL load c-phae current DC ide capacitor Voltage ia ib ic ica icb icc ia Va The Real (P) and Reactive (Q) power are calculated and preented in the table. (c) (d) (e) Fig.6 Simulation reult for APLC under noninuoidal with Unbalanced load condition RL Load current or Source current before APLC compenation, PLL ynchronization output current (c) Source current after APLC (d) Compenation current by APLC and (e) unity power factor waveform. DC ide capacitor voltage ettling time: The dc ide capacitance voltage and it ettling time are controlled by PID controller. Thi controller reduce the ripple voltage to certain level and make ettling time low; thee are hown in fig 7. pll a pll b pll c Table Real (P) and Reactive (Q) power meaurement Load Real (P) and Reactive (Q) Condition power meaurement Without APLC With APLC Noninuoidal Noninuoidal with Unbalanced P=9,9 kw Q=.97 kw P=, kw Q=. kw P=, kw Q=.35 kw P=,5 kw Q=.8 kw Order of harmonic plotted: The Fourier analyi of the ource current facilitate in extracting the fundamental a well a harmonic; ignal f ( i given a, a ( ) o f t = an co( nω + bn in( nω (4) n=,,3.. The FFT reult are plotted in Fig. 9 for variou condition a labeled. Magnitude baed on "Bae Peak" - Parameter Order of Harmonic DC ide capacitor voltage Fig 7 the DC ide capacitor voltage ettling time controlled by PID a) Non-inuoidal (t=.3) and b) Unbalanced load (t=.3) Real and reactive power meaurement PID and PLL ynchronizing controller baed compenation improve the power quality. The active power and reactive power are calculated by averaging the voltage-current product at the fundamental frequency 5 Hz, are hown fig 8. Real Power Reactive Power Magnitude baed on "Bae Peak" - Parameter (c) Magnitude baed on "Bae Peak" - Parameter Order of Harmonic Order of Harmonic Fig 9 Order of harmonic under the noninuoidal load condition, the ource current without APLC (THD=6.86%), under the non-inuoidal condition with APLC (THD=.49%) and (c) under the unbalanced load condition ource current with APLC compenation(thd=3.74%) Real Power Reactive Power Fig 8 Active and Reactive power after APLC compenation under the Non-inuoidal load (P=, kw, Q=.35 kw) Unbalanced load (P=,5 kw, Q=.8 kw) Total harmonic ditortion meaured: The PID controller and PLL ynchronizing control baed filter make ource current in the upply inuoidal. The total harmonic ditortion i meaured uing ource current waveform. The total harmonic ditortion i meaured and compared, and preented in Table.

6 Table FFT analyi of THD Condition Source (THD) Current(I S ) without APLC Non-inuoidal load Non-inuoidal with Unbalanced Source Current(I S ) with APLC 6.86 %.49 %.98 % 3.74 % Power factor The imulation i conducted for variou noninuoidal and unbalanced load condition. The PID controller along with PLL controller baed filter made ource current balanced even if the ytem i unbalanced. FFT analyi confirm that the active filter bring the THD of the ource current to be le than 5% that i in compliance with IEEE-59 tandard for harmonic under both balanced/unbalanced condition. CONCLUSIONS The invetigation on propoed APLC demontrated that PID controller maintain the dc ide capacitor voltage nearly contant and alo ettle early even under unbalanced load condition. Thi hunt active power line conditioner connected to the ac main in parallel with the load; compenate the current harmonic and reactive power under unbalanced and non linear load condition. The reference current() are generated uing PID controller with PLL ynchronizing control algorithm and PWM- VSI gate control ignal are generated from hyterei band current controller. The propoed hunt APLC validated uing extenive imulation. The important performance parameter are preented graphically and THD i found to be. 49 % under balanced load condition and 3.74 % under unbalanced a load condition that complie with IEEE 59 tandard; thu the uperior feature of the propoed APLC are etablihed. ACKNOWLEDGEMENT The author would like to acknowledge to the Minitry of Communication and Information Technology (MCIT), Govt. of India for the financial upport. REFERENCES [] Abdelmadjid Chaoui, Jean Paul Gaubert, Fateh Krim, Gerard Champenoi PI Controlled Threephae Shunt Active Power Filter for Power Quality Improvement - Electric Power Component and Sytem, 35:33 344, 7 [] Bhim Singh, Kamal Al-Haddad & Ambrih Chandra, A New Control Approach to 3-phae Active Filter for Harmonic and Reactive Power Compenation -IEEE Tran. on Power Sytem, Vol. 46, NO. 5, Oct-999 [3] Hirofumi Akagi, Edon hirokazu watanabe and Mauricio Arede Intantaneiu power theory and application to power conditioning IEEE-pre chapter 3-4, 7 [4] S.K. Jain, P. Agrawal and H.O. Gupta Fuzzy logic controlled hunt active power filter for power quality improvement -IEE proc.electr.power.appl,vol 49, No.5, Sept- [5] Lezek S. Czarnecki Intantaneou Reactive Power p-q Theory and Power Propertie of Three- Phae Sytem - IEEE Tran on Power Vol., No., Jan- 6 [6] Lui F.C. Monteiro, Joe C.C.Cota, Maurício Arede, and João L.Afono A Control Strategy for Unified Power Quality Conditioner Brazilan power electronic conference-july 5 [7] Brod D.M, Novotny D.M Current control of VSI- PWM Inverter -IEEE Tran on Indutry Appl, Vol., pp July/Aug [8] K. K. Mahapatra, Arindam Ghoh and S.R.Doradla Simplified model for control deign of STATCOM uing Three-Level Inverter - IEEE Conference vol., pp BIOGRAPHIES P.Karuppanan received the B.E in Electronic & communication Engg from Madurai Kamraj Univerity-India and M.E in VLSI Deign from Anna Univerity- India in 4 and 7 repectively. He ha been with National Intitute of Technology-Rourkela, India a a Reearch Scholar in the Dept of Electronic & communication Engineering ince 8. Hi reearch interet are power electronic application in power quality, Analog and Digital VLSI deign. Kamala kanta Mahapatra received B.Tech degree with Honour in 985 from Univerity of Calicut, Mater in 989 from Sambalpur Univerity and Ph.D from Indian Intitute of Technology, Kanpur in the year in Electrical Engineering.Currently, he i a Profeor in the Electronic and Communication Engineering Department of National Intitute of Technology Rourkela; he aumed thi poition ince February 4. He i a Fellow of the Intitution of Engineer (India), Hi reearch interet include Power Electronic, Embedded Sytem, Electronic Circuit, FPGA baed Sytem deign and VLSI Deign.