Design of a Robust Digital Current Controller for a Grid Connected Interleaved Inverter

Transcription

1 Deign of a Robut Digital Current Controller for a Grid Connected nterleaved nverter M. A. Abuara and S. M. Sharkh School of Engineering Science,Univerity of Southampton, Highfield,Southampton SO7 BJ,United Kingdom. Tel ,Fax uleiman@oton.ac.uk ABSTRACT-Thi paper i concerned with the deign and practical implementation of a robut digital current controller for a threephae voltage ource grid-connected interleaved inverter. Each phae conit of 6 half-bridge channel connected in parallel. Due to the current ripple cancellation of the interleaving topology, only mall output filter capacitor are required which provide high impedance to grid voltage harmonic and hence better current quality compared to traditional 2-level C topology. The current in each inductor i controlled via a ingle feedback loop. A feedforward loop of the grid voltage i incorporated to compenate for the grid diturbance. To control the high reonance frequency of the filter, high ampling and witching frequencie are required. Alternatively, reitor in erie with the filter capacitor are ued to provide damping. Thi method become practically poible due to the low magnitude of the current of the capacitor and conequently low power diipation in the damping reitor. The paper alo tudie in detail the effect of computational time delay and grid impedance variation on ytem tability. A phae lag compenator incorporated in the inductor current loop i deigned to increae ytem immunity to grid impedance variation. Simulation and practical reult are preented to validate the deign.. NTRODUCTON n recent year, ditributed generator (DG) have been widely ued to generate electricity. They provide an alternative or an enhancement to the traditional electric power ytem. Advantage of uing DG include reduction of electricity tranmiion loe, reduction of the ize of power line, low pollution, and high efficiencie. A typical DG conit of an electrical energy ource and a power electronic interface. Example of electrical ource include fuel cell, olar cell, wind turbine, flywheel, and batterie. Mot of the commercially available power electronic interface inverter are baed on the two-level voltage ource topology []-[4]. However, the need to improve efficiency and reduce ize and cot of both the inverter and the output filter encouraged more reearch into uing different inverter topologie. A 3-level inverter topology ha been hown to halve the output inductor ripple current for a given witching frequency, thu reducing the ize of the inductor. Additionally, the power witche in a 3-level inverter need only have half the voltage rating of the power witche in a 2-level inverter, and hence have fater witching frequencie, thu enabling further reduction in filter ize [5]-[7]. n thi paper we invetigate an alternative topology, namely an interleaved inverter topology. The multiphae interleaved topology ha been recently gaining popularity in DC/DC and AC/DC converter application [8]-[2]. nterleaving i a form of paralleling technique where a ingle converter channel, e.g., half a bridge with an output inductor, i replaced by a number of maller channel connected in parallel whoe witching intant are phae hifted equally over a witching period. By introducing uch a phae hift, the total capacitor ripple current i greatly reduced due to the ripple cancelation effect which in turn reduce the ize of the required filter capacitor. Additionally, the inductor ize i proportional to 2 [3] which mean that replacing a ingle inductor by N maller inductor of the ame inductance value, each carrying (/N) of the original current, could reduce the total ize of inductor by (/N). Furthermore, haring the current among multi channel enable the ue of maller power witche which can witch at a higher frequency thu allowing a further reduction in inductor ize. Alo, The witching loe are pread over everal component that can be cooled more effectively. Although replacing one channel by everal require more gate drive and more current enor, the improvement in term of ize reduction may jutify the extra complexity. n addition to the benefit mentioned above for the interleaving topology for DC/DC application, uing thi topology in grid-connected inverter will help overcome ome of the problem inherent in the two-level and multilevel inverter. The need for a large filter capacitor to filter out the witching frequency ripple in thee traditional topologie provide a low ytem output impedance and hence an eay path for harmonic current caued by grid voltage harmonic. n the interleaved topology, much mall filter capacitor are required thank to the ripple cancellation feature. Thi alo eliminate the need for a econd output filter inductor (i.e. uing an C filter intead of an C filter) that i normally ued in 2-level and multi-level grid connected inverter to block the witching ripple in cae where the grid impedance i too low. Furthermore, the reonance frequency of the interleaved ytem will be high due to the much maller output filter capacitor and inductor. Thi give more headroom for increaing the controller gain at lower harmonic frequencie in order to uppre the low harmonic current caued by grid voltage harmonic ditortion.

2 Thi paper focue on the deign of the control ytem of a 6-channel 3-phae grid connected interleaved inverter. The inverter ytem i firt decribed in ection. Section derive a model of the ytem, ection V dicue the deign of the control ytem, and ection V preent imulation and practical reult.. SYSTEM DESCRPTON AND CONTROER STRUCTURE A chematic diagram for the inverter i hown in Fig. and the ytem parameter are lited in Table. The half bridge leg of the inverter i made of N6 channel in parallel. The optimal election of the number of channel, witching device and filter parameter, and the deign of the filter component are outide the cope of thi paper, but will be the ubject of future publication. n general, the choice of the number channel i contrained by practical conideration of the maximum poible witching frequency of the GBT with the appropriate voltage rating, overall efficiency of the inverter and availability of uitable filter component. The output of each channel i connected to a common point of coupling to the grid through the inductance, carrying a hare x (x..6) of the total current uch that N x () The common point of the three-phae are connected to tar-connected capacitor C in erie with reitor R. The voltage ource V u and the inductance (with ubcript a, b and c for the three phae) repreent the grid equivalent circuit, and Out i the grid current. The three phae of the inverter are controlled independently. Fig. 2 how the block diagram of the PWM inverter and filter and the control ytem of one of the phae. The model aume balanced three-phae current and hence the voltage of the tar point of the filter capacitor i at the ame potential a the grid neutral point. The current in each inductor i controlled uing a ingle feedback loop with a digital controller K(z). A feedforward loop of the grid voltage at the point of common coupling V G i alo included to cancel the grid voltage diturbance, a dicued in [5]. A econd feedback loop of the capacitor current to provide active damping a dicued in [5] wa not implemented a the ampling frequency f (35kHz) i only.47 to 3.2 time the natural damped frequency f d., depending on the value of the grid inductance a hown in Table 2, which i too low to provide effective damping. n order to control the ytem reonance frequency, the ampling rate need to be at leat 8 to 0 time fater than the natural damped frequency f d [4]. ntead, a reitor in erie with the filter capacitor i ued to provide paive damping. Fortunately, due to the ripple cancellation feature of the interleaving topology, the capacitor current i quite mall and hence the power diipation in R i alo mall and the loe are acceptable. The time delay T d caued by the controlling proceor Td computational time i modeled a e. The Analogue to digital converter are modeled a Zero Order Hold (ZOH) block preceded by ampler. The total inductor current equal the um of the capacitor current and the output current Out, and hence the demanded hould ideally include a correction to allow for the capacitor fundamental frequency 50 Hz current. But ince thi current i very mall in practice, it may be neglected and the demanded can be et to the value of the required output current. V dc V in V G Out Fig.. Three-phae interleaved grid-connect interleaved inverter. TABE SYSTEM PARAMETERS VAUES Decription Symbol Value Number of interleaved channel N 6 Paive damping reitor R 0.5 Channel inductor 50µH Grid inductance to 500 µh Filter capacitor C 0.8µF Switching frequency f w 35kHz Sampling frequency f 35kHz Time delay T d 4.28µ Output current Out 50 Arm Grid voltage V u Grid voltage at the point of V G 230 Vrm common coupling Grid Frequency F 50Hz nverter dc voltage V dc 750 Vdc TABE 2. NATURA DAMPED FREQUENCY VERSUS. (µh) Natural damped frequency f d (khz)

3 Out N K (z) V in V Mod 2 K (z) V f V f V Mod2 e T d e T d V in2 V c V c 2 RC V c C V u Out N K (z) V f V Mod N e T d V inn V c N. SYSTEM ANAYSS n thi ection, the effect of the paive damping reitor R, the computational time delay T d, and the variation in grid impedance on ytem tability are tudied. The ytem ability to reject grid harmonic i alo analyzed. For the purpoe of the dicuion in thi ection, which meant to provide an inight into the problem, the controller K(z) i aumed to be a imple proportional gain with a value of 0. n the next ection, the deign of a more ophiticated controller K(z) i dicued. From Fig. 2, the tranfer function A() of to i given by Fig. 2. Block diagram of one phae and it controller. the ytem will be critically table. n Fig. 4, the root locu of K(z)G(z) i plotted when R i et to 0.5. t i clear that the cloed loop pole have been puhed well inide the unit circle making the ytem more table. However, the ytem eem to uffer from a lack of immunity to grid impedance variation a it become untable when > 20µH. 2 u C RC 3 2 u u u A( ) C RC( N ) ( N ) (2) The continuou time delay open loop tranfer function including the computational time delay block will therefore be given by T d G( ) e A( ) (3) n the dicrete domain, G(z), can be obtained by performing the Z-tranform of G() taking into account the zero order hold effect, Fig. 3. Root locu of K(z)G(z) with changing from 0 to 500uH, T d 0, K(z) 0, R 0 Ω. T e Td G( z) Z e A( ) (4) u 20µ H G(z) wa computed uing Matlab with the time delay approximated uing Pade approximation. d e T A. Effect of Paive Damping and Grid mpedance Without computational time delay (T d 0) and with R et to zero, the root locu of K(z)G(z) i hown in Fig. 3, with a a parameter varying from µh to 500µH. The cloed loop pole are located at the border of the unit circle which mean Fig. 4. Root locu of K(z)G(z) with changing from 0 to 500µH, T d 0, K(z) 0, R 0.5Ω.

4 B. Effect of the Computational Time Delay Fig. 5 illutrate the ampling trategy for the propoed controller. n thi ytem, the inductor current are ampled at the ame rate a the witching frequency. Each inductor current i ampled when the PWM carrier reache it trough. The proceor then tart performing the controller calculation and update the modulating voltage V when Mod the PWM carrier reache it peak. n thi cae the time delay equal half of the ampling period, T d 0.5T (5) Fig. 6 how the root locu of K(z)G(z) a a function of when R i et to 0.5 but with T d et to 0.5T. The ytem become untable only when > 300µH. Thi i may be a urpriing reult a time delay normally reduce ytem tability. To undertand thi phenomenon, the bode diagram of K(z)G(z) with and without time delay are plotted in Fig. 7. Although the time delay ha decreaed the phae margin (PM) from 72 o to 32 o, it alo caued a magnitude attenuation which reulted in an increae in the gain margin (GM) from -.5 to 3.5 and hence tabilized the ytem. Note that time delay in the continuou time domain doe not alter the magnitude bode diagram becaue Td e. However, in dicrete time domain, time delay may alter the magnitude of the bode diagram. C. Grid Harmonic Rejection To completely compenate for the grid diturbance, the feedforward loop hould ideally take the form of B()V u a dicued in [5] where Fig. 8 how the bode diagram of /V u with and without the feedfrward loop for different value of. The effectivene of the feedforward loop in attenuating the grid voltage and it low frequency bae harmonic i clear from the diagram. ( n ) V ( n ) ( n) V ( n) ( n ) x T d u T Mod x x Mod x Fig. 5. Sampling Strategy. 300µ H Fig. 6. Root locu of K(z)G(z) with changing from 0 to 500µH, T d 0.5T, K(z) 0, R 0.5Ω. x RC B( ) 2 C RC u (6) However, V u cannot be meaured directly and varie according to the grid. Fortunately, the mall value of C, make a direct feedforward of grid voltage V G at the point of common coupling, which i approximately equal to V u, good enough to reject the grid harmonic diturbance. With the feedforward loop and neglecting the ampling effect and time delay, can be hown to be given by (auming 0 in Fig. 2) ( B ) A( ) ( ) NV K( ) A( ) u (7) Fig. 7. Bode diagram of K(z)G(z) with and without time delay, 40µH. Note that K(z) i expreed by it equivalent function. f the feedforward loop of the grid voltage i not employed, (7) become A( ) B( ) NVu (8) K( ) A( ) Fig. 8. Bode diagram of /V u with and without feedforward, 5, 50, 250, and 500µH, K() 0.

5 V. CONTROER DESGN The controller K(z) need to be deigned to fulfill certain tak. Firtly, it hould provide good tracking of the reference ignal. Secondly, it hould provide good rejection of grid voltage harmonic. Thirdly, the controller tability ha to be immune to variation in grid impedance. Good tracking and good grid harmonic rejection require a high gain value of K(z) at the fundamental and the low frequency harmonic. However, high value of K(z) mean le tability. The magnitude of K(z) ha already been choen to be 0 to give a good low frequency gain. However, the ytem will become untable when > 300µH a wa hown in Fig. 6. Fig. 9 how the bode diagram of K(z)G(z) with having the value of 5, 50, 250, and 500µH. At high value of, the gain margin become negative and hence the ytem become untable. f K(z) i modified to be a phae lag a illutrated in Fig. 0 then it provide more attenuation at the higher frequencie to improve the gain margin and at the ame time increae the gain at the lower frequencie to improve reference ignal tracking and grid harmonic rejection. The propoed phae lag controller i given by ignal tracking and grid harmonic rejection. The root locu of K(z)G(z) with varying from 0 to mh i hown in Fig. 2. The ytem remain alway table and the immunity of the ytem to grid impedance variation i clear. Fig.. Bode diagram of K(z)G(z), 0.5z 0.35, K( z) 0 u 5, 50, z , and 500 µh. u 000µ H 0.5z 0.35 K( z) 0 z 0.97 (9) Fig. 2. Root locu of K(z)G(z) with changing from 0 to mh, T d 0.5T, R0.5 Ω, and 0.5z K( z) 0 z 0.97 Fig. 9. Bode diagram of K(z)G(z), K(z)0, 5, 50, 250, and 500 µh. Fig. 0. Bode diagram of a phae lag K(z), 0.5z 0.35 K( z) 0 z 0.97 Fig. how the bode diagram of K(z)G(z) with K(z) a given in (9) for different value of. t can be noticed that the ytem alway ha a poitive gain margin. Alo the low frequency gain i now higher, which will improve reference V. SMUATON AND PRACTCA RESUTS A detailed Matlab/Simulink model wa ued to aid the deign and predict the performance of the ytem. The imulated grid voltage included low frequency harmonic imilar to thoe meaured at the tet ite. The total voltage THD wa 2%. Fig. 3 how the output current for a 50Amp rm demand. The current THD wa only 2.%. Fig. 4 how the filter capacitor current to have a low magnitude at both the fundamental and witching frequencie. A three-phae grid-connected interleaved inverter wa deigned and built. The propoed controller wa implemented uing the Texa ntrument TMS320F bit Digital Signal Proceor (DSP). One DSP per phae wa ued and the low peed communication between the controller uch a tart/top and total current command were implemented uing the Controller Area Network (CAN) protocol. Synchronization with the grid wa implemented by having each phae controller meaure the correponding grid phae voltage to detect the zero croing. Fig. 5 how the grid voltage and the inverter output current. The grid voltage THD

6 wa meaured to be.8% and the output current THD wa meaured to be 2.3%. Fig. 6 how the tep repone of the output current when the demand change from zero to full value. The inverter ha alo been teted with variou output inductor up to mh to repreent the grid impedance and robut tability ha been confirmed. Fig. 3. Simulated output current Fig. 4 Simulated capacitor current. Fig. 5. Practical reult, Ch grid voltage, Ch2 Output current Amp/2mv. V. CONCUSON The deign and practical implementation of a robut digital current controller for a three-phae voltage ource grid- ha been preented. The connected interleaved inverter interleaved topology offer the advantage of reduced filter ize, and higher grid diturbance rejection compared to other inverter topologie. But the high reonance frequency of the filter required paive damping reitor in erie with the filter capacitor, which wa found to be acceptable due to the low capacitor current. The grid impedance variation were found to reduce ytem tability. But uing a phae lag compenator incorporated in the inductor current loop wa found to be ufficient to increae the ytem' immunity to grid impedance variation. The deign ha been validated by imulation and practical reult. V. REFERENCES [] S.M. Sharkh, M. Abu-Sara, and Z.F Huien, Current control of utility- inverter uing repetitive connected DC- AC three-phae voltage-ource feedback, European Power Electronic Conference EPE, Graz, 200. [2] E. Twining, and D.G. Holme, Grid current regulation of a three-phae voltage ource inverter with an C filter, EEE 33 rd Annual Power Electronic Specialit Conference, 2002, 3, pp [3] M. Prodanovic, T.C. Green, Control and filter deign of three-phae inverter for high power quality grid connection, EEE Tranaction on Power Electronic, 2003, 8, (), pp [4] G. Shen, D. Xu,. Cao, and X. Zhu, An mproved Control Strategy for Grid-Connected Voltage Source nverter With an C Filter, EEE Tranaction on Power Electronic, vol. 23, NO. 4, 2008, pp [5] S. M. Sharkh and M. Abu-Sara, "Digital current control of utility connected two-level and three-level PWM voltage ource inverter," European Power Electronic Journal, vol. 4 No. 4, 2004, pp [6] O. Bouhali, B. Francoi, C. Saudemont, and E.M. Berkouk, "Practical power control deign of a NPC multilevel inverter for grid connection of a renewable energy plant baed on a FESS and a Wind generator," EEE Annual Conference on ndutrial Electronic, ECON 2006, pp [7] S.V. Araujo, A. Engler, B. Sahan, and F. Antune, C Filter deign for grid-connected NPC inverter in offhore wind turbine, nternational Conference on Power Electronic, Korea, October [8] B.N. Singh, G. Joo, G, and P. Jain, " A new topology of 3-phae PWM AC/DC interleaved converter for telecommunication upply ytem," ndutry Application Conference, vol. 4, pp , [9] M. Gerber, J. A. Ferreira,. W. Hofajer, and N. Seliger, " High Denity Packaging of the Paive Component in an Automotive DC/DC Converter," EEE Tranaction on Power Electronic, vol. 20, 2005, pp [0] B. Detraz, Y. ouvrier, and A. Rufer, High Efficient nterleaved Multi-channel DC/DC Converter Dedicated to Mobile Application, ndutry Application Conference 2006, pp [] M. Pavlovky, Y. Turuta, and A. Kawamura, Puruing high powerdenity and high efficiency in DC-DC converter for automotive application, Power Electronic Specialit Conference PESC, pp , [2]. Cervante, A. Mendoza-Torre, A.R. Garcia-Cueva, and F.J. Perez- converter," Vehicle Power and Pinal, " Switched control of interleaved Propulion Conference VPPC, pp. 56-6, [3] N. Mohan, T. M. Undeland, W. P. Robbin, Power Electronic, Converter, Application, and Deign. John Wiley & Son, [4] K. Ogata, Dicrete-Time Control Sytem. Prentice Hall, 995. Fig. 7. Step repone in current demand Ch grid current Amp/2mv voltage, Ch2 Output