GENERALIZED PWM ALGORITHM FOR THREE PHASE n-level VOLTAGE SOURCE INVERTER FED AC DRIVES

Transcription

1 GENERALIZED PWM ALGORITHM FOR THREE PHASE n-leel OLTAGE SOURCE INERTER FED AC DRIES M. Khaimulla 1 G.Srinivaa Rao 2 D.Nagaraju 3 and P Shahavali 4 Abtract Thi paper preent pace vector baed pule width modulation (SPWM) algorithm for voltage ource inverter fed AC drive by uing the concept of offet time. To reduce the harmonic ditortion and to increae the dc bu utilization of the inverter when compared with the inuoidal PWM (SPWM) algorithm, thi paper ha been focued on the implementation of pace vector baed PWM algorithm. The propoed PWM algorithm have been developed by uing the intantaneou phae voltage and hence reduce the complexity involved in the conventional pace vector approach. Moreover the propoed algorithm can be eaily extended to multilevel inverter. To validate the propoed algorithm, numerical imulation tudie and THD analyi ha been carried out on v/f controlled induction motor drive and reult are preented. Index Term PWM, SPWM, Multilevel inverter, THD, Induction motor drive. D I. INTRODUCTION ue to the invention of fat witching power emiconductor device and motor control algorithm, a growing interet i found in a more precie pule width modulation (PWM) method. During the pat decade everal PWM algorithm have been tudied extenively. ariou PWM method have been developed to achieve wide linear modulation range, le witching lo, le total harmonic ditortion (THD) and eay implementation and le computation time. A large variety of algorithm for PWM exit, and a urvey of thee wa given in [1]. There are two popular approache for the implementation of PWM algorithm, namely triangular comparion (TC) approach and pace vector (S) approach. For a long period, TC approach baed PWM method were widely ued in mot application. The earliet modulation ignal for TC approach baed PWM are inuoidal. But, the addition of the zero equence ignal to the inuoidal ignal reult in everal non-inuoidal ignal. Compared with inuoidal PWM (SPWM) algorithm, noninuoidal PWM algorithm can extend the linear modulation range for line-to-line voltage. Different zero-equence ignal lead to different non inuoidal PWM modulator [2]. Nowaday, due to the development of digital ignal proceor, SPWM ha become one of the mot popular PWM method for three-phae inverter [3]-[4]. It ue the S approach to compute the duty cycle of the witche. The main feature of thi PWM algorithm are eay digital implementation and wide linear modulation range for output line-to-line voltage. The equivalence between TC and S approache ha tudied in [5] and concluded that S approach offer more degree of freedom compared to TC approach. However, the conventional pace vector approach require angle and ector information and hence increae the complexity involved in the algorithm. to reduce the complexity involved, implified approache have been propoed in [6]-[8] by uing the concept of imaginary witching time and offet time. In thi paper, pace vector baed PWM algorithm for AC drive are preented by uing the concept of offet time. Furthermore, the imulation of the propoed PWM method i dicued and imulation reult are provided to validate the drawn concluion. II. CONENTIONAL SPWM ALGORITHM The main purpoe of the voltage ource inverter (SI) i to generate a three-phae voltage with controllable amplitude, and frequency. A general 2-level, 3-phae SI feeding a threephae induction motor i hown in Fig 1. dc 2 dc 2 o T 1 T 3 T 5 T 4 a Fig. 1 2-level, 3-phae voltage ource inverter feeding induction motor From Fig. 1, it can be oberved that the two witching device on the ame leg cannot be turned on and cannot be turned off at the ame time, which will reult in the uncertain voltage to the connected phae. Thu the nature of the two witche on the ame leg i complementary. The witching-on and witching-off equence of a witching device are repreented by an exitence function, which ha a value of unity when it i turned on and become zero when it i turned off. The exitence function of a SI compriing of witching device T i i repreented by S i, i = 1, 2,..., 6. Hence, S 1, S 4 which take value of zero or unity repectively, are the exitence function of the top device (T 1 ) and bottom device (T 4 ) of the inverter leg which i connected to phae a. S 1 S4 1; S3 S6 1; S5 S2 1 (1) A een from Fig 1, there are totally ix witching device and only three of them are independent. The combination of thee three witching tate give out eight poible voltage vector. At any time, the inverter ha to operate one of thee voltage vector. Out of eight voltage vector, two are zero voltage vector ( 0 and 7 ) and remaining ix ( 1 to 6 ) are active voltage vector. In the pace vector plane, all the voltage vector can be repreented a hown in Fig 2. b T 6 T 2 c IM Page 86

2 4 (- ++) 3 (- + -) III ref 7 (+ ++) Motor I 1 (+ - -) 0 (- - -) T 1 q I Fig. 2 oltage pace vector produced by a voltage ource inverter II T 2 For a given et of inverter phae voltage ( an, bn, cn ), the pace vector can be contructed a j j 3 3 an bne cne 3 (2) From (2), it i eaily hown that the active voltage vector or active tate can be repreented a 2 j( k1) 3 k dce where k 1,2,...,6 (3) 3 By maintaining the volt-econd balance, a combination of witching tate can be utilized to generate a given ample in an average ene during a ubcycle. The voltage vector ref in Fig.2 repreent the reference voltage pace vector or ample, correponding to the deired value of the fundamental component for the output phae voltage. But, there i no direct way to generate the ample and hence the ample can be reproduced in the average ene. The reference vector i ampled at equal interval of time, T referred to a ampling time period. Different voltage vector that can be produced by the inverter are applied over different duration with in a ampling time period uch that the average vector produced over the ubcycle i equal to the ampled value of the reference vector, both in term of magnitude and angle. A all the ix ector are ymmetrical, here the dicuion i limited to ector-i only. Let T 1 and T 2 be the duration for which the active tate 1 and 2 are to be applied repectively in a given ampling time period T. Let T z be the total duration for which the zero tate are to be applied. From the principle of volt-time balance T 1, T2 and T z can be calculated a: 2 3 o T 1 M Sin (60 ) T (4) 2 3 T 2 MSin( ) T (5) TZ T T 1 T 2 (6) where M i known a the modulation index and defined a given in (7). 2 (+ + -) I 5 (- - +) 6 (+ - +) d v M ref (7) dc In the SPWM algorithm, the maximum modulation index i [1]. In the SPWM trategy, the total zero voltage vector time i equally ditributed between 0 and 7. Further, in thi method, the zero voltage vector time i ditributed ymmetrically at the tart and end of the ubcycle in a ymmetrical manner. Moreover, to minimize the witching frequency of the inverter, it i deirable that witching hould take place in one phae of the inverter only for a tranition from one tate to another. Thu, SPWM ue in firt ector, in econd ector and o on. Table-1 depict the witching equence for all the ector. TABLE I SWITCHING SEQUENCES IN ALL SECTORS FOR SPWM Sector number On-equence Off-equence Alo, with the SPWM algorithm, the modulation index and dc bu utilization can be increaed when compared with the SPWM algorithm [1]. III. PROPOSED PWM ALGORITHM To reduce the complexity involved in the exiting SPWM algorithm, in thi ection, the propoed PWM algorithm have been developed by uing the notion of imaginary witching time. In thi approach, the imaginary witching time period proportional to the intantaneou value of the reference phae voltage are calculated a given in (8) [6]-[7]. T Tan an dc T bn T T dc bn cn dc To calculate the active vector witching time, the maximum, middle and minimum value of imaginary witching time are calculated in every ampling time a given in (9) (11). Tmax Max( Tan, Tbn, ) (9) Tmid Mid( Tan, Tbn, ) (10) Tmin Min( Tan, Tbn, ) (11) Then, the effective time during which the induction motor i effectively connected to the ource (that i the power will be tranferred to the motor from ource) can be calculated a given in (12). (8) Page 87

3 T eff T max T min (12) When the actual gating ignal for power device are generated in the PWM algorithm, there i one degree of freedom by which the effective time can be relocated anywhere within the ampling time period. Therefore, the actual witching time for each inverter leg can be obtained by the time hifting operation a follow: T T T (13) T ga an offet gb Tbn Toffet (14) Tgc Toffet (15) where Toffet T1 1T max T min (16) To guarantee the full utilization of dc-link voltage of the inverter, the actual witching time hould be retricted to a value from 0 to T. In the implementation of the propoed offet time baed unified PWM algorithm, the zero voltage vector time partition parameter (μ) can take any form (contant or time-varying) ranging between 0 and 1. The choice of μ affect the average neutral voltage. In the conventional SPWM algorithm, a the zero voltage vector time i ditributed equally, μ i generally taken a 0.5. If μ i either 0 or 1, each witching device ceae to witch for a total of 120 degree per fundamental cycle. Hence, the witching loe and effective inverter witching frequency are ignificantly reduced. A the modulating ignal are dicontinuou, thee PWM algorithm are alo known a DPWM algorithm or bu-clamping PWM algorithm. The SPWM, DPWMMIN and DPWMMAX algorithm can be obtained for μ = 0.5, 1 and 0 repectively. I. EXTENSION TO MULTILEEL INERTERS The recent indutrial application require high power apparatu. The claical Two-level inverter may not be ueful in high voltage range (above 2 k) due to limited rating of witche. In conventional two-level inverter configuration, the harmonic content reduction of an inverter output current i achieved mainly by increaing the witching frequency. But the witching frequency i retricted by the witching loe in high power and high voltage application [9]. In uch application, multilevel inverter have been widely ued in recent year for the advantage of low harmonic output at low witching frequency. At the ame time, low blocking voltage in the witching device can be achieved. A a reult, multilevel power inverter tructure ha been introduced a an alternative in high power and medium voltage ituation [10]. The multilevel inverter have everal advantage like i) Staircae waveform quality: Multilevel inverter can generate the output voltage with very le ditortion. A level of inverter increae, the output voltage i nearer to inuoidal. ii) oltage tre reduction: Multilevel inverter can reduce voltage tre on witching device. iii) Input current quality: Multilevel inverter can draw input current with le ditortion. iv) Reduction in Total Harmonic Ditortion (THD): Multilevel inverter output can have le harmonic content compared to two level waveform operating at the ame witching frequency [11]. The propoed approach can be eaily extended with few variation to the control of multilevel inverter. With reference to the generation of control ignal, in thi cae, the main idea i to manage each voltage level independently from the other level. Conidering multicarrier and a ingle reference i equivalent to conidering only one carrier and more reference voltage [12]. Carrier baed modulation technique control each phae leg of an inverter eparately and allow the line to line voltage to be developed implicitly. The multilevel carrier baed SPWM for N-level inverter ue a et of N-1 adjacent level triangular carrier wave with the ame peak-to-peak amplitude and the ame frequency [13] a hown in fig 3((a),(b),(c)). a) Modulating Wave and Carrier Wave comparion for two level SI b) Modulating Wave and Carrier Wave comparion for three level SI c) Modulating Wave and Carrier Wave comparion for five level SI Fig. 3 Modulating Wave and Carrier Wave comparion for SI. SIMULATION RESULTS AND DISCUSSIONS To validate the propoed PWM algorithm, everal numerical imulation tudie have been carried out on v/f controlled induction motor drive uing Matlab-Simulink. For the imulation tudie, the average witching frequency of the inverter i taken a 5 khz, fundamental frequency i taken a 50Hz and the dc link voltage i taken a 600. Modulating Wave and Multicarrier Wave comparion for two level, three level and five level are hown in fig 3(a),(b),(c). Modulating waveform, pole voltage, phae voltage, line voltage and teady tate tator current wave of two level, three level and five level inverter are hown in fig (4)-(6). Moreover, the Page 88

4 harmonic ditortion of line voltage and teady tate current along with the total harmonic ditortion (THD) value are given in fig (7)-(12). From the imulation reult it can be oberved that the propoed approach give ame reult when compared with the exiting approache. The THD value of line to line voltage are highly reduced a level increae. The input current drawn by the induction motor i le ditorted a level of inverter increae. Moreover a the number of level increae the output voltage ha more tep and nearer to inuoidal with le ditortion. Thi allow mitigation of the harmonic at low witching frequencie thereby reducing witching loe. Fig 6 Simulation reult of Propoed SPWM algorithm for five level SI Fig 4 Simulation reult of Propoed SPWM for two level SI Fig. 7 Harmonic pectra of line voltage for two level inverter at f=50 Hz Fig. 8 Harmonic pectra of tator current for two level inverter at f=50 Hz Fig 5 Simulation reult of Propoed SPWM algorithm for three level SI Page 89

5 Fig. 9 Harmonic pectra of line voltage for three level inverter at f=50 Hz propoed algorithm ue a generalized expreion for offet time and by varying which variou PWM algorithm are generated. Moreover, the propoed algorithm ue only reference phae voltage and eliminate the angle and ector calculation. The propoed algorithm can be eaily extended to multilevel inverter imply by comparing the modulating wave and multicarrier wave. For a N-level inverter N-1 carrier wave with the ame peak-to-peak amplitude and the ame frequency are required. Simulation reult for two level, three level and five level inverter are preented. THD analyi of line to line voltage and teady tate tator current are alo preented. From the imulation reult it can be oberved that the THD value of line to line voltage are highly reduced and the input current drawn by the motor i le ditorted a level increae. Moreover the output voltage i a taircae and nearer to inuoidal with le ditortion a the level increae. ACKNOWLEDGMENT The author are thankful to the Management of Sri enkatewara Engineering College, Suryapet, Andhra Pradeh, India for providing neceary facilitie to carry thi work. REFERENCES Fig. 10 Harmonic pectra of tator current for three level inverter at f=50 Hz Fig. 11 Harmonic pectra of line voltage for five level inverter at f=50 Hz Fig. 12 Harmonic pectra of tator current for five level inverter at f=50 Hz I. CONCLUSION A imple propoed SPWM algorithm ha been developed and imulation reult are preented in thi paper. The [1] Joachim Holtz, Pule width modulation A urvey IEEE Tran. Ind. Electron.., vol. 39, no. 5, Dec 1992, pp [2] Grahamme Holme and T.A. Lipo, Pule width modulation for power converter IEEE pre, [3] Heinz Willi ander Broeck, Hna-Chritoph Skudelny and Georg iktor Stanke, Analyi and realization of a pule width modulator baed on voltage pace vector IEEE Tran. Ind. Applicat., vol. 24, no. 1, Jan/Feb 1988, pp [4] P.G. Handley and T.J. Boy, Space vector modulation: An engineering review IEE 4 th International Conference on Power Electronic and ariable Speed Drive, Conf Pub 324, 1990, pp [5] G. Narayanan and.t. Ranganathan, Triangle comparion and pace vector approache to pule width modulation in inverter fed drive, Journal of Indian Intitute of Science, Sept/Oct 2000, pp [6] Joohn-Sheok Kim and Seung-Ki Sul, A novel voltage modulation technique of the pace vector PWM in Proc. IPEC, Yokohama, Japan, 1995, pp [7] Dae-Woong Chung, Joohn-Sheok Kim and Seung-Ki Sul, Unified voltage modulation technique for real-time three-phae power converion IEEE Tran. Ind. Applicat., vol. 34, no. 2, Mar/Apr 1998, pp [8] T. Brahmananda Reddy, J. Amarnath and D. Subbarayudu, Improvement of DTC performance by uing hybrid pace vector Pulewidth modulation algorithm International Review of Electrical Engineering, ol.4, no.2, Jul-Aug, 2007, pp [9] J.Rodriguez, J.S.Lai, F.Z.Peng, Multilevel Inverter: A Survey of Topologie, Control and Application IEEE-IE Tran. On Indutrial Electronic, ol.49, No 4 pp , Aug [10] D. Grahame Holme & Thoma A. Lipo, Pul Width Modulation for Power Converter- Principle and Practice, ME El-Hawary, Ed. New Jerey, IEEE Pre, Wiley-Intercience, [11] P. Satih Kumar, J.Amarnath, S..L. Naraimham A Qualitative Space ector PWM Algorithm for a Five-level Neutral Point Clamped Inverter ICGST-ACSE Journal, ISSN , olume 9, Iue I, June [12] Antonio Cataliotti, Member, IEEE, Fabio Genduo, Angelo Raciti, Senior Member, IEEE, and Giueppe Ricco Galluzzo Generalized PWM SI Control Algorithm Baed on a Univeral Duty-Cycle Expreion: Theoretical Analyi, Simulation Reult, and Experimental alidation IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, OL. 54, NO. 3, JUNE Page 90

6 M.Khaimulla 1 i a PG tudent in the Department of Electrical & Electronic Engineering, Sri enkatewara Engineering College, Suryapet, Andhra Pradeh, India. akmkhayyum@gmail.com contact: G.Srinivaa Rao 2 wa born in He received B.Tech degree a in the year 2010 and M.Tech degree in 2012 from J.N.T.Univerity, Hyderabad. He i preently Aitant Profeor in the Electrical and Electronic Engineering Department, Sri enkatewara Engineering College, Suryapet,A.P., India. D.Nagaraju 3 wa born in He received B.E degree from Omania Univerity, Hyderabad, India in the year 2000 and M.Tech from J.N.T.Univerity, Hyderabad in the year He i preently Sr.Aitant Profeor in the Electrical and Electronic Engineering Department, Sri enkatewara Engineering College, Suryapet,A.P., India. P Shahavali 4 i a academic aitant in the Department of Electrical & Electronic Engineering, JNTUCE,Pulivendula, Andhra Pradeh, India. Page 91