SPACE VECTOR BASED TRANSISTOR-CLAMPED CASCADED MULTILEVEL INVERTER

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1 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 SPACE ECOR BASED RANSISOR-CLAMPED CASCADED MULILEEL INERER M.B. eenaani, Mr.G. Satheeh, Mr.G. Kih EEE Department, G. Pulla Reddy Engineering College, Kurnool Mr. R Ram Praad, EEE Department, NBKR Intitute of Science and echnology, Nelle. Abtract he inerter configuration with higher number of output oltage leel hae the ability to modulate waefm with a better harmonic pectrum. A hree phae cacaded multileel inerter which ue fie-leel tranit clamped H-bridge power cell i preented. In thi, Multi Carrier Phae Shifted Pule Width Modulation technique i applied f the balanced power ditribution among the power cell. hi PWM technique i applied f both Sine PWM and Space ect PWM. he output oltage harmonic and the mot current harmonic are obered and compared f both technique. he propoed inerter i imulated under MALAB/Simulink enironment on an induction mot model. From the reult, the propoed inerter proide higher output quality with le harmonic dittion a compared to the other conentional inerter. Keywd ranit clamped H-Bridge cell, Cacaded multileel inerter, SPWM, Multicarrier phae-hifted pule width modulation. I. INRODUCION he technology of deeloping multileel inerter ha been growing becaue of the demand f high-oltage, high power conerter. hee are capable of producing high quality waefm while utilizing low-oltage deice and reduced witching frequency with regard to emiconduct power witch oltage limit. he modified multileel output are uperi in quality in reducing filter requirement and oerall ytem ize. A the witching frequency i reduced, witching loe are alo reduced and high-power quality i maintained. he multileel inerter implementation ha done in different application ranging from medium to high power leel uch a renewable energy generation and ditribution [], [2], mot drie [3], [4], power conditioning deice [5]. here are three maj conentional multileel inerter topologie namely the diode-clamped Neutral-point-clamped (NPC) inerter [6], flying capacit multileel inerter [7] and cacaded multileel inerter [8]. Many other topologie like NPC hae been introduced f ariou indutrial application [9], []. Different modulation technique ued f multileel inerter are pace ect modulation (SM) [], [2], carrier-baed pule-width modulation [3]-[5], taircae fundamental frequency modulation [6] and electie harmonic elimination [7], [8]. Here the cacaded multileel inerter i mainly focued becaue of it modularity in achieing bet fault tolerance and control implicity [9]. Uually by connecting eeral identical H-bridge cell in cacade at the output ide, we can achiee and low harmonic dittion medium-oltage operation [2]. he imptant adantage of H conerter are the number of DC ource ued i reduced to 5% which reduce the ize and complexity, they can only produce an odd number of leel which enure the exitence of the - leel at the load. In thi paper, ymmetrical cacaded inerter poible of increae in oltage leel without arying oltage with ame number of power cell i propoed. Now-a-day, the tranit clamped conerter topology ha improed which ha the adantage of requiring ame number of power tranit a the number of leel generated and therefe the number of emiconduct i alo reduced [2]. Intead of clamping the connection point between the capacit and witche through diode, it i done uing bidirectional witche. hi gie a controllable path f the clamping deice [22]. A cacaded multileel inerter with two inerter with two inerter leg in erie i propoed in [2] in which me cell are required and thi tend to the increae in number of iolated ource a well a bulky tranfmer een though the number of witche f each cell required i lower. he propoed new configuration make ue of a fie-leel ranit Clamped H-Bridge (CHB) a a power cell which can produce a fie-leel output intead of three-leel a with the conentional H-bridge [22], [23]. he propoed inerter i compared with the SPWM technique applying to the multicarrier phae-hifted pule width modulation on an Induction mot. Simulation reult are preented to erify the aliditie of the propoed inerter. 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India.

2 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 II. PROPOSED CONERER OPOLOGY Fig. how the general configuration of the propoed inerter which comprie of N c erie-connected fie-leel CHB cell. Fig. i the propoed ingle-phae fie-leel PWM inerter cell. One witching element and four diode which are combined known a bidirectional witch added in the conentional full-bridge inerter and i connected to the centretap of power upply. Proper witching control of the auxiliary witch can generate half leel of upply oltage. he cell i able to produce fie output oltage leel (, ± (/2), ± ) baed on the witching combination gien in able I. he number of power cell required mainly depend on the operating oltage and manufacturing cot. In thi cae, a two cell configuration can produce a high quality output which can generate up to 7-oltage leel. In general, the relation f the maximum number of leel of the phae-to-neutral oltage an (t) and the line-to-line output oltage ab (t) baed on N c cell are repectiely repreented by n p = 4 N c + () n l = 8 N c + (2) Baed on the poible witch combination, S -S 5 in able I, the power cell output oltage an can be gien by an S5n S4n S n S2n S4n S3n S5 2 n (3) From the ummation of the power cell oltage, the phae-toneutral oltage, an and line oltage, ab are denoted Fig.. CHB: General configuration of the propoed three- phae cacaded multileel inerter and topology of fie leel tranit-clamped H-bridge f each cell. ABLE I FIE-LEEL RANSISOR CLAMPED H-BRIDGE OUPU OLAGE S S 2 S 3 S 4 S 5 an ½ -½ - repectiely a N c an n ab an an bn (4) (5) III. MODULAION SRAEGY PWM technique hae been deeloped f inerter circuit to reduce the magnitude of harmonic and to allow control of fundamental component of output oltage. In the propoed topology, Multicarrier Phae-hifted PWM (CPS-PWM) modulation i ued to generate the PWM ignal. Baic principle of the propoed witching trategy i to generate gate ignal by comparing the reference ignal with the two carrier wae. he amplitude and frequency of all triangular carrier wae are the ame a well a the phae hift between adjacent carrier wae. F ignal generation in each cell, one carrier ignal and two oltage reference are ued [24]. Both reference wae are imilar but diplaced by an offet equal to the carrier amplitude which i ½. he reference ignal ref and ref2 are deried from a full-wae oltage reference, ref defined by M in t (6) ref 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 2

3 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 (7) ref ref ref 2 ref (8) 2 he modulation index M of the propoed method i defined by M 2 ref (9) cr Depending on the number of cell, the phae hift in the carrier wae f each cell θ Cr, n can be obtained from c 2 n Cr, n, n =, 2.N c () N When the oltage reference i between < ref (/2), ref i compared with the triangular carrier and when S 5 i in ON tate, witche S and S 3 operate alternately to produce either ½. Wherea, when the reference i during the interal (/2) < ref, ref2 i compared and when S 5 i in ON tate, witche S and S 2 operate alternately to produce either ½. If the reference oltage i between (/2) < ref, ref i compared and when S 4 i ON, witche S and S 2 alternately produce either -½. If the reference oltage i between - < ref - (/2), ref2 i compared with the carrier and when S 4 i ON, witche S and S 3 alternately produce either -½. From thi, we can notice that the two witche S 4 and S 5 only operate in each reference half cycle. hi implie that Fig. 3. PWM ignal generation with multicarrier phae-hifted modulation f phae a. both witche S 4 and S 5 operate at the fundamental frequency and the remaining witche operate cloe to the carrier frequency. Hence the oltage will be witched at low frequency and o the witching loe are reduced. Fig. 2 how the modulation cheme ued f the propoed twocell configuration and fig. 3 how the block diagram f generating the PWM ignal. he fie-leel output oltage will be generated from each cell. he phae-to-neutral oltage an which i obtained baed on the oltage reference magnitude and the combination of cell oltage a and a2 are lited in able II. From able II, we can obere a total of nine leel (± 2, ± (3/2), ±, ± (/2), ) phae-to-neutral oltage when both cell are cacaded with CPS-PWM modulation. he phae oltage are diplaced by (2/3)ᴨ from each other and hence higher leel of line oltage will be produced f ab from (5). Fig. 2. Multicarrier phae-hifted PWM f two-cell configuration ABLE II PHASE-O-NEURAL OUPU OLAGE FOR WO-CELL CONFIGURAION < ref ½ ½ < ref -½ < ref a a2 an ½ ½ ½ ½ ½ ½ ½ ½ ½ 3/2 ½ 3/2 2 -½ -½ -½ -½ -½ -½ - - < ref -½ -½ -½ - 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 3

4 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () ½ -3/2 -½ - -3/ (d) Fig. 5. Harmonic pectrum of the propoed inerter Cell output oltage harmonic Cell 2 output oltage harmonic (c) Phae oltage harmonic (d) Line oltage harmonic I. RESULS 4. R Load Fig. 4 how the output oltage f the two-cell configuration from the imulation reult. he modulating ignal modulation index and frequency are.95 and 5 Hz repectiely. he carrier wae hae a maximum frequency of khz and there i 8 o phae-hift between each other. he upply gien to each cell i k oltage. Each cell Fig. 4. Simulated output oltage of propoed inerter Fig. 6. Harmonic pectrum of line oltage produce fie-leel oltage. In the phae oltage of the inerter, nine leel are produced and in the line oltage, 7 leel are produce which proide high output quality. he harmonic and frequency component of the output oltage obtained from the FF analyi uing MALAB are hown in Fig. 6. he harmonic pectrum of line oltage with repect to frequency meaured up to 998 th harmonic i hown in Fig. 7 with HD of 3.6% and the fundamental RMS oltage of (c) 4.2 Induction Mot he propoed tranit clamped multileel inerter i fed to a three-phae Induction mot. he oltage upplied to each cell i 22 and the carrier frequency i khz. Fig. 7 how the nine-leel phae-to-neutral output oltage of the model. he three phae current, tque and peed of the Induction mot at tranient and teady tate are hown in Fig. 8. he harmonic of the current i alo preented in Fig. 9 and noted a 5.35% with a fundamental RMS alue of A. 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 4

5 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 Imptant adantage of SPWM i the minimization of the current ripple and/ the total loe of the power conerter. he SPWM technique i analyzed baed on the effectie time. Effectie time i the time duration when the oltage difference i not zero which happen becaue an effectie power flow i made during thi duration. When the witching tate of each phae goe to from during one ampling interal at different time, an effectie oltage i introduced and the time duration f that i denoted a eff Fig. 7. Nine-leel phae-to-neutral output oltage Fig.. Actual gating time generation which i known a Effectie time. denote the ampling time. Fig. 8. Simulation waefm of Current, que and Speed of Induction mot with SPWM at Steady tate An imaginary time alue i introduced which i directly proptional to the phae oltage and the relation i a follow. a : a : a a : : b b b c : c : c c () a, b and c are the A-phae, B-phae and C-phae reference oltage repectiely. he imaginary time i called the Imaginary witching time. b he time duration between the larget and mallet of three imaginary time i called the effectie time and i gien by eff max min (2) Fig. 9. Harmonic of current. SPWM BASED PROPOSED OPOLOGY SPWM technique generate ine wae that proide a higher oltage to the mot with lower total harmonic dittion. Where min = min ( a, b, c), max = max ( a, b, c) o generate the actual getting time ( ga, gb, gc), a time hifting operation will be applied to the imaginary witching time which i done by adding the offet time a hown in Fig.. 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 5

6 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 ga gb gc a b c offet offet offet (3) o generate the ymmetrical witching time within two ampling interal, the actual witching time hould be replaced by the ubtraction alue with ampling time a follow. ga gb gc ga gb gc (4) F the full utilization of DC link oltage, the gating time hould be limited to a alue between and a follow., min offet offet max Fig. 2. Nine-leel phae-to-neutral output oltage with SPWM Fig.. Modulating waefm of SPWM In SPWM method, accding to the reference ect location, the applying time hould be combined with the zero oltage applying time which i ditributed ymmetrically at the tart and end of the ampling interal in a ymmetrical manner. Hence, to repoition the effectie time at the center of the ampling interal, the time-hifting alue offet i offet min 2 where eff (5) Fig. how the modulating waefm obtained from SPWM. Now the SPWM waefm i applied intead of ine wae in the multicarrier phae-hifted pule width modulation technique and the pule generated are applied to the tranit clamped multileel inerter fed Induction mot. Fig. 2 how the nine-leel phae-to-neutral output oltage. Fig. 3 how the waefm of Current, que and Speed at tranient and teady tate. Fig. 3. Simulation waefm of Current, que and Speed of Induction mot with SPWM at Steady tate Fig. 4. Harmonic of current 25 IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 6

7 IJAIC olume 2, Iue 5, September 25 Doi:.4/ijaict Publihed on 5 () 25 Fig. 5. Ripple current of SPWM and SPWM he harmonic of the current i repreented in Fig. 4 and noted a 4.32% with a fundamental RMS alue of A. he ripple current of SPWM and SPWM are hown in Fig. 5. he ripple current magnitude i le f SPWM compared to SPWM aboe.5. I. CONCLUSION In thi paper, a ranit clamped cacaded multileel inerter with multicarrier phae-hifted pule width modulation uing SPWM and SPWM i preented. he output oltage along with harmonic were preented with R load and the output of current, tque and peed of induction mot load were preented f both SPWM and SPWM. Here, SPWM ha me adantage uch a reduction of HD and low ripple current. Reference [] E. illanuea, P. Crea, J. Rodriguez, and M. Paca, Control of a ingle-phae cacaded H-bridge multileel inerter f grid-connected photooltaic ytem, IEEE ran. Ind. Electron., ol. 56, no., pp , No. 29. [2] N. A. Rahim and J. Selaraj, Multitring fie-leel inerter with noel PWM control cheme f P application, IEEE ran. Ind. Electron., ol. 57, no. 6, pp , Jun. 2. [3] F. Khoucha, S. M. Lagoun, K. Marouani, A. Kheloui, and M. El Hachemi Benbouzid, Hybrid cacaded H-bridge multileel-inerter induction mot-drie direct tque control f automotie application, IEEE ran. Ind. Electron., ol. 57, no. 3, pp , Mar. 2. [4] B. Ge, F. Z. Peng, A.. de Almeida, and H. Abu-Rub, An effectie control technique f medium-oltage high-power induction mot fed by cacaded neutral-point-clamped inerter, IEEE ran. Ind. Electron., ol. 57, no. 8, pp , Aug. 2. [5] H. Akagi and R. Kondo, A tranfmerle hybrid actie filter uing a three-leel Pule width Modulation (PWM) conerter f a medium oltage mot drie, IEEE ran. Power Electron., ol. 25, no. 6, pp , Jun. 2. [6] A. Nabae, I. akahahi, and H. Akagi, A new neutral-point-clamped PWM inerter, IEEE ran. Ind. Appl., ol. IA-7, no. 5, pp , Sep./Oct. 98 [7] M. F. Ecalante, J. C. annier, and A. Arzande, Flying capacit multileel inerter and DC mot drie application, IEEE ran. Ind. Electron., ol. 49, no. 4, pp , Aug. 22. [8] F. Z. Peng, J. W. McKeeer, and D. J. Adam, Cacade multileel inerter f utility application, in Proc. Int. Conf. Ind. Electron. Control Intrum., 997, ol. 2, pp [9] S. Kouro, M. Malinowki, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, Recent adance and indutrial application of multileel conerter, IEEE ran. Ind. Electron., ol. 57, no. 8, pp , Aug. 2. [] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Ptillo, M. A. M. Prat, and M. A. Perez, Multileel conerter: An enabling technology f high-power application, Proc. IEEE, ol. 97, no.,pp , No. 29. [] J. I. Leon, S. azquez, J. A. Sanchez, R. Ptillo, L. G. Franquelo, J. M. Carraco, and E. Dominguez, Conentional pace-ect modulation technique eru the ingle-phae modulat f multileel conerter, IEEE ran. Ind. Electron., ol. 57, no. 7, pp , Jul. 2. [2] D W Chung, J S Kim, Seung-Ki Sul Unified oltage modulation technique f real ime hree Phae power Conerion, IEEE ran. on Indutry Application, olume 34, No.2, pp , March/April 998. [3] J. Selaraj and N. A. Rahim, Multileel inerter f grid connected P ytem employing digital PI controller, IEEE ran. Ind. Electron, ol. 56, no., pp , Jan. 29. [4] G. Waltrich and I. Barbi, hree-phae cacaded multileel inerter uing power cell with two inerter leg in erie, IEEE ran. Ind. Electron.ol. 57, no. 8, pp , Aug. 2. [5] R. Naderi and A. Rahmati, Phae-hifted carrier PWM technique f general cacaded inerter, IEEE ran. Power Electron., ol. 23, no. 3, pp , May 28. [6] L. Yu, H. Hoon, and A. Q. Huang, Real-time algithm f minimizing HD in multileel inerter with unequal arying oltage tep under taircae modulation, IEEE ran. Ind. Electron., ol. 56, no. 6, pp , Jun. 29. [7] W. Jin and D. Ahmadi, A precie and practical harmonic elimination method f multileel inerter, IEEE ran. Ind. Appl., ol. 46, no. 2, pp , Mar./Apr. 2. [8] H. aghizadeh and M.. Hagh, Harmonic elimination of cacade multileel inerter with non equal DC ource uing particle warm optimization, IEEE ran. Ind. Electron., ol. 57, no., pp , No. 2. [9] S. Mukherjee and G. Poddar, A erie-connected three-leel inerter topology f medium-oltage quirrel-cage mot drie application, IEEE ran. Ind. Appl., ol. 46, no., pp , Jan./Feb. 2. [2] G. Waltrich and I. Barbi, hree-phae cacaded multileel inerter uing power cell with two inerter leg in erie, IEEE ran. Ind. Electron.ol. 57, no. 8, pp , Aug. 2. [2] J. Dixon and L. Man, High-leel multitep inerter optimization uing a minimum number of power tranit, IEEE ran. Power Electron.ol. 2, no. 2, pp , Mar. 26. [22]. Kouro, M. Malinowki, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, Recent adance and indutrial application of multileel conerter, IEEE ran. Ind. Electron., ol. 57, no. 8, pp , Aug. 2. [23] P. Sung-Jun, K. Feel-Soon, L. M. Hyung, and U. K. Cheul, A new ingle phae fie-leel PWM inerter employing a deadbeat control cheme, IEEE ran. Power Electron., ol. 8, no. 3, pp , May 23. [24] J. Selaraj and N. A. Rahim, Multileel inerter f grid-connected P ytem employing digital PI controller, IEEE ran. Ind. Electron, ol. 56, no., pp , Jan IJAIC ( Creponding Auth: M. B. eenaani, G. Pulla Reddy Engineering College, Kurnool, India. 7