9-level Hybrid Symmetric Cascaded Multilevel Converter for Induction Motor Drive

Transcription

1 9level Hybrid Symmetric ascaded Multilevel onverter for Induction Motor Drive Indrajit Sarkar and B. G. Fernandes Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai , India. Abstract A 9level hybrid symmetric cascaded multilevel converter fed induction motor (IM) drive is proposed in this paper. The converter used in the proposed drive system is capable of producing nine output voltage levels by cascading one 5level Transistor lamped Hbridge (THB) power cell and one 3level HB power cell per phase. The other feature of the converter is near equal power distribution among the power cells, which results in improved input power quality. The operation of proposed converter is explained using Hybrid multicarrier SPWM technique. In THB power cell, the D link mid point (MP) is connected to one of the output legs using a bidirectional switch. Therefore, the variation in D link MP voltage in THB power cell is also analysed and presented in this paper. Finally, the proposed converter system is validated by simulating a 500 hp IM speed controlled drive in MATLAB/Simulink environment. Keywords Multilevel converter, cascaded Hbridge (HB), hybrid multilevel inverters, transistorclamped Hbridge inverter (THB), induction motor. I. INTRODUTION In high power applications, the use of multilevel converters is common due to their superior input and output power quality with low EMI and lower switching losses [1][3]. Among the popular multilevel converter topologies [2][8], cascaded multilevel converters are of special interest as it features simple control and high modularity [9], [10]. Moreover, in case of a fault in any one of the power cells, the faulty cell can be bypassed and normal operation can be restored easily [9], [11]. However, the main limitation of cascaded multilevel inverter (MLI) is the requirement of a large number of isolated D power supplies to feed each power cell [4]. These power supplies are usually obtained using a complex multiwinding transformer at the converter input [9], [10]. Another limitation of cascadedmli is the higher component count [4]. In order to use low power semiconductor devices, the number of power cells to be cascaded increases with an increase in output voltage level. Hence, the component count and transformer complexity increases with an increase in output voltage level, which tends to reduce the overall system reliability. In order to reduce the component count, the use of asymmetric cascaded inverters with unequal D link voltages is reported in [2] & [5]. In asymmetric structure, the number of output voltage levels can be increase further by selecting suitable D link voltage ratio [4][8]. 15 level asymmetric converter by cascading one 5level diode clamped power cell and one 3level HB power cell with dc link voltage ratio 1:6 is proposed in [12]. Asymmetric HBMLI using 5level THB power cell is proposed in [14]. Hybrid asymmetric cascaded HBMLI for Direct Torque ontrolled (DT) IM drive for electric or hybrid EVs is proposed in [15]. However, use of asymmetric structure losses modularity [2], [13] and results in unequal power distribution among the power cells, which tends to deteriorate the input power quality [2]. Solution to improve input current quality with asymmetrically loaded rectifier is suggested in [16] with more complex design of input transformer. Moreover, the solution is not suitable for all the loading conditions. Therefore, the use of asymmetric or hybrid cascaded inverters are popular for electric vehicle applications, and have limited industrial application [13]. In [17], a 9level SHBMLI is proposed by cascading two 5level THB power cells per phase. However, for the proposed topology, MP voltage balancing technique needs to be employed for all the THB power cells leading to complex control algorithm. The number of output voltage levels in symmetric or asymmetric HBMLI is increased further by using level doubling network (LDN) proposed in [18]. The converters proposed in [17], [18] features symmetry, uniform power distribution and significant number of redundant switching states. In this paper a 9level hybrid symmetric cascaded inverter fed IM drive is proposed using one 5level and one 3level power cell per phase. The proposed converter features: a) Increase in output voltage levels to nearly double to that of SHBMLI with same number of power cells, b) Near equal power distribution among the power cells (helps to improve input power quality [2], [10], [17], [18]), c) Reduced number of redundant switching states. Moreover, the voltage balancing needs to be employed for three THB power cells only. II. PROPOSED ONVERTER TOPOLOGY The power circuit diagram of proposed 9level Hybrid SHBMLI is shown in Fig. 1, with each phase consisting of a 5level THB power cell and a 3level HB power cell, connected in cascade. 3level power cell is a conventional 3 level HB power cell with 3 output voltage levels (±2V dc and 0). 5level THB power cell is a modified HB power cell with one of the output terminals of HB is connected to the D link MP using a bidirectional switch [14], [17]. This is to enable 5 output voltage levels i.e. ±2V dc, ±V dc, and 0 with 2V dc D link voltage.

2 va1 vb1 vc1 va2 vb2 vc2 S11 1 2Vdc S15 2 S14 S21 1 2Vdc S24 2 S13 S12 S23 S22 ia VA1 VA2 THB B1 HB B2 N VB1 VB2 THB 1 HB 2 V1 V2 TABLE I. SWITHING STATES AND VOLTAGE LEVELS S 11 S 12 S 13 S 14 S 15 V THB S 21 S 22 S 23 S 24 V HB V an E E 4E E E 3E E 2E E E E E E E E E E 2E E E 3E E E 4E ia ib ic VaN VbN VcN Fig. 1. Topology of the proposed 9level hybrid symmetric cascaded multilevel induction motor drive. In mcell cascaded MLIs, the inverter leg voltages can be expressed as [2], [13]: V jn = IM m v ji, j (a, b, c). (1) where, V jn is the leg voltage and v ji is the output voltage of i th power cell in j phase with m power cells per phase. SHBMLI with two, 3level HB power cells per phase, the maximum number of voltage levels obtained in inverter leg and line voltage waveforms are 5 and 9 respectively [9], [13]. In case of proposed topology, a 5level THB power cell is in cascade with a 3level HB power cell. Therefore total 9 voltage levels (±4V dc, ±3V dc, ±2V dc, ±V dc, and 0) are obtained in inverter leg voltage waveform and 17 levels are obtained in line voltage waveforms with 3 rd harmonic injection technique (15level line line voltage is obtained without third harmonic injection). Various switching states and the corresponding voltage levels for the proposed 9level converter are presented in Table I. Unlike [17] and [18] only few redundant switching states are possible here. Switching state redundancies are generally used to balance the D link MP voltage using SVM technique. However, for the proposed converter, the switching redundancies are not applicable as multicarrier SPWM technique is used. For the proposed converter topology, the D link voltages are equal in all the power cells. Therefore, the voltage ratings are identical for all HB switches except for the bidirectional switch. The voltage rating of the devices used in bidirectional switches is half of that of HB switches as the maximum voltage appearing across it is V dc i.e. half of the D link voltage. Equal D link voltage and cascade connection of power cells also enables the feature of near equal power distribution among the power cell. This helps in eliminating lower order harmonics from the source current waveform using a phase shifting multiwinding transformer at the converter input [13], [19]. III. OPERATING PRINIPLE Based on the switching states, the inverter leg voltage V an can be expressed as V an = 2V dc (S 11 S 13 ) 2V dc (S 21 S 23 ) V dc S 15. (2) Where switches S 11 and S 15 can not be turned on simultaneously. The first two terms in equation 2 are similar to that obtained in SHB inverter, where as the third term is the result of adding one extra bidirectional switch in THB power cell. Therefore, the third term V dc S 15 in equation 2 improves the resolution of output voltage profile from 2V dc to V dc i.e. number of output voltage levels from 5 to 9 with two power cells per phase. A. PWM Technique In the proposed topology, the devices in all the power cells do not have similar switching patterns. Hence, Hybrid PWM technique based on level shifted multicarrier sine PWM (LSSPWM) technique [2], [13] is used to generate PWM switching pulses for the inverter switches. A nlevel SHBMLI using LSSPWM technique requires total (n 1) triangular carriers of equal magnitude and frequency. These carriers are shifted vertically to make contiguous band [13], [19], [20]. Therefore, for a 9 level converter 8 triangular carriers are used and these are as shown in Fig. 2. Eight triangular carriers of magnitude 0.25 each are termed as, r1 varying from 1.0 to 0.75, r2 from 0.75 to 0.5, r3 from 0.5 to 0.25, r4 from 0.25 to 0, r5 from 0 to 0.25, r6 from 0.25 to 0.5, r7 from 0.5 to 0.75, and from 0.75 to 1.0 is r8 respectively. In THB power cell, the four triangular carriers r1, r2, r5, & r6 are used to generate PWM switching signals for switch S 11 and four carriers r3, r4, r7, & r8 for switch S 14 (Fig. 2). All triangular carriers are used for bidirectional switch S 15 which results in uniform switching of S 15 over a complete power cycle. Switches S 12 and S 13 are operated at fundamental switching frequency. In HB power cell, two triangular carriers r2 & r3 are used to generate PWM switching signals for switch S 21 and carriers r6 & r7 for switch S 23. The gate signals of lower switches S 22 and S 24 are complementary to that of upper switches S 21 and S 23 respectively. Three reference voltages for phases a,b,c are defined as: v an = V m sin(ω o t)

3 (c) Fig. 2. Switching pulses for THB Power ell, HB Power ell. v bn = V m sin(ω o t 2π 3 ) v cn = V m sin(ω o t 2π 3 ) where, ω o = 2πf o, f o is output frequency. The modulation index m i is defined as: m i = V m V cr (n 1) where V cr is amplitude of triangular carriers. For 9level output, when the reference signal vjn is from 0 to 0.25, the expected leg voltage output is V dc. Therefore S 15 and S 12 of THB power cell are switched ON and HB power cell is bypassed. When reference is from 0.25 to 0.5, i.e. for 2V dc output, either switch pair S 11, S 12 of THB power cell is switched ON or switch pair S 21, S 22 of HB power cell is switched ON. For vjn from 0.5 to 0.75 i.e. when expected output is 3V dc, switches S 15 & S 12 of THB power cell and S 21 & S 22 of HB power cell are turned ON. When vjn is from 0.75 to 1.0 i.e. for 4V dc output, the outputs of both the power cells are 2V dc, therefore S 11 & S 12, and S 21 & S 22 are switched ON. For zero output voltage both the cells are bypassed. The principle of HybridPWM technique employed for the proposed converter operating with frequency modulation index m f = 27, m i = 1.0, f o = 50 Hz, and carrier frequency f cr = f o m f = 1350 Hz is shown in Fig. 2. The PWM output voltage waveforms of THB power cell, HB power cells and leg voltage waveform are shown in Fig. 3. The dominant harmonics can be observed at frequency 1350 Hz in leg voltage waveform in Fig. 3(d) [13]. It is to be noted from Fig. 2 that the number of switchings in HB switches are much less than the carrier frequency, (3) (d) Fig. 3. Output voltage waveforms: V T HB, V HB, (c) V an and (d) Leg voltage spectrum (f cr = 1350 Hz). while switch S 15 is switched at carrier frequency. Therefore, for the proposed converter with hybrid PWM technique, the average inverter switching frequency becomes much less than the carrier frequency. Switch S 15 is switched from 0 to V dc which is half of the D link voltage. Therefore, switching loss in S 15 is also reduced. IV. MP VOLTAGE VARIATION IN THB POWER ELL In THB power cell the switch S 15 operates at carrier frequency and allows the bidirectional flow of load current to the D link MP. Therefore, the D link MP carries a PWM current with current envelop same as that of load current waveform. The average value of MP current during positive and negative halves of the power cycles is given by i avr = n p t oni i i n p T s and i avr = n n j=1 t onj i j n n T s. (4) where, i, i are the instantaneous currents in positive and negative half cycles, t on is the ON duration of switching period T s. n p, n p are the total number of switching in positive and negative half cycles respectively. The variation in D link capacitor voltages can be obtained

4 as v = idt = i avr T. (5) Therefore, v for positive half and v for negative half can be obtained as n p n n t oni i t v i onj i j = and v j=1 = For one complete power cycle, the MP voltage variation can be expressed as ( v = ( v v ) = 1 np ) n n t oni i i t onj i j. (6) j=1 At steady state i avr = i avr, therefore the average value of D link MP current is zero over a power cycle ensuring natural balancing of MP voltage with average value close to V dc. However, during transients or due to parameter mismatch, i avr and i avr may not be equal, resulting in shifting of MP voltage from V dc. Moreover, the D link MP current profile also depends on load current, load power factor, and device switching frequency. Therefore, some technique must be employed to ensure balancing of capacitor voltages during transient conditions [17]. The torque producing current I qsf is generated by speed controller depending on reference speed ωr and measured rotor speed ω r. Similarly the flux producing current component I dsf is obtained from flux reference and actual flux obtained from dynamic flux model. The PI controllers generate dfaxis and qfaxis reference voltage signals based on daxis and qaxis current errors respectively. TABLE II. SIMULATION PARAMETERS Parameters & Symbols Values Utility Supply 2.3 kv, 50 Hz Source Impedance r s, l s Ω (0.05 pu), 3.58 mh (0.1 pu) Isolation Transformer 85 kva, 2300/660V, Y/Y (3), Y/ (3) D Link Voltage, 2V dc 930 V D link apacitors 1, µf Switching Frequency, f cr 1950 Hz (m f = 39) Output frequency, f o 50 Hz Induction Motor 500 hp, 2.3 kv, 50 Hz, 4P, 1485 rpm VI. SIMULATION RESULTS Simulation of proposed 9level converter feeding 500 hp IM speed controlled drive is carried out in MATLAB/Simulink environment with simulation parameters listed in Table II. It Field Frame ωr ωr λ r λ r i qf PI Speed ontroller i qf i df PI Flux ontroller i df PI PI v qf v df dq abc v a v b v c θ f IM i df i qf dq abc i as i bs i cs ωr θf ias a b c iqs (d q)s iqf θf ibs ωf ωf ʃ ics (d q)s ids (d q)f idf 1/(1Ʈrd/dt) imr Ʈr ωr Fig. 4. ontrol block diagram Dynamic flux model of indirect rotor field oriented IM speed controlled drive. V. INDUTION MOTOR SPEED ONTROLLED DRIVE The IM speed control drive based on indirect rotor flux orientated control (FO) scheme is implemented using the proposed 9level converter as explained below. The control block diagram of speed control drive and block diagram to calculate rotor field position (θ f ) under indirect FO scheme [13], [21][22] is shown in Fig. 4 and respectively. Fig. 5. Reference signals m i, i d, i q and rotor flux Speed and T em. is to be observed from Fig. 5 that at time t = 1.5 sec, a load torque of magnitude 2.4 knm is applied and a part of it is withdrawn at time t = 3.5 sec. With instantaneous rise and fall in electromagnetic torque, it can been seen in Fig. 5 that the shaft speed is constant at 1300 rpm. D link current, capacitor voltages V 1 & V 2 and MP current are shown in Fig. 6. As expected, MP current envelop is same as that of load current waveform and capacitor voltages are balanced with an average voltage close to V dc. ell voltages of phase A and commonmode voltage are shown in Fig. 7 with 9 levels in leg voltage

5 Fig. 8. Output line voltage and line current waveforms. Fig. 6. cell. D link current, capacitor voltages and MP current in THB power Fig. 7. ell voltage waveforms: V T HB, V HB, V leg, and V com. waveform. 15level output line voltage (without 3 rd harmonic injection) and line current waveforms are presented in Fig. 8. The average value of D link power in THB and HB power cells are around 50 kw and 60 kw as shown in Fig. 9. Because of the use of multiwinding phase shifting stardelta transformer and near equal power distribution feature of proposed converter, the lower order harmonics are suppressed in input current waveforms as can be observed in Fig. 9. The FFT of input current is shown in Fig. 9(c) with magnitudes of 5 th, 7 th, 11 th and 13 th harmonic components are 1.5%, 1.1%, 2.7% and 1.5% respectively with l s = 0.1 pu. VII. ONLUSION High performance IM drive based on indirect FO using proposed 9level hybrid symmetric cascaded MLI is presented in this work. Since the number of output voltage levels is increased from 5 to 9 which is nearly double compared to SHBMLI with same number of power cells, sinusoidal line currents are obtained at the converter output without using any output filter. Moreover, equal D link voltage and cascade connection of power cells results in near equal power distribution among the power cells, which helped in improving the input current quality by using a phase shifting transformer at the converter input. Simulation results thus obtained for the proposed drive system is presented and discussed. The average Mag (% of Fundamental) 10 5 THD= 3.91% Frequency (Hz) (c) Fig. 9. Average D link powers in THB and HB power cell Input line current waveforms (c) Input line current FFT. D link power in THB and HB power cell is presented along with input current FFT to validate the claims. REFERENES [1] J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel inverters: Survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp , Aug [2] J. Rodriguez, B. Wu, S. Bernet, J. Pontt, and S. Kouro, Multilevel voltage source converter topologies for industrial medium voltage drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp , Dec [3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp , Aug [4] K. orzine, Operation and Design of Multilevel Inverters, Developed for the Office of Naval Research, Dec. 2003, Rev. Jun [5] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, Hybrid multilevel power conversion system: A competitive solution for highpower appli

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