Harmonic Analysis & Filter Design for a Novel Multilevel Inverter

Transcription

1 Harmonic Analysis & Filter Design for a Novel Multilevel Inverter Rashmy Deepak 1, Sandeep M P 2 RNS Institute of Technology, VTU, Bangalore, India rashmydeepak@gmail.com 1, sandeepmp44@gmail.com 2 Abstract multilevel inverters have become an incredibly main choice in the field of medium voltage & high power control. The main advantages of multilevel inverters are reduces the total harmonic distortions & voltage stress across each switch and also produce good quality of power. The various topologies of MLI are diode clamped, capacitor clamped and cascaded H-bridge inverter. Among those inverters cascade multilevel is quite impressive and has more benefits than other multilevel inverter. Even though the cascade multilevel inverter holds good features it requires more number of components (Power semiconductor switch, DC sources & gate drive circuit). Use of more number of switches in the multilevel inverter has limitation for wide range application, because of increase in size and cost of the system and also affects the system reliability. In this paper a new class of multilevel inverter is proposed to reduce the number of switches and other components. In this topology, each battery cell can be controlled to be connected into the circuit or to be bypassed by a half- bridge converter. All half bridges are cascaded to output a staircase shape DC voltage. Then, an H- bridge converter is used to change the direction of the DC bus voltages to obtain AC voltages. When compare to conventional multilevel inverter, the proposed multilevel inverter can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. The novel multilevel inverter is made compared with cascade multilevel inverter to investigate the performance, here we are considered induction motor as a load connected to 11-level inverter which is simulated using MATLAB/simulink software. In addition, different SPWM technique (PD, POD &APOD) are implemented. Finally, the filter is added at the load side of novel multilevel inverter to reduce the THD. Index Terms Unequal voltage sources (UVS), Cascaded Multilevel inverter (CML), Novel MLI, Total Harmonic Distortion (THD), Induction Motor (IM), Pulse width modulation (PWM), Insulated Gate Bipolar Transistor (IGBT), MATLAB/Simulink. I. INTRODUCTION At present world, the multilevel inverters has found wide acceptance in various applications for its capability of high -voltage and high-efficiency operation. Compared with the traditional two level voltage converters, the primary advantage of multilevel inverters is better output voltage step with lower THD, which results in high power quality, lower switching frequency and lower switching losses [2]. The - multilevel inverters are basically three types 1) Diode Clamped MLI, 2) Capacitor clamped MLI and 3) Cascaded H-bridge MLI. The main attractive features of MLI are as outlined are as 1) Output voltages have extremely low distortion and low dv/dt. 2) They draw current with very low distortion. 3) They operate with a lower switching frequency [1]. Among various topologies the popular topology of multilevel inverters is the cascaded H-bridge multilevel inverter which is based on the series connection of single phase H-bridge inverters with separate DC sources. In this, the output voltage waveform is nearly sinusoidal even without filtering. If the number of DC sources in single phase inverters is n, then the number of output levels will be (2n+1). Therefore an increase in n will increase the number of levels in the output. But for each added inverter four switching devices will be added [6]. Compared to traditional Multi Level Inverter the cascade multilevel inverter requires fewer components i.e., clamping diodes and capacitor are absent. The conventional CMI performance is quite impressive, moreover it is possible to adopt different switching approaches very easily (compare to other multilevel structures). All these reasons made this inverter topology to found in the market for medium and high power applications. But on the other side, there are some aspects that need further developments. They are summarized as below [3]. The primary one is that to improve the efficiency. Even though many advance technology are reported to minimize the loss in switching with the best modulation, but conduction loss are more serious because of series connection of switches. Further the new technologies are expected to reduce the conduction loss. To reach higher voltage levels with less number of switching components is another prominent issue. 2259

2 So new kind of architectures and designs are essential. The CMI requires separate identical DC source which is the greatest limitation. Blocking voltage are increased which leads to modify the gate drives and sensors. II. NOVEL Modularized circuit layout. Good output waveforms. Less Complexity in switching. Good THD of the output voltage. IV. ELEVEN LEVEL NOVEL The novel multilevel inverter actually divides the circuit in to two sections. First section is called level generator section which is used to generate required positive voltage levels. Only positive voltage level is generated by the level generation part. The switches used in level generation must have high frequency of switching capability. The second section is responsible for polarity generation which decides the output voltage polarity. This part requires low frequency switches [7]. So there is no need of all switches to operate at high frequency. Fig 1 shows general block diagram of novel multilevel inverter topology. V1 V2 S1 S3 S2 S4 SA SC Load SD SD DIRECT CURRENT SOURCE LEVEL GENERATING CIRCUIT POLARITY GENERATING CIRCUIT OUTPUT VOLTAGE V3 S5 S6 Fig 1: General block diagram of novel multilevel inverter. The circuit consists of Battery, High frequency switches and Low frequency switches. All half bridges are connected in series to get shape of AC voltage. The direction of DC voltage is change by using H bridge inverter. For getting positive voltage switches S A and S D are turned on and for getting negative wave switches S B & S C is to be turned ON thus we can get multilevel AC voltage at the output. The circuit diagram of novel multilevel inverter is shown in fig 2. III. IMPORTANT FEATURES OF NOVEL CONTROL STRATEGY Significant improvement in reliability. Less in price tag as less dc sources are used. Finite Modularity, easy in circuit layout and packaging. Finally, it confers feasibility to CMC for manufacturing and flexibility in sense of power expansion. Cost effective, compact in size & Weight of the system is reduced. Overall system is simple. Improvement in reliability. LOAD HIGH FREQUENCY LOW FREQUENCY SWITCHES LEVEL SWITCHES POLARITY GENERATION GENERATION Fig 2: Single phase 11-level novel multilevel inverter structure. Single phase 11-level novel multilevel inverter structure is shown in fig 2. Operating principle of proposed 11-level inverter: Operation of proposed 11-level inverter is explained by assuming V 1=1V, V 2=2V and V 3=2V. To obtain voltage level +1 V dc the switch S 4, S 1, S 6, turned off. To get voltage level +2 V dc the switch S 2, S 6, S 3, S A, S D are conducting & remaining switches are turned off. To obtain voltage level +3 V dc the switch S 3, S 1, S 6, turned off. To obtain voltage level +4 V dc the switch S 2, S 3, S 5, turned off To obtain voltage level +5 V dc the switch S 3, S 1, S 5, turned off. Remaining voltage levels are shown in table

3 For 3-phase multilevel inverter system the output of three separate single phase inverters are connected in either star/delta fashion. In this requires one sine wave and five carrier waves for each phase to operate high frequency switches. To produce three phase 11-level voltage, each cell produce phase voltage with delaying 0 0, and electrical for phase A, B and C respectively. Table 1: Switching model of 11- level MLI Levels S1 S2 S3 S4 S5 S6 S A SB SC S D VOUT VDC VDC Fig 3: Phase disposition modulation VDC VDC VDC VDC VDC VDC VDC VDC V. LEVEL SHIFTING PWM TECHNIQUE Fig 4: Phase opposition & disposition modulation. Sinusoidal pulse width modulation (SPWM) is an important technique which employs to reduce total harmonic distortion. In this modulation there are two main parameters which are defined as follows. 1) M f = F c/f m known as frequency modulation index. 2) M a = A m/a c know as amplitude modulation index. Where F m = Carrier frequency. F c = Reference frequency. A m =Amplitude of reference signals. A c = Amplitude of carrier signals. In this method every pulse width varied comparative to amplitude of sine-wave. Comparing sine wave with triangular carrier waves pulses are produced. The reference signal frequency is a fundamental frequency which is inverter output frequency [2]. The crest amplitude will controls modulation index in turn controls RMS value of voltage. Fig 5: Alternate Phase Opposition & Disposition. VI. SIMULATION STUDY The simulation of three phase novel multilevel inverters fed to three phases induction motor has been carried out using MATLAB/Simulink software shown in fig 6 & motor parameters is shown in table 2. The IGBT switches are used as a switching device and in this study all the switches are considered to be ideal. The frequency of output voltages is 50 Hz. 2261

4 Discrete, Ts = 5e-005 s powergui PHASE A PHASE B PHASE C Subsystem Conn2 Conn1 Conn2 Conn1 Conn2 Conn1 Fig 7: Phase Voltage waveforms of proposed 3-phase 11-level inverter. + - v + - v + - v Display Display Display Display Constant Vabc A Iabc B a b C c Three-Phase V-I Measurement Tm A m B C Asynchronous Machine SI Units -K- <Rotor speed (wm)> <Electromagnetic Gaintorque Te (N*m)> <Rotor current ir_a (A)> <Stator current is_a (A)> Fig 6: Simulation diagram of proposed 11-level inverter. Table 2: Motor rating and parameters used in MATLAB/simulink Rated Power 5.4hp(4Kw) Rated stator voltage (LL) 400rms Number of poles 4 Operation Frequency 50Hz Fig 8: line voltage & current of 3-phase novel 11-level inverter. Stator resistance (Rs) Ω Rotor Resistance (R r 1 ) 1.395Ω Stator inductance (Ll s) H Rotor inductance ( L1 r 1 ) H Rated speed 1430rpm The simulated result of phase voltage, line voltage & line current are shown in fig 7 & fig 8. The FFT spectrum of phase voltage (V a), line voltage (V an) & line current (I an) for 11-level inverter form are shown in the fig 9 & also motor characteristics (speed, torque, stator current and rotor current) are shown in fig

5 Table 3: Comparison of THD values CASCADE 11-Level NOVEL 11-Level V a V b V c V ab V bc V ca Speed(rpm) Fig 9: FFT analysis of proposed 11-level multilevel inverter (V a, V an and I an). Table 4: Comparison of components requirement CASCADE 11-Level NOVEL 11-level Number of dc source 15 9 Number of switch Number of carrier signal Table 5: Comparison of SPWM techniques 11-level PD. POD. APOD. V ab V bc Fig 10: Speed, torque, stator current and rotor current of induction motor fed by Three-phase 11- level inverter. Simulated output of novel multilevel inverter circuit consist of both current & voltage waveform where Total Harmonic distortions (THD) for both the output voltages and currents are done using powergui FFT analysis. THD comparison of both cascade and novel multilevel inverter is shown in Table 3. The comparison of components requirement for both cascade and novel multilevel inverter is shown in table 4. V ca LC filter is designed to reduce the THD of the output voltage less than 5% the switching frequency of inverter is f s=5000hz. The resonant frequency is 2000Hz is selected. The filter value are L=3.246mH & C= 1.978*10-5 F are selected. The output voltage with LC filter is shown in fig 11, fig 12 & its FFT analysis is shown in fig 13. Various method of the SPWM (PD, POD &APOD) scheme is simulated & the results have been tabulated in table

6 Fig 11: Phase Voltage of proposed 3-phase 11-level inverter with L-C filter. Fig13: FFT analysis of proposed 11-level multilevel inverter with L-C filter (V a, V an ) With LC filter all the higher order harmonics are eliminated and therefore the THD of 11-level inverter output voltage reduce to 4.54% in phase voltage and 2.98% in line voltage. VII. CONCLUSIONS Fig 12: Line Voltage of 3-phase proposed 11-level multilevel inverter with L-C filter. In this paper presents multilevel inverter which has good feature compared to conventional inverter. The novel multilevel inverter requires the least components (switches, DC sources & gate drives) such that the system is more reliable, compact and cost effective. In this paper the operating principle of 11-level inverter is explained. In addition, different SPWM technique (PD, POD&APOD) are implemented among those APOD technique better which produce less THD. The proposed novel multilevel inverter is connected to induction motor drive is simulated using MATLAB/simulink software. The simulated result i.e., output waveform and motor characteristics are shown. From the simulated result comparison are made between conventional cascade and the novel multilevel inverter, it is found that both inverter produces same output with same THD respectively. But novel multilevel inverter consist of the least number of components compared to cascade inverter, hence the novel multilevel inverter is superior to conventional multilevel inverter. Finally, LC filter is added at the load side of novel multilevel inverter to reduce THD. REFERENCES [1] Fang Peng zheng et al Multilevel inverter a survey of topologies, controls & application. IEEE, Transaction on Industrial Electronics, Aug-2002, and volume no: 49. [2] Dnyaneshwar D. Khairnar and V. M. Deshmukh Performance Analysis of Diode Clamped 3 Level MOSFET Based Inverter International Electrical Engineering Journal (IEEJ) Vol. 5 (2014) No.7, pp

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