Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources

Transcription

1 Crossover Switches Cell (CSC): A New Multilevel Inverter Topology with Maximum Voltage Levels and Minimum DC Sources Hani Vahedi, Kamal Al-Haddad, Youssef Ounejjar, Khaled Addoweesh GREPCI, Ecole de Technologie Superieure, University du Quebec, Montreal, QC, Canada

2 Outline Introduction Multilevel Inverters Concept and Applications Seven-Level PUC Nine-Level CSC Linear Control Strategy Simulation Results Conclusion 2

3 Introduction The major task of Power Electronics is to process and control the power flow to the consumers and load. [Ned Mohan] AC-AC Converters (Cycloconverter) AC-DC Converters (Rectifier) DC-DC Converters DC-AC Converters (Inverter) 3

4 Introduction Multilevel Inverters Concept Conventional two-level inverter: 4

5 Introduction Multilevel Inverters Concept Weaknesses of Conventional two-level inverter: High distortion at the output (high THD) Requiring large AC filters Low power quality Limited high-power applications Limited voltage switches ratings High power losses EMI 5

6 Multilevel Inverters Concept V dc V dc V dc V a V dc V a V dc V a V dc V dc V dc (a) (b) (c) One leg of a) 2-level, b) 3-level and c) n-levels inverter 6

7 Multilevel Inverters Concept Three Level Inverter Switching States how to obtain 3 level: 7

8 Multilevel Inverters Advantages and Applications Introduction Advantages: Applications: Lower distortion in the output voltage due to multiple levels of output waveform Lower dv/dt that leads to endure the reduced voltage for switches. mining applications as regenerative conveyor medical purposes like MRI gradient coil driver hydro pump storage Lower common mode voltage which is helpful in motor drives Lower switching frequency results in lower switching losses STATCOM and Active Filters, FACTS, ship propulsion train traction Aerospace renewable energy (wind and photovoltaic) conversion 8

9 Multilevel Inverters Ratings Reported Manufactured Ratings of Multilevel Inverters Parameter NPC CHB FC Max Power 3.7MW, 10MW, 27MW, 27MVA, 31.5MVA, 33.6MW, 40MVA, 44MW 5.6MW, 6MVA, 6.25MVA, 10MVA, 11.1 MVA, 15MW, 120MW 2.24MW Output Voltage (kv) 2.3, 3.3, 4, 4.16, , 3, 3.3, 4, 4.16, 6, 6.6, 10, , 3.3, 4.16 Cooling System air/water, air, water air/water, air air Modulation Method PWM, SHE, SVM PS-PWM PS-PWM Voltage Levels (#) 3 7, 9, 11, 13, 15,

10 Seven-Level PUC The 7-level Packed U-Cell converter a S1 S2 S3 V ab S 1 S V dc V dc + _ V dc -C dc C dc C dc S 2 S 5 V ab C dc -V dc V dc C dc + S 3 S 6 Using one DC supply and fixing the capacitor voltage by controller to 1/3 Vdc achieve seven levels of voltage at the output b 10

11 Nine-Level CSC Nine-Level Crossover Switches Cell Inverter a S 1 S 4 S 2 S 8 V dc + _ S7 S 5 + V ab S7 and S8 are two bidirectional switches enabling the proposed topology to produce two extra higher levels of the output which is summation of DC supply and capacitor voltages. If the V dc is 3E and V C is E, then the output is : 0, ±E, ±2E, ±3E, ±4E C dc + S 3 S 6 b FIO50-12BD 11

12 Nine-Level CSC Switching States of a Nine-Level Crossover Switches Cell Inverter S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 Output V ab V dc +C dc +4E V dc +3E V dc +3E V dc -C dc +2E C dc +E C dc +E C dc -E C dc -E V dc +C dc -2E V dc -3E V dc -3E V dc- C dc -4E 12

13 Nine-Level CSC Topology Diode Switch DC Source Capacitor CHB with equal DC sources CHB with unequal trinary DC sources NPC CSC number of components in multilevel inverters 13

14 Controller Strategy Controller strategy to fix the capacitor voltage: V PI i ref + - PI Modulation Reference Wave V 2 Sin i load First the capacitor voltage (V2) is compared to the reference voltage which is one third of the DC supply (V1). This error signal goes to a PI to compensate the voltage. The output of the PI controller is compared to the load current which is circulating in the inverter and is responsible to charge or decharge the capacitor. The error is sent to the multilevel PWM scheme via second PI controller to reduce the current error. The concept of this controller is to adjust the current passed through the capacitor to fix the voltage at a desired level. 14

15 Multilevel PWM Standard Multilevel PWM v Modulation Reference and Carriers Waveforms Cr 1 Cr 2 Cr 3 0 Cr 4 Cr 5 Cr 6 Logic Comparator Output Voltage Level Switching Table Pulses Cr 7 Cr 8 Ref -v Modulation Reference Wave Cr 1 Cr 2 Cr 3 Cr 4 Cr 5 Cr 6 Cr 7 Cr 8 The reference wave calculated from controller will be compared with nine-level PWM to generate the appropriate pulses for associated switches 15

16 Voltage (V) Voltage (V) Current (A) Simulation Results Load voltage and current waveforms Time (s) Time (s) The switching frequency is 1200 Hz and the RL load includes a 30Ω resistor and a 20mH inductance. The output voltage frequency is 60Hz and the DC voltage magnitude is 450V. The capacity of the DC capacitor is 4mF and it has been precharged Time (s) Capacitor voltage fixed at one third of the DC supply 16

17 Voltage (V) Voltage (V) Current (A) Voltage (V) Current (A) Simulation Results load change from 30Ω to 12Ω With inductance 20mH the controller shows good performance Time (s) Time (s) Time (s) Load voltage Time (s) Time (s) Load current Capacitor voltage fixed at 150V (one third of the DC supply) 17

18 Conclusion A modified topology of PUC inverter called CSC is proposed which produces the maximum voltage levels whereas using minimum DC sources and switches. In order to reduce the number of DC supplies, the DC capacitor has been used in this topology with a voltage controller scheme. Due to stable dynamic performance of the CSC and accurate operation of designed controller and switching pattern, the capacitor voltage has kept constant. As a result, the maximum voltage levels have been produced at the output. The simulation results prove the validity of the proposed topology in producing high voltage with nine levels containing low value of harmonics 18

19 References J. Rodríguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, "Multilevel voltage-source-converter topologies for industrial medium-voltage drives," Industrial Electronics, IEEE Transactions on, vol. 54, pp , J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," Industrial Electronics, IEEE Transactions on, vol. 49, pp , 2002 Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM inverter," Industry Applications, IEEE Transactions on, pp , 1981 L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, "The age of multilevel converters arrives," Industrial Electronics Magazine, IEEE, vol. 2, pp , 2008 S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, "Recent advances and industrial applications of multilevel converters," Industrial Electronics, IEEE Transactions on, vol. 57, pp , M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, "A survey on cascaded multilevel inverters," Industrial Electronics, IEEE Transactions on, vol. 57, pp , 2010 F. Z. Peng, "A generalized multilevel inverter topology with self voltage balancing," Industry Applications, IEEE Transactions on, vol. 37, pp , 2001 Y. Ounejjar, K. Al-Haddad, and L. A. Gre goire, "Packed U cells multilevel converter topology: theoretical study and experimental validation," Industrial Electronics, IEEE Transactions on, vol. 58, pp , 2011 K. Al-Haddad, Y. Ounejjar, and L. A. Gregoire, "Multilevel Electric Power Converter," US Patent A1,

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