Implementing a Three Phase Nine-Level Cascaded Multilevel Inverter with low Harmonics Values

Transcription

1 Proceedings of the th International Middle East Power Systems Conference (MEPCON 0), Cairo Uniersity, Egypt, December 9-, 00, Paper ID 9. Implementing a Three Phase Nine-Leel Cascaded Multileel Inerter with low Harmonics Values Hussein A. Konber and Osama I. EL-Hamrawy Department of Electrical Engineering Uniersity of Al-Azhar Cairo, Egypt, hamrawy@gmail.com Mahmoud EL-Bary Department of Power Electronics Electronics Research Institute Cairo, Egypt mahmdali@yahoo.com Abstract A three phase nine-leel cascaded multileel inerter with ery low alues of the undesired low order harmonics is implemented. The switching angles of the inerter power switches are calculated to obtain zero alues of the low order harmonics till the th harmonic for different alues of the output oltage. These alues of the switching angles are then applied to the constructed multileel inerter and the harmonics are measured till the st harmonic. The paper presents experimental results, which show ery low alues of these harmonics as well as for the total harmonic distortion under no load and inductie load. Index Terms Multileel inerter implementation, Multileel inerter harmonics, Selectie harmonic elimination, Total harmonic distortion. I. INTRODUCTION Multileel inerters are widely used in high power industrial applications such as ac power supplies, static VAR compensators, drie systems, etc., []. One of the significant adantages of multileel inerters is the low alues of the produced undesired low order harmonics, een when using low switching frequencies, []. Cascaded multileel inerter is a well-nown multileel inerter topology. It is superior to other multileel inerter topologies, such as diode clamped and flying capacitor multileel inerters [], due to its simple modular structure, ease of control, least number of component and no need for clamping diode or oltage balancing capacitors, [, 5]. The selection of the leel of a multileel inerter is a critical issue, since multileel inerters of higher leels produce lower alues of undesired harmonics and need power switches of lower ratings, but at the cost of increasing the number of components and control complexity. In this paper a three phase nine-leel cascaded multileel inerter is considered. Fig. shows the structure of a single phase of this inerter. It consists of four simple H-bridge inerters, each can produce three output oltages +V dc, 0 or V dc, thus the whole inerter can produce nine oltage leels. Fig. shows an odd-sine symmetric waeform that each phase will be designed to produce. Each H-bridge will be switched on and off only once each half cycle of the main harmonic. The harmonics produced by this way will be the main harmonic in addition to odd sine harmonics only. The switching angles α, α, α, and α are first calculated at different alues of the main harmonics, so as to obtain zero alues of the 5 th, 7 th, and th harmonics, using a selectie harmonic elimination technique [6, 7]. All the undesired low order harmonics till the th harmonic are eliminated in the output line oltage of the three phase cascaded multileel inerter. Noting that the odd tripled harmonic, i.e. ( th, 9 th, 5 th, etc.) are self cancelled by the three phase balancing. The harmonic alues and total harmonic distortion till the st harmonic are registered. Next the construction of the implemented three phase nineleel cascaded multileel inerter is described and experimental measures when applying the calculated switching angles are recorded under no load and inductie load. Fig. single-phase structure of a nine-leel multileel cascaded inerter 98

2 = E [cosα ] 5 = E [cos5α ] 5 7 = E [cos7α ] 7 = E [cosα ] These four relations will be turned to be four equations that are soled to obtain the alues of the switching angles α, α, α, and α ; by setting: = The required amplitude of the main harmonic = 0, = 0, = Fig. Output phase oltage waeform of a nine-leel cascade inerter (taing equal alues of the dc oltage sources) II. CALCULATING THE SWITCHING ANGLES A. Formulation of the problem The Fourier series of the general quarter wae symmetric waeform, similar to that of Fig., with switching angles α, α, α..., α s per quarter cycle is gien by V out ( ω t) = sin(m + ) t 0 a m + with a m+ = Vout sin(m + ) ωtdωt 0 s = V cos(m + ) α (m + ) = Where V is the increase in oltage alue from each switching angle to another. Assuming regular staircase waeform (V =V =...=V s =E), the amplitude of the harmonic oltage m+ is gien by the alues of a m+ i.e. s E m+ = cos(m + ) α (m + ) = For the nine leel inerter four switching angles α, α, α, α are aailable, and the first four non zero harmonics in the output line oltages of the three phase inerter are B. Solution results The aboe four nonlinear equations are soled using the "Newton-Raphson method" [, 8and 9] for the alues = E,.8E,.6E,.E,.E, and.8e Table gies the obtained alues of α, α, α, and α, as well as the percentage total harmonic distortion (THD) in the output line oltage till the st harmonic for each alue of, as defined by 5 THD = ( m + ) / 00 Noting that the tripled odd harmonics (m+=, 9,.) are not considered. Table.the switching angles at different alue of E.8E.6E.E.E.8E α α α α THD % Figure shows the ariations of THD with. Figures and 5 show the harmonic spectrum of the line oltage till the st harmonic for =E and.8e respectiely. It should be noted that under pure inductie load the total harmonic distortion in the current will be much lower, since it is gien by: 5 ( m+ THD = ) / m

3 Fig. the oltage THD ersus Fig. Harmonic spectrum of the line oltage at =E Fig.5 Harmonic spectrum of the line oltage at =.8E Fig.6 Construction of a three-phase nine-leel cascaded inerter The hardware prototype shown in Fig. 6 consists of four main parts as follows: ) The control circuit; An Atmel AT89C5 microcontroller is used as the main processor, which proides the gate logic signals. The microcontroller board is a part of the control unit. It receies the control command from the ey button to enter the alue of the switching angles, and generates the control signals for the gate dries. The microcontroller board consists of one microcontroller chip as the master processor and three microcontrollers as slae processors for generating the control signal for each gates of the module board. The generation of the control signals is realized inside the microcontroller chip. To control the gate signals, the command program, which is implemented in C++ language, is generated on a personal computer and then transferred to the microcontroller on the control circuit board. ) The gate-drier circuit: NE555 is used as a gate-drier, which receies a TTL logic signal from the microcontroller and proides +0 V for the turn on the gate signal and 0 V the for the turn off the gate signal to obtain the proper gate oltages necessary for proper switching of the MOSFET. It is important to isolate the output signal from the drie circuit to aoid the propagation of fault oltages. Isolation is achieed by using optocouplers (type N5). ) The power stage: Four MOSFET, IRFP60, are used as the main switches, which are connected in full-bridge configuration. Each power stage is supplied by a separate dc source E=7 V. Figure 7 shows the experimental configuration III. EXPERIMENTAL ANALYSIS A. Experiment setup The construction of the three phase wye-connected, nine-leel cascaded multileel inerter is illustrated in Fig.6. The power electronics switch used for this particular multileel inerter is IRFP60 MOSFET with oltage ratings of 00V and current ratings of 6A. 985

4 H-bridge power stage Separate DC source Fig. 0 No load pea phase oltage at =.8E=00 Fig. 7 Experimental configuration B. Experimental results -under no load: Figure8 shows the pea phase oltage of the inerter with no load at =E=88 and f=50hz. Figure9 shows the oltage harmonic spectrum at =E=88 The THD measured by a power harmonic analyzer is.8%. Figures 0, and show the same at =.8E=00. The THD measured by a power harmonic analyzer is 7.6%. Fig. 8 No load pea phase oltage at =E=8 Fig. Harmonic spectrum of line oltage at =.8E -under inductie load: The inerter is loaded by a three phase step down transformer 80/ connect to a three phase inductie load each inductance has L=5mH, r =0.9Ω. Figures and show the phase oltage and phase current waeform respectiely of the inductie load at the secondary output of the transformer at = E. Figures and 5 show the harmonic content of phase oltage and phase current at different oltage alues respectiely. The experimental phase oltage THD measured by the power harmonic analyzer 5.79 %. The experimental phase current THD measured by the power harmonic analyzer is.67 %. The alue of each of the dc oltage sources was taen 7. This alue can be changed to obtain any desired alue of the output oltage. It is clear that the inerter produces ery low alues, nearly negligible, of the undesired low order harmonics. Fig. 9 Harmonic spectrum of line oltage at =E 986

5 IV. CONCLUSIONS A three phase nine-leel cascaded multileel inerter is implemented that produces ery low alues of the low order harmonics. The switching angles of the inerter power switches are calculated such that the low order harmonics till the th harmonic are eliminated. Digital generation of switching signals using a microcontroller allows generating the required switching angles for different oltage alues. The harmonics measured till the st harmonic are ery low for different alues of the output oltage, as well the alue of the total harmonic distortion under no load and inductie load. Fig. Output oltage with inductie load, =E Fig. Inductie load current, =E Fig. Voltage harmonic spectrum at =E REFERENCES [] Lai J.S. and Peng F.Z., "Multileel Inerters: A Surey of Topologies, Control and Applications," IEEE Trans.Ind.Elec., ol. 9, pp.7-78, Aug.00. [] A. Muthuramalingam, M. Balaji and S. Himaathi "Selectie Harmonic Elimination Modulation Method for Multileel Inerters" Proceedings of India International Conference on Power Electronics pp.0-5, 006 [] M. Ghasem Hosseini Aghdam S. Hamid Fathi and Georg B. Gharehpetian "Harmonic Optimization Techniques in Multi-Leel Voltage-Source Inerter with Unequal DC Sources" Journal of power electronics.ol.8, No, April 008 pp.7-80 [] Y.Sahali, and M. K. Fellah, "Optimal Minimization of the Total Harmonic Distortion (OMTHD) Technique For The Symmetrical Multileel Inerters Control"st national conference on electrical engineering and its applications (CNEA0), Sidi-bel-Abbes, May [5] Y.Sahali, and M. K. Fellah, "Application of the Optimal Minimization of the Total Harmonic Distortion technique to the Multileel Symmetrical Inerters and Study of its Performance in Comparison with the Selectie Harmonic Elimination technique" SPEEDAM 006 International Symposium on Power Electronics, Electrical Dries, Automation and Motion pp. 9-5 [6] E. Guan, P. Song, M. Ye, and B. Wu, "Selectie Harmonic Elimination Techniques for Multileel Cascaded H-Bridge Inerters", The 6th International Conference on Power Electronics and Drie Systems (IEEE PEDS 005), Kuala Lumpur, Malaysia, pp. -6, 8 Noember- December 005 [7] Jagdish Kumar, Biswarup Das, and Pramod Agarwal "Harmonic Reduction Technique for a Cascade Multileel Inerter" International Journal of Recent Trends in Engineering, Vol, No., May 009 pp.8-85 [8] Q. Jiang, and T. A. Lipo, "Switching Angles and DC Lin Voltages Optimization for Multileel Cascade Inerters", Electric Power Components and Systems, Vol., No., October 005. [9] S. Sirisuprasert, J. Lai, and T. Liu, "Optimum Harmonic Reduction with a Wide Range of Modulation Indexes for Multileel Conerters", IEEE Transactions on Industrial Electronics, Vol. 9, No., pp , August 00 Fig.5 Current harmonic spectrum at =E 987