DESIGN OF HIGH FREQUENCY ISOLATION TRANSFORMER USING MATRIC CONVERTER

Transcription

1 DESIGN OF HIGH FREQUENCY ISOLATION TRANSFORMER USING MATRIC CONVERTER College: SRM UNIVERSITY, CHENNAI Dept:Electrical and Electronics. Batch Members Guide faculty Mr. Anish Raj 1 Mr. K. Venkatasubramani 5 Mr. Paan Kumar 2 Mr. Abhishek Singh 3 Mr. Abhishek Bora 4 Abstract In this paper, a new type of matrix conerter also called a single-phase high-frequency transformer isolated (HFTI) buck matrix conerter (MC) is proposed. The proposed conerter can proide step -down operation of the input oltage with arious types of output oltages such as; in-phase and out-of-phase output oltages, rectified (or positie) output oltage, and output oltage with step-changed frequency. By incorporating HFT isolation, the proposed MC saes an extra bulky line frequency transformer, which is required for the conentional MCs to proide electrical isolation and safety, when used in application such as dynamic oltage restorers (DVRs), etc. Two different circuit ariations of the propose d HFTI MC are presented with and without continuous output currents, with the latter haing less passie components. The safe -commutation strategy is also employed for the proposed HFTI MC to proide current path for the inductor during dead -time, which aoids switch oltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed MC are presented, and switching strategies are also deeloped to obtain arious output oltages. Moreoer, a prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output oltages, and output oltage with step-changed frequency. Index Terms High-frequency transformer, in-phase and out-of-phase operations, rectified output, single-phase matrix conerter, step-changed frequency. I. INTRODUCTION OR ac-ac power conersions in industry, the direct ac-ac conerters are adanced because of their obious merits such as simple topology and control, single-stage conersion, and smaller size. Howeer, these direct ac-ac conerters can only regulate the output oltage without proiding ariable frequency operation, which is also desired in arious ac-ac conersion applications. To proide both Variable output oltage and frequency, the two common solutions are indirect ac-dc-ac conerters with dc-link and matrix conerters. The indirect ac-dc-ac conerters hae some drawbacks, such as two-stage power conersion. Moreoer, they require bulky short-life dclink capacitors and large source filter inductors, which increase their cost, size,losses, and decrease reliability. The MCs can directly conert input ac oltage to ac oltage of a ariable amplitude and frequency in a single-stage conersion without using any intermediate dc-link capacitor. The MCs hae been widely explored in arious researches, coering many aspects such as modulation and control schemes, ac drie applications,and circuit deelopment. The single-phase buck MC was proposed by Zuckerberg et al. in, where the frequency step-up operation was presented. Thereafter, this single-phase buck MC is explored in many studies. The safe-commutation strategy for this MC is proposed in and the frequency step-up and step-down operations are discussed. The experimental results of this MC with sinusoidal PWM scheme and RL load are gien in. The staircase modulation This is an open access article distributed under the Creatie Commons Attribution License, which permits 745

2 technique for this MC is proposed in to improe the output power quality. The applications of this MC are proposed for induction motor dries, induction heating, dynamic oltage restorers (DVRs), and audio power amplification. The single-phase boost MC is used along with a Cockcroft-Walton oltage multiplier in, in order to achiee a high stepup AC-DC conerter with low oltage ripple and ariable oltage gain. A Z-source buck-boost MC is proposed in for applications such as to control the speed of a fan or pump, or to compensate oltage sags and swells as a DVR. A single-phase buck-boost MC is proposed in, which can proide both oltage step-up and step-down operations, similar to the Z-source buck-boost MC, with the benefits of using less actie switches and passie components. All of the single-phase MCs can proide both in-phase and out-of-phase output oltages; and therefore, are ery suitable for application as DVR. The in-phase operation of the MC can be used to compensate oltage sags while out-ofphase operation can compensate oltage swells, when used as a DVR. Fig. 1 shows the configuration of a singlephase MC when used as DVR. When the input oltage is low during oltage sag, the MC produces in-phase oltage s., which is added to the input oltage in to regulate the output oltage o ( - c- in ), as can be seen in Fig. 1. Similarly when the input oltage is high during oltage swell, the MC. + Existing non- In Isolated MCs + 1:1 c + + o Load + V Existing nonin Isolated MCs + 1:1 + c + o Load Line frequency Transformer Line frequency Transformer Fig. 1. The DVR based on the single-phase MC [23]. Compensation of oltage sag. Compensation of oltage swell. Produces out-of-phase oltage VC, which is subtracted from the input oltage in to regulate the output oltage o (= in- c ), as can be seen from Fig. 1. Howeer, these existing single-phase MCs are non-isolated, thus, require a bulky and heay line frequency transformer, as shown in Fig. 1; to proide electrical isolation and safety (for protecting sensitie electronic load) when used in DVR applications. This line frequency transformer has its own shortcomings, such as increased size, high losses, start-up inrush current, saturation problem, etc. In addition, the transformer impedance results in oltage drop, and output oltage harmonics becomes significant with non-linear loads. In this paper, a single-phase high-frequency transformer isolated (HFTI) buck MC is proposed, which can produce in-phase, out-of-phase, and rectified output oltages. Moreoer, output oltage frequency can also be changed in steps. As the proposed MC has HFT isolation, it does not require the extra bulky line frequency transformer for galanic isolation and safety, which increases its power density and decreases its cost, when compared with its non-isolated counterparts with external line frequency transformers. The proposed HFTI MC can be realized with two different secondary side circuits; one with continuous output current, and the other with discontinuous output current. Whereas, the latter would hae less passie components. A commutation strategy is employed for the proposed MC, which aoids the switch oltage spikes without adding any snubber circuits. The operation principle and circuit analysis of the proposed conerter are gien, and switching strategies are also deeloped to obtain arious output oltages. A 200 W laboratory prototype is fabricated and experiments are conducted to produce in-phase/out-of-phase and rectified output oltages, and output oltage with step-changed frequency. This is an open access article distributed under the Creatie Commons Attribution License, which permits 746

3 II. PROPOSED HIGH-FREQUENCY TRANSFORMER ISOLATED BUCK MATRIX CONVERTER Fig. 2. Proposed HFTI buck MC. Type I with continuous output current. Type II with discontinuous outputcurrent. Fig. 2 shows the proposed single-phase HFTI buck MC. The proposed MC has two types: the type I, as shown in Fig. 2, has continuous output current; and the type II, as shown in Fig. 2, has discontinuous output current. The proposed type I circuit [see Fig. 2] consists of four actie switches S 1 S 4 and a dc-blocking capacitor C p on the primary side, an HFT; and capacitor C s, two switches S 5, S6 and an output filter inductor L o and capacitor C o at the secondary side. The proposed type II circuit [see Fig. 2] also has the same primary side components, HFT, switches S 5,S 6 and an output filter capacitor C o on the secondary side, with the only difference being that it can sae capacitor C s and inductor L o at the cost of discontinuous output current. The number of switches used by the proposed MC is only six, which is the same as that used by the non-isolated single-phase buck-boost MC [28], and smaller than that used by the buck, boost and Z-source buck-boost MCs. Moreoer, because both types of the proposed MCs hae the same switching signals, circuit operation and output oltage gain, only type I of the proposed MC [see Fig. 2] is considered in rest of the paper. Similar to the other existing direct ac-ac conerters [1-3] and MCs, the proposed MC also has a commutation problem. Through path is created for the input oltage source in through switches S 1 -S 4, as shown in Fig. 3, which may damage the switches because of oer-current. During dead time, as shown in Fig. 3, the primary side reflected output inductor current ni Lo has no path to flow, and the switches may also be damaged because of oltage spikes. To sole this commutation problem, PWM dead-times are deliberately inserted between complementary switching signals, which aoid the short-circuit problem. Thereafter, - This is an open access article distributed under the Creatie Commons Attribution License, which permits 747

4 either RC snubber circuits are added across switches or soft-commutation strategies are implemented to proide a continuous path for inductor current, which eliminates the switch oltage spikes as well. In this paper, a softcommutation strategy is employed to the proposed HFTI buck MC, which eliminates the switch oltage spikes without using RC snubbers. Fig. 3. Commutation problem of the proposed HFTI buck MC. Oerlap time. Fig.4 In-phase mode operation Fig. 4. Switching signals with safe-commutation and key waeforms of the proposed conerter for in-phase operation mode for reduced switching frequency. This is an open access article distributed under the Creatie Commons Attribution License, which permits 748

5 Fig. 4 shows the switching strategy with soft-commutation and the key waeforms of the proposed MC during the in-phase mode operation for reduced switching frequency. For the positie half-cycle of the input oltage in >0, switch S 1 is switched at high frequency, complementary to switches S 2, S5, with a small dead time. Whereas, the switches S 3,S 4,S 6 are fully turned-on for commutation purpose. Similarly, during the negatie half-cycle of the input oltage in <0, switches S 4 and S 3, S 6 are switched complementary, whereas switches S 1, S 2 and S 5 are now fully turned-on for commutation purpose. Fig. 5 shows the equialent circuits of the proposed MC for VIN=0. Fig. 6 shows the gating signals and key oltage and current waeforms for high switching frequency cycles during the in-phase mode, when in =0. (c) (d) Fig. 5. Equialent circuits of the proposed single-phase MC for in-phase mode. DT interal. Commutation state I. (c) (1-D)T interal. (d) Commutation state II. This is an open access article distributed under the Creatie Commons Attribution License, which permits 749

6 Fig. 6. Switching signals and key waeforms for high frequency switching cycles during in-phase mode when in >0. Fig. 5 shows the equialent circuit during the DT interal when switch S 1 is turned-on, whereas switches S 2,S 5 are turned-off. In this interal, the dc-component of the input oltage is blocked by capacitor C p, whereas the ac component is applied across the primary winding as p, and is also reflected on the secondary side as s -n p. On the secondary side, capacitor C s discharges through the current i Lo, whereas the output inductor L o stores energy in this interal. The current i p through the primary winding is clamped to ni Lo, which is positie and gradually increasing. Applying KVL yields, -in+ Cp +p =0 --cs+ Cs rect =0 (1) -rect +Lo +o=0 At the end of this DT interal, during dead time when switch S 1 is turned-off and switches S 2,S 5 are not yet turned-on, the commutation state I occurs, in which the positie current i Cp ni Lo flows through switch S 3 and the body diode of switch S 2, as shown in Fig. 5. After the dead time ends, the (1-D)T interal begins in which switch S 1 is turned-off, whereas switches S 2,S 5 are turned-on. The equialent circuit during this interal is shown in Fig. 5(c). The capacitor C p gets discharged in this interal, and its current i p flows in the negatie direction to fulfill the charge-balanced condition. The capacitor C p and leakage inductance of HFT are in series, and form a resonant LC tank, due to which the current i p changes smoothly in a sinusoidal manner, as shown in Fig. 6. The primary winding is in parallel with C p ; and therefore, the oltage Cp across C p is reflected on the secondary side as s n Cp, and it charges the capacitor C s. The inductor L o releases the energy to the load in this interal. This is an open access article distributed under the Creatie Commons Attribution License, which permits 750

7 Applying KVL, we obtain Cp + p =0 +Lo +o=0 - s- Cs =0 (2) After the end of the (1-D)T interal, and during dead time when all switches S 1, S 2 and S 5 are turned-off, there are two possible commutation states depending on the i Cp current direction. If the i Cp current has become positie, then the commutation state I occurs again, as shown in Fig. 5. Howeer, if the i Cp current is still negatie, then the commutation state II occurs, in which the i Cp current flows through switch S 4 and the body diode of S 1, whereas the output inductor current flows through switch S 6 and the body diode of S 5. After the end of dead time, the DT interal begins and the same operation is repeated. Applying the olt-sec balance condition on the primary winding yields, Cp D in (3) Furthermore, because Cs n Cp during the (1-D)T interal, and because capacitor maintains its oltage alue (acts as oltage source), Cp n D in (4) Applying the olt-sec balance condition on the secondary winding from (1) and (2), and substituting the alue of Cp from (4), yields rect n in (5) Applying the olt-sec balance condition on the output inductor L o gies, o nd in (6) From (6), it can be concluded that the oltage gain ( o / in ) during this in-phase mode is nd, where n is the turns ratio of the HFT and D is duty ratio. B. OUT-OF-PHASE MODE OPERATION switching frequency. This is an open access article distributed under the Creatie Commons Attribution License, which permits 751

8 Fig. 7. Switching signals with safe-commutation and key waeforms of the proposed conerter for out-of-phase operation modes for reduced Fig. 7 shows the switching patterns with the soft-commutation strategy and key waeforms of the proposed MC for the out-of-phase mode operation. For the positie half-cycle of the input oltage in >0, switch S 2 is switched at a high frequency complementary to switches S S 1, 6, with a small dead time, whereas, the switches S 3, S 4 and S 5 are fully turned-on for commutation purpose. Similarly, during the negatie half-cycle of the input oltage in <0, switches S 3, S 4 and S 5 are switched complementary, whereas switches S 1, S 2, and S 6 are now fully turned-on for commutation purpose. Fig. 8 shows the equialent circuits of the proposed MC for in >0. Fig. 8 shows the equialent circuit during the (1-D)T interal when switches S S 1, 6 are turned-on and switch S 2 is turned-off. In this interal, the dc-component of the input oltage is blocked by capacitors, which is charged by the positie input current, whereas the ac component is applied across the primary This is an open access article distributed under the Creatie Commons Attribution License, which permits 752

9 (c) (d) Fig. 8. Equialent circuits of the proposed single-phase MC for out-of-phase mode. (1-D)T interal. Commutation state I. (c) Commutation state II. (d) DT interal. winding as p and also reflected on secondary side as s =n p. On secondary side, the positie i Cs current and negatie i Lo current pass through switch S 5 and the body diode of S 6. In this interal, the capacitor C s gets charged while the output inductor L o releases energy to the load. Applying KVL yields, -in+ Cp +p =0 - s- Cs =0 (7) Lo +o=0 At the end of this (1-D)T interal, during dead time when switch S 2 is turned-off, whereas switches S S 1, 6 are not yet turned-on, there are two possible commutation states, depending on the i Cp current direction. If the i Cp current is still positie, then the commutation state I occurs, as shown in Fig. 8, in which the current i Cp flows through S 3 and body diode of S 2, whereas the output inductor current i Lo flows through S 5 and the body diode of S 5. Howeer, if the i Cp current becomes negatie, the commutation state II occurs [see Fig. 8(c)], in which the inductor current i Lo passes through the secondary winding and the primary side reflected inductor current i p ni Lo flows through switch S 4 and the body diode of S 1. After the dead time ends, the DT interal begins in which switches S S 1, 6 are turned-off and switch S 2 is turned-on. The equialent circuit during this interal is shown in Fig. 8(d). The capacitor C p gets discharged, and current flowing through it is negatie, which is the same as the primary side reflected output inductor currenti Cp ni Lo. The secondary side capacitor C s is also discharged by the output inductor current. The inductor L o stores the energy released by C s in this interal. Applying KVL, we obtain Cp + p =0 - s -Cs + rect =0 (8) -rect +Lo +o=0 This is an open access article distributed under the Creatie Commons Attribution License, which permits 753

10 After the end of the DT interal, and during dead time when all switches S 1, S 2 and S 6 are turned-off; the commutation state II, as shown in Fig. 8(c), occurs, in which the inductor current i Lo passes through the secondary winding, and the primary side reflected inductor current i p -ni Lo flows through switch S 4 and the body diode of S 1. After the end of dead time, the (1-D)T interal begins, and the same operation is repeated. Applying olt-sec balance condition on the primary winding using (7) and (8) yields, Cp = in(1-d) (9) Substituting (9) into (7) and soling gies, Cs =-n D in (10) Applying the olt-sec balance condition on the secondary winding from (7) and (8), and substituting the alue of Cs from (10), yields rect =-n in (11) The negatie sign in (10) and (11) shows that the oltage polarity of Cs and rect is reersed. Applying the olt-sec balance condition on output inductor L o yields, o =-nd in (12) From (12), it can be seen that oltage gain ( o / in ) during this out-of-phase mode is nd, which is the same as that for the in-phase mode, whereas the - sign show that the polarity of output oltage is reersed. The oltage gain ersus duty ratio for both the in-phase and out-of-phase modes are shown in Fig. 9. In-phase mode Out-of-phase mode Fig. 9. Voltage gain G ersus duty ratio D of the proposed HFTI buck MC conerter when n=1. C. RECTIFIER OPERATION Fig. 10 shows the switching pattern and in, rect and o waeforms for the rectifier operation. From this figure, it can be seen that the rectified positie output oltage o can be obtained from the input ac oltage in by operating the proposed MC in the in-phase mode for the positie half-cycle of in, and then in the out-of-phase mode for the negatie half-cycle of in and so on. This is an open access article distributed under the Creatie Commons Attribution License, which permits 754

11 Fig. 10. Switching strategy and waeforms for rectifier operation. D. STEP-DOWN FREQUENCY OPERATION( f o <f in ) Fig. 11. Switching strategy and waeforms for 30 Hz (step-down) frequency operation. Fig. 11 shows the switching pattern and in, rect and o waeforms for the 30 Hz (step-down) frequency operationfrom this figure, it can be seen that the 30 Hz output oltage o can be obtained from the 60 Hz input ac oltage, by operating it in the in-phase mode for one cycle of the input oltage, and then in the out-of-phase mode for the next cycle of input oltage, and so on. The general switching str. ategy to obtain any n th submultiple (n=1,2,3 ) of the input frequency ( f o -(1/ n f) in ) is summarized below, To obtain een n th submultiples (n=2, 4, 6 ) of the input frequency, the proposed MC is operated in the in-phase mode for one cycle of the input oltage, and then (starting from out-of-phase mode) the out-of-phase and in-phase modes are consecutiely repeated eery half-cycle for (n-2) half-cycles. After that, the proposed MC is operated in This is an open access article distributed under the Creatie Commons Attribution License, which permits 755

12 the out-of-phase mode for one cycle of input oltage, and then (starting from in-phase mode) in-phase and out-ofphase modes are consecutiely repeated eery half-cycle for (n-2) half-cycles, and the same pattern is repeated. To obtain odd n th submultiples (n=1, 3, 5...) of the input frequency, the proposed MC is operated in the in-phase mode for one cycle of the input oltage, and then the out-of-phase (starting from out-of-phase mode) and in-phase modes are consecutiely repeated eery half-cycle for (n-2) half-cycles, and the same pattern is repeated. E. STEP-UP FREQUENCY OPERATION ( f o >f in ): Fig. 12 shows the switching pattern and in, rect and o waeforms for the 120 Hz (step-down) frequency operation. From this figure, it can be seen that the 120 Hz output oltage o can be obtained from the 60 Hz input ac oltage by operating it in the in-phase mode from the positie peak to the negatie peak for a half-cycle of the input oltage, and then in the out-of-phase mode from negatie to positie peak of the input oltage, and so on. The general switching strategy to obtain any n th multiple (n=1,2,3 ) of the input frequency ( f o =nf in ) is summarized below, To obtain een n th multiples (n=2, 4, 6...) of the input frequency, each half-cycle of the input oltage is diided into 1/n time interals, and then the out-of-phase and in-phase modes are consecutiely repeated for each 1/n time interal. Howeer, if the in-phase mode comes first at the at the start of positie half-cycle of the input oltage, then the out-of-phase mode will come first at the start of the negatie half-cycle of the input oltage, ice ersa. To obtain odd n th multiples (n=1, 3, 5...) of the input frequency, each half-cycle of the input oltage is diided into 1/n time interals, and then the out-of-phase and in-phase modes are consecutiely repeated for each 1/n time interal. In this case, if the in-phase mode comes first at the start of the positie half-cycle of the input oltage, then the same mode will come first at the start of the negatie half-cycle of the input oltage, ice ersa. Fig. 12. Switching strategy and waeforms for 120 Hz (step-up) frequency operation. III. COMPONENT DESIGN/SELECTION OF THE PROPOSED HFTIBUCK MC This is an open access article distributed under the Creatie Commons Attribution License, which permits 756

13 The proposed HFTI buck MC uses six actie switches S 1 -S 6, an HFT, and three energy storing components C p, C s and L o. In this section, the design of the HFT/output inductor L o and capacitors C p, C s are presented based on their current and oltage ripples. Moreoer, the oltage and current stresses of the actie switches are gien, and the switches can be selected accordingly. 1) The current ripple of an inductor can be determined as, where, L is the alue of the inductor and L is the oltage applied across the inductor during interal Δt. The oltage across the output inductor and magnetizing inductor of HFT are Cs and Cp, respectiely, during the (1-D)T interal. By substituting these alues into (13), the alues of L o and L m corresponding to current ripples Δi Lo and Δi Lm can be obtained as, respectiely. IV. EFFICIENCY CONSIDERATION TABLE I Switches ( S 1(a b, ) - S 3(a b, ) ) Magnetic core for inductors/hft Capacitors ( C p, C s and C f ) IXGH40N60C2 (600V/40A) PQ5050 MKP K2 ( 6μF/450V ) PARAMETERS FOR EFFICIENCY ESTIMATION AND COMPARISON In this section, the efficiencies of the proposed HFTI buck MCs with continuous output current [see Fig. 2] and without continuous output current [see Fig. 2] are estimated and compared to each other. For this purpose, 300 W topologies of both the proposed conerters are considered using the components as specified in Table I. The three bidirectional switches S (1,4), S (2,3), S (5,6) in both of the proposed conerters are realized by six IXGH40N60C2 IGBTs. The proposed conerter with continuous current requires two Switching strategy and waeform for 120 Hz Frequency A. Where, i o, o, P o are the peak alues of the output current, output oltage and output power, respectiely. 3) The peak oltage stresses of switches S 1 S 6 are gien by, without continuous current requires one core for the HFT This is an open access article distributed under the Creatie Commons Attribution License, which permits 757

14 B.. Furthermore, the proposed conerter with continuous current requires three MKP K2 film capacitors ( C p,c C s, f ), whereas that without continuous current requires only two of these capacitors ( C p,c f ). The loss related parameters gien in Table I are used and PSIM simulations are performed to measure the efficiencies of both proposed HFTI buck MC topologies. Fig. 13 shows these efficiency results when o =110 V rms, D=0.7, f s =20kHz. From this figure, it can be seen that the efficiency of the proposed conerter topology without continuous output current is higher than that with continuous output current. This is because it uses less passie components and has lower magnetic (winding and core) and capacitor losses. Fig. 13. Efficiency of the proposed HFTI buck MCs with and without continuous output currents. V. EXPERIMENTAL RESULTS TABLEII ELECTRICAL SPECIFICATIONS OF THE PROPOSED CONVERTER Output oltage 95 VRMS/ 60 Hz Input oltage (in-phase 136 VRMS mode) Input oltage (out-ofphase 136 VRMS mode) Output power 200 W Switching frequency 20 khz HFT L m =400µH, n=1 Capacitors ( C p,c c ) 6.8µF Output filter inductor ( L f ) 800µH Output filter capacitor ( C o 4.5µF ) This is an open access article distributed under the Creatie Commons Attribution License, which permits 758

15 A hardware prototype of the proposed single-phase HFTI buck MC is fabricated and experiments are performed. The hardware specifications and operating conditions are gien in Table II. To practically realize the switching signals with safe-commutation for arious operating modes, the input oltage polarity is sensed by connecting an LEM LV 25-P oltage transducer across it. The sensed signal is fed into DST-kit, followed by an FPGA, where switching signals for arious operating modes are generated based on the input oltage polarity. Figs. 14 and show measured waeforms of the input oltage in, output oltage o and output current i o for the in-phase and out-of-phase modes, respectiely. Fig. 15 shows the switch oltage stresses S1, S4, and S4 for the in-phase mode operation. Fig. 16 shows the secondary winding oltage s, capacitors i Cs current and output inductor current i Lo for the out-of-phase mode. Figs show the experimental results for the rectified output mode operation with in -136V rms, and D = 0.7. Fig. 17 shows the input oltage in, output oltage o and output current i o waeforms; and Fig. 17 shows the switch gating signal GE1, and oltage stresses S1 and rect. Fig. 18 shows the primary winding oltage s, and capacitor oltages Cp, Cs. Figs. 19 and show the experimental results of the input oltage in, output oltage o and output current i o waeforms for the 30 Hz and 60 Hz frequency modes, respectiely. Fig. 20 shows the switch gating signal GE2, and oltage stresses S2 and rect. All of the experimental results are in good agreement with theoretical analysis and alidate the functions of the proposed HFTI buck MC. [200 V / di ] in in [200 V / di ] o [200 V / di ] o [200 V / di ] i o [5 Adi / ] i o [5 Adi / ] t [10 msdi / ] t [10 msdi / ] Fig. 14. Measured waeforms of input oltage in, output oltage o and output current i o for in =136V rms, and D=0.7. In-phase mode. Out-of-phase mode. S [200 Vdi / ] 1 [200 Vdi / ] S 4 S [200 Vdi / ] 1 [200 Vdi / ] S 4 S Vdi [200 / ] 6 [200 Vdi / ] S 6 t [10 msdi / ] t [20 sdi / ] Fig. 15. Measured waeforms for in-phase mode with in -136V rms, and D=0.7. Switch oltage stresses S 1, S 4, and S 6. Enlarged waeforms of. This is an open access article distributed under the Creatie Commons Attribution License, which permits 759

16 S [200 Vdi / ] S [200 Vdi / ] i CS [20 Adi / ] i CS [20 Adi / ] i Lo [5 Adi / ] i Lo [5 Adi / ] t [5 msdi / ] t [20 sdi / ] Fig. 16. Measured waeforms for out-of-phase mode with in -136V rms, and D=0.7. Voltage S, and currents i Cs,i Lo. Enlarged waeforms of. in [200 Vdi / ] GE Vdi [20 / ] 1 o [100 Vdi / ] S Vdi [200 / ] 1 rect [200 Vdi / ] i o [5 Adi / ] t [10 msdi / ] t [5 msdi / ] Fig. 17. Measured waeforms for rectified output oltage with in 136V rms, and D=0.7. Input oltage in, output oltage o and output current i o. Gating signal GE1, and oltage stresses S1, rect. CP [200 Vdi / ] CP [200 Vdi / ] CS [200 Vdi / ] CS [200 Vdi / ] P [200 Vdi / ] P [200 Vdi / ] t [5 msdi / ] t [20 sdi / ] Fig. 18. Measured waeforms for rectified output oltage with in 136V rms, and D=0.7. Voltage stresses Cp, Cs and p. Enlarged waeforms of This is an open access article distributed under the Creatie Commons Attribution License, which permits 760

17 in [200 Vdi / ] in [200 Vdi / ] o [200 Vdi / ] i o [5 Adi / ] o [200 Vdi / ] i o [5 Adi / ] t [10 msdi / ] t [10 msdi / ] Fig. 19. Measured waeforms of input oltage in, output oltage o and output current i o for output oltages with step-changed frequency. 30 Hz frequency (step-down). 120 Hz frequency (step-up). GE [20 Vdi / ] 2 GE Vdi [20 / ] 2 [200 Vdi / ] S 2 S [200 Vdi / ] 2 rect [200 Vdi / ] rect [200 Vdi / ] t [5 msdi / ] t [20 sdi / ] Fig. 20. Measured waeforms for 30 Hz frequency operation with in 136V rms, and D=0.7. Gating signal GE 2, and oltage stresses S 2, rect. Enlarged waeforms of. VI. CONCLUSIONS In this paper, a buck MC is proposed with HFT isolation. The proposed MC is capable of proiding arious types of output oltages, such as in-phase, out-of-phase and rectified output oltages. Moreoer, the frequency of the output oltage can be changed in steps, so that it is integer multiple or integer fraction of the input oltage frequency. The use of HFT isolation in the proposed MC for electrical isolation and safety benefits in that it remoes the need for extra bulky line frequency transformer, which is added with conentional non-isolated MCs for applications as DVRs. Two different secondary side structures of the proposed HFTI buck MC are proposed, with one haing continuous output current, and the other haing discontinuous out current but with one inductor and capacitor less. The softcommutation strategy is suggested for the proposed MC, which aoids switch oltage spikes without using any snubber circuits. The operation principle and circuit analysis of the proposed conerter are presented and switching strategies are also deeloped to obtain arious output oltages. Moreoer, a 200 W laboratory prototype of the proposed MC is fabricated, and experiments are performed to produce in-phase/out-of-phase and rectified output oltages, and output oltage with step-changed frequency. This is an open access article distributed under the Creatie Commons Attribution License, which permits 761

18 REFERENCES [1] F. Z. Peng, L. Chen, and F. Zhang, Simple topologies of PWM ac-ac conerters, IEEE Power Electron. Letters, ol. 1, no. 1, pp , Mar [2] T. B. Lazzarin, R. L. Andersen, and I. Barbi, A switched-capacitor three-phase ac-ac conerter, IEEE Trans. Ind. Electron., ol. 62, no. 2, pp , Feb [3] H. F. Ahmed, H. Cha, A. A. Khan, and H.-G. Kim, A family of high-frequency isolated single-phase Z-source ac-ac conerters with safe-commutation strategy, IEEE Trans. Power Electron., ol. 31, no. 11, pp , No [4] C. Liu, B. Wu, N. R. Zargari, D. Xu and J. Wang, A noel three-phase three-leg ac-ac conerter using nine IGBTs, IEEE Trans. Power Electron., ol. 24, no. 5, pp , May [5] C. B. Jacobina, I. S. d. Freitas, E. R. C. d. Sila, A. M. N. Lima, and R. L. d. A. Riberio, Reduced switch count dc-link ac-ac fie-leg conerter, IEEE Trans. Power Electron., ol. 21, no. 5, pp , Sep [6] P. Alemi, Y.-C. Jeung, and D.-C. Lee, Dc-link capacitance minimization in T-type three-leel ac/dc/ac PWM conerters, IEEE Trans. Ind. Electron., ol. 62, no. 3, pp , Mar [7] J. W. Kolar, T. Friedli, J. Rodriguez, P. W. Wheeler, Reiew of three-phase PWM ac-ac conerter topologies, IEEE Trans. Ind. Electron., ol. 58, no. 11, pp , No [8]P. C. Loh, R. Rong, F. Blaabjerg, and P. Wang, Digital carrier modulation and sampling issues of matrix conerters, IEEE Trans. Power Electron., ol. 24, no. 7, pp , Jul [9] M. Jussila and H. Tuusa, Comparison of simple control strategies of space-ector modulated indirect matrix conerter under distorted supply oltage, IEEE Trans. Power Electron., ol. 22, no. 1, pp , Jan [10] I. Sato, J. Itoh, H. Ohguchi, A. Odaka, and H. Mine, An improement method of matrix conerter dries under input oltage disturbances, IEEE Trans. Power Electron., ol. 22, no. 1, pp , Jan [11]R. Vargas, U. Ammann, and J. Rodriguez, Predictie approach to increase efficiency and reduce switching losses on matrix conerters, IEEE Trans. Power Electron., ol. 24, no. 4, pp , Apr About the author Hafiz Furqan Ahmed receied his B.S. in Electronics Engineering from National Uniersity of Sciences and Technology (NUST), Pakistan, in He is currently working towards his MS leading to Ph.D. degree in the School of Energy Engineering, Kyungpook National Uniersity, Korea. His current research Interests include high efficiency bidirectional dc-dc conerters, Z-source inerters, and high reliable ac-ac conerters without commutation problem. Honnyong Cha (S 08-M 10) receied his B.S. and M.S. in Electronics Engineering from Kyungpook National Uniersity, Daegu, Korea, in 1999 and 2001, respectiely, and his Ph.D. in Electrical Engineering from Michigan State Uniersity, East Lansing, Michigan, in From 2001 to 2003, he was a Research Engineer with the Power System Technology (PSTEK) Company, An-san, Korea. From 2010 to 2011, he worked as a Senior Researcher at the This is an open access article distributed under the Creatie Commons Attribution License, which permits 762

19 Korea Electrotechnology Research Institute (KERI), Changwon, Korea. In 2011, he joined Kyungpook National Uniersity in the School of Energy Engineering. His current research interests include high power dc-dc conerters, dc ac inerters, Z-source inerters, and power conersion for electric ehicles and wind power generation. This is an open access article distributed under the Creatie Commons Attribution License, which permits 763