PHASE-LOCKED LOOP FOR AC SYSTEMS: ANALYSES AND COMPARISONS

Transcription

1 PHASE-LOCKED LOOP FOR AC SYSTEMS: ANALYSES AND COMPARISONS Siyu Gao*, Mike Barnes* *The Uniersity of Manchester, Oxford Road, Manchester,M13 9PL, UK Keywords: phase-locked loop (PLL), SRF-PLL, EPLL, SOGI-PLL, DDSRF-PLL Abstract As the number of distributed power generation systems (DPGSs) connected to the utility grid is increasing, the issue of synchronization between the DPGSs and the grid is attracting more attention. The phase-locked loop (PLL) technique is considered as the state of art in proiding phase and frequency information for DPGSs. This paper presents quantified analyses and comparisons of the main PLL techniques based on different structures for both single phase and 3-phase systems. The fundamentals of different phase locking principles are explained. Performance of different PLLs when subjected to arious distortions is compared based on quantified PSCAD simulation results. The performance of the PLL module of the PSCAD software package has also been inestigated. 1 Introduction Synchronization with the utility grid oltage is an important matter for DPGSs, which are based on grid-connected power electronic conerters. The phase and frequency information of the utility grid oltage are crucial for ensuring normal operation and control of the conerters and become een more critical when the utility grid is subjected to unbalanced faults. A PLL is a feedback control system which is able to generate an output signal, whose phase and frequency are synchronized with the input reference signal [1]. Figure 1.1 shows the basic structure of a PLL. Phase e Voltage lf ' Loop Filter Controlled Detector Oscillator Figure 1.1 Basic Structure of a PLL The phase detector (PD) block in a PLL is responsible for generating an error signal, which is proportional to the phase difference between the input signal and the output signal of the PLL,. Conentionally, the function of PD is achieed ia a multiplier, as indicated in Figure 1.2. The loop filter (LF) is responsible for reducing the input phase error, which contains AC components, and proides a drie signal for the oltage controlled oscillator (VCO) to generate the frequency and phase outputs [2]. The drawback of the multiplier based PD is that oscillations at twice the frequency of the input signal will be introduced to the phase error signal, e. These oscillations will then be passed to the rest of the system and finally present in the output signal [2]. In order to remoe the double frequency oscillations, a more adanced type of PD is required. Phase Loop Voltage Controlled Detector (PD) Filter (LF) Oscillator (VCO) Kpd e Kp Ki lf Kco (x) ' Figure 1.2 Block Diagram of an Elementary PLL Generally, adanced PD configurations inole adaptie filtering and quadrature signal generation. According to the different configuration and combination of these two techniques, different PD structures can be formed and thus different types of PLL can be built. To improe the performance of the PLL een further, positie sequence extraction is included in some adanced 3-phase PLL structures, such as the 3-phase enhanced PLL (EPLL), double second order integrator PLL (DSOGI-PLL) and decoupled double synchronous reference frame PLL (DDSRF-PLL). This paper is organized as follows. Section 2 is deoted to a brief study of phase detection based on in-quadrature signals and the application of adaptie filtering in PLLs. Study and simulation results of single phase PLLs are presented in Section 3. Section 4 is dedicated to 3-phase PLLs, including analyses for their structure and simulation results. Quantified simulation results and analyses are presented in Section 5. 2 Phase detection based on in-quadrature signals and adaptie filtering 2.1 Phase detection based on in-quadrature signals To sole the problems caused by the multiplier based PD, a PD based on a set of in-quadrature signals can be used. Figure 2.1 shows a PLL with an in-quadrature PD using a quadrature signal generator (QSG). The expression of the error signal e can be deried according to Figure 2.1 [2]. Define as the phase of the input signal V, Define as the output phase signal of the PLL, (1) When the PLL is locked to the input signal,, and thus, which indicates no oscillatory term will be present c

2 once the PLL is synchronized with the input signal and reaches steady state. The deriation of e in (1) is effectiely part of the Park Transform [3, 4], which transforms signals in the stationary reference frame to the dq rotational reference frame. The Park Transform matrix is gien as the following [3, 4]: (2) V Phase Voltage Controlled Detector (PD) Oscillator (VCO) Vsin(t) (x) Loop Filter (LF) Quadrature e lf Kp Ki Signal Generator -Vcos(t) c (x) Figure 2.1 A PLL using an In-Quadrature PD [2] The relation between (1) and (2) can be illustrated geometrically. Figure 2.2, defines the irtual input ector as the ector the PLL is trying to synchronize with. q q o a V d b V = d c d-q = Figure 2.2 Vector Illustration of QSG Output Signals As shown in Figure 2.2,. hence (3) (4) (5) Hence, for the PLL shown in Figure 2.1, is connected to the LF. When synchronization is achieed, will be aligned with the and will be zero. Either or can be connected to the LF, and this will result in different alignment at steady state. If is chosen to be connected to the LF, will be equal to at steady state and will be aligned with the d axis. In this case, will proide the amplitude information of and the phase detected by the PLL will be synchronized with the irtual input ector. This means the phase of the sinusoidal input signal will be 90 ahead of the detected phase generated by the PLL [2]. By introducing the QSG to the PLL, actie and reactie power control can be implemented [2]. For the following discussions, q will be chosen to be connected to the LF. The PLL in Figure 2.1 can now be simplified as in Figure 2.3, where the VCO is replaced by the block known as the frequency/phase-angle generator (FPG). d V QSG PD Park Transform d - dq LF Frequency / Phase-Angle Generator (FPG) q lf Kp Ki Figure 2.3 PLL with q Connected to the LF [2] 2.2 Application of adaptie filtering in PLLs Signals of the electrical utility grid are usually corrupted by noise and harmonics. One way to remoe these interferences is to apply filters. Either fixed or adaptie filters can be used to fulfil the aboe purpose. Yet, the design of fixed filters requires prior knowledge of both the signal and the noise [5], which may be difficult to obtain, especially when the 3-phase grid is subjected to unbalanced faults. On the other hand, adaptie filters are able to adjust their impulse responses automatically according to the output signal of the filters, and their designs require less knowledge of the source signals or noise characteristics [5]. This property of adaptie filters has made them highly useful for a ariety of applications. For PLL applications, the adaptie filtering technique is employed mainly for noise reduction and quadrature signal generation, as is illustrated in the following example. An adaptie filtering structure based on the block known as the second order generalized integrator (SOGI) is shown in Figure 2.4. The characteristic transfer functions can be deried as the following: (6) (7) (8) (9) - e Ke ' K - q' c Second-Order Generalized Integrator (SOGI) Figure 2.4 A Second Order Adaptie Filter based on the Second-Order Generalized Integrator (SOGI) [2] It is eident from (11) that, ' and q ' are a pair of inquadrature signals which makes it possible to apply an adaptie filter based on the SOGI to implement a QSG. Moreoer, from (7) and (8), it can be deried that the bandwidth of the SOGI based adaptie filter is independent of and is only decided by the gain K [2]. Also, when the input frequency matches the centre frequency, the magnitude of ' and q ' will match the magnitude of the input signal. This property is conenient for implementing the Park Transform. (10) (11)

3 3 Modelling of gle Phase PLLs In this section, modelling of 3 different types of single phase PLLs is presented; the simulation results are analysed and compared. 3.1 Modelling of conentional single phase PLL The structure of the basic conentional single phase PLL is shown in Figure 1.2. Figure 3.1 shows the response of this PLL when it is subjected to a frequency jump from 50Hz to 51Hz Time/s Figure 3.1 Simulation Results of the Conentional PLL when subjected to Frequency Jump from 50Hz to 51Hz In Figure 3.1, the double frequency oscillation mentioned in section 1 can be clearly seen in the frequency output. It has also been discoered during the modelling process that, the double frequency oscillation remains in some form whateer the tuning of the PI controller is and will always be present for reasonable tuning alues. In other words, altering the bandwidth of the conentional PLL has limited effect on the double frequency oscillation. ce the phase output of the PLL is effectiely the integration of the frequency output, this distortion is passed to the phase output and thus affects the accuracy of the PLL. 3.2 Modelling of EPLL The structure of the EPLL is presented in Figure 3.2. In the EPLL, the multiplier based PD of the conentional PLL is replaced by an adaptie notch filter to remoe the double frequency oscillation and to proide better noise rejection characteristics [6]. The block responsible for frequency and phase output generation is the same as the basic conentional single phase PLL. The in-quadrature phase detection technique is not used in the EPLL. Adaptie Notch Filter Conentional PLL Structure e - Kp Ki A K (x) (x) Figure 3.2 Structure of the EPLL Figure 3.3 and Figure 3.4 show the responses of the EPLL when subjected to frequency and phase distortions. The EPLL has been tuned to achiee a settling time of 0.1s when subjected to a 1Hz frequency sag. The tuning method has also c tried to minimize the steady state error of the outputs. It is eident from Figure 3.3 and Figure 3.4 that the EPLL is able to reduce the input error to zero and produce reliable outputs. Howeer, the EPLL suffers from high transient oershoots and oscillations during distortions Figure 3.3 Response of EPLL when subjected to Frequency Sag from 50Hz to 45Hz at time 0.5s, lasted for 0.3s Figure 3.4 Response of EPLL when subjected to Phase Jump of 45 at time 0.5s, lasted for 0.3s 3.3 Modelling of SOGI-PLL Figure 3.5 shows the structure of the SOGI-PLL. Both the adaptie filtering technique and in-quadrature phase detection technique are used in the SOGI-PLL to generate the frequency and phase outputs. Figure 3.6 and Figure 3.7 shows the responses of the SOGI- PLL when subjected to frequency and phase distortions. The SOGI-PLL has been tuned to achiee a settling time of 0.1s when subjected to a 1Hz frequency sag. The tuning method has also tried to minimize the steady state error of the outputs. Second-Order Park Generalized Integrator (SOGI) Transform d - e K Ke - ' - q' dq q Figure 3.5 Structure of the SOGI-PLL Frequency / Phase-Angle LF Generator (FPG) Kp Ki lf c Comparing the simulation results of the SOGI-PLL with the results of the EPLLs show that the response of the SOGI- PLL during transients is much less oscillatory than the EPLLs. The transient oershoots of the SOGI-PLL are less seere than the EPLLs, howeer, the oershoots can still be significant if the distortions are substantial. It has also been

4 discoered during the tuning process that the EPLL requires higher controller gains in order to fulfil the same requirements Figure 3.6 Response of SOGI-PLL when subjected to Frequency Sag from 50Hz to 45Hz at time 0.5s, lasted for 0.3s Figure 3.7 Response of SOGI-PLL when subjected to Phase Jump of 45 at time 0.5s, lasted for 0.3s 4 Modelling and Simulation of 3-Phase PLLs Generally, there are two ways to implement a PLL for a 3- phase system. The first one is to use 3 single phase PLLs for each phase to extract the phase angles independently. The transformation from 3-phase abc to dq is not necessary for this structure [7]. A positie sequence extractor can be added to this structure to improe the performance when the system is subjected to unbalanced faults, e.g. the 3-Phase EPLL. The other implementation is to use a 3-phase PLL, which does inole the transformation from 3-phase abc to dq. These two different structures will result in different reference quantities, and thus different control strategies [7]. In this section, modelling of 4 different types of 3-phase PLLs is presented; the simulation results are analysed and compared. 4.1 Synchronous Reference Frame PLL (SRF-PLL) The SRF-PLL is a classic example of 3-phase PLL based on in-quadrature signals. The structure is shown in Figure 4.1.The SRF-PLL structure can be found een within some adanced 3-phase PLLs, located at the output stage to generate the frequency and phase outputs, such as the DSOGI-PLL and the DDSRF-PLL. Clarke and Park Transform V a d FPG LF abc V b lf Kp Ki dq q V c c Figure 4.1 Structure of the SRF-PLL When subjected to noise and harmonics, the bandwidth of the SRF-PLL can be reduced in order to obtain better performance [8], howeer, it is difficult for the SRF-PLL to produce satisfactory outputs when the system is subjected to unbalanced distortions [2]. This problem can be addressed by adding an element dedicated to extracting the positie sequence from the 3-phase oltages, which is used in the DSOGI-PLL and DDSRF-PLL. This technique is also used in the 3-phase EPLL, howeer, as for the single phase EPLL, phase detection based on in-quadrature signals is not included in the 3-phase EPLL Phase EPLL The structure of the 3-phase EPLL is shown in Figure 4.2. Three sets of in-quadrature signals are generated from 3 single phase EPLLs and then passed to the positie sequence extractor (PSE) followed by another single phase EPLL to generate the estimated frequency and phase outputs. Two extra single phase EPLLs can be added to locked on to the positie components of phase B and phase C [9]. Detailed discussion of the 3-phase EPLL can be found in [6]. Va Vb Vc 4.3 DSOGI-PLL Va Vb Vc EPLL (A) EPLL (B) EPLL (C) Va' qva' Vb' qvb' Vc' qvc' Positie Sequence Extractor Va Vb Vc EPLL Figure 4.2 Structure of the 3-Phase EPLL Clarke Transform abc - SOGI- QGS q SOGI- QGS q PSE - Park Transform - dq d q Kp Ki Figure 4.3 Structure of the DSOGI-PLL c The structure of the DSOGI-PLL is shown in Figure 4.3. The principle of the DSOGI-PLL is to use a pair of SOGI based adaptie filters to generate the in-quadrature signals of the stationary reference frame oltages. These in-quadrature signals are then passed to the PSE to proide the positie sequence components for frequency and phase estimation. The DSOGI-PLL is fundamentally different from the 3-phase EPLL and does proide extra filtering. Judging from the results of the SOGI-PLL and the single phase EPLL, the DSOGI-PLL is expected to be less oscillatory during transients than the 3-phase EPLL, which is later shown in

5 simulation results. Detailed discussion about the DSOGI-PLL can be found in [2] and [10]. 4.4 DDSRF-PLL The structure of the DDSRF-PLL is shown in Figure 4.4. The concept of the DDSRF-PLL is that the rotating dq reference frame can be separated into positiely rotating components and negatiely rotating components. If the positiely rotating components are decoupled and extracted from the negatiely rotating components, then the performance of the traditional SRF-PLL can be improed based on the positie components. This idea is discussed in detail in [2] and [11]. Structures of the two decoupling cells are shown in Figure 4.5. It has been discoered during modelling process that, the outputs of the decoupling cells contain quadruple frequency oscillations which are then filtered out by the low pass filters shown in Figure Va Vb Vc V &V - dq abc - Vd Vd * Decoupling Cell Vq Vd - - V &V dq - Vq - Decoupling Cell - Vd * Vq * Vq * c *=Low pass filter Kp Ki Vd * Vq * Figure 4.4 Structure of the DDSRF-PLL Decoupling Cell Vd Decoupling Cell - Vd Vq - Vd * 2 Vd * - Vq * Figure 4.5 Structure of Decoupling Cells The DDSRF-PLL is the most complex PLL among the four 3- phase PLLs discussed in this paper. It is expected that its DSRF structure should be able to delier better performance than the other 3 PLLs. Judging from simulation results shown in the next section, the oerall performance of the DDSRF- PLL does appear to be the most satisfactory. 4.5 Simulations of 3-Phase PLLs The four 3-phase PLLs and the in built PLL module of PSCAD hae been subjected arious distortions in order to ealuate their performance and response characteristics. The configuration of the PSCAD PLL module has been kept as default. Other PLLs hae been tuned to minimize the steady state error and to achiee a settling time of 0.1s when subjected to a 1Hz frequency sag. The adaptie control mechanism proposed in [12] has been used to improe the start-up and transient responses of the PLLs. In Figure 4.6, the PLLs hae been subjected to a -90 phase jump at t=0.5s. The oershoot of the SRF-PLL is the most seere while the EPLL response is most oscillatory. The Vq * Vq PSCADs PLL appears to hae a limiter on its output. Figure 4.7 shows the responses of the PLLs when subjected to a 3- phase to through unbalanced impedances. The SRF-PLL and the PSCADs PLL are not able to recoer within the fault condition and become oscillating. The DDSRF-PLL performs much better than other PLLs during this fault. (a) (b) y (kv,rad) PSCAD-PLL DDSRF-PLL EPLL 32.5 SRF-PLL DSOGI-PLL 3 Time/s (c) V a V b V c SRF-PLL EPLL DSOGI-PLL DDSRF-PLL Va PSCAD-PLL SRF-PLL EPLL DSOGI-PLL DDSRF-PLL Va PSCAD-PLL Figure 4.6 Response of PLLs when subjected to -90 phase jump, (a) Input oltages; (b) Phase outputs and phase A oltage; (c) s; V a V b V c (a) (b) y (kv,rad) DDSRF PLL DSOGI PLL EPLL SRF-PLL PSCAD-PLL 4 4 Time/s (c) SRF-PLL EPLL DSOGI-PLL DDSRF-PLL V a PSCAD-PLL SRF-PLL EPLL DSOGI-PLL DDSRF-PLL V a PSCAD-PLL Figure 4.7 Response of PLL when subjected to unbalanced 3-phase to, (a) Input oltages; (b) Phase outputs and phase A oltage; (c) s From different simulations, a qualitatie conclusion on the responses of these 5 different PLLs can be yielded: (1) The response of the EPLL is the most oscillatory. (2) The SRF-PLL and the PSCADs PLL hae similar responses. Neither of them can recoer during the unbalanced faults used. (3) The DDSRF-PLL deliers the best performance among the fie PLLs when subjected to unbalanced faults used. (4) The DSOGI-PLL is able to generate smooth response, howeer, the oershoots can be high. 5 Quantitatie Comparison on the Performance of Different PLLs In this section, a quantitatie comparison of the performance of the 5 PLLs mentioned in section 4 is presented. The PLLs hae been subjected to arious distortions, including balanced and unbalanced faults. Judging from the results presented in Table 5.1, the DDSRF- PLL appears to be able to delier the best oerall performance

6 as expected. The DSOGI-PLL is able to deliery satisfactory performance, howeer, the transient oershoot can be quite high. The response of the EPLL is highly oscillatory with substantial oershoots. Both the SRF-PLL and the PSCADs PLL are not able to recoer during the unbalanced faults used, and enter a state of constant oscillation. Similarities hae been obsered between these two PLLs, the only significant difference is that PSCADs PLL is able to remoe harmonic contents in the inputs. This function can be added to the SRF- PLL by introducing external filters. Frequency sag (5Hz) Frequency jump (5Hz) Voltage sag (50%) Voltage jump (50%) Phase jump (90 ) Phase jump (-90 ) White noise (25%) 7 th harmonic (20%) 1-phase to 2-phase to 3-phase to Phase-Phase fault Phasephase-phase fault Unbalanced 2-phase to Unbalanced 3-phase to Steady state error SRF-PLL EPLL DSOGI- PLL DDSRF- PLL PSCAD-PLL (limited) (limited) (-3.9,3.9) (-3.3,3.3) (-1.6,1.6) (-3.4,3.2) (-2.1,) (-6.8,6.3) (-4.3,4.1) (-3.0,2.8) (-2.8,2.8) (-1.7,1.6) (-2.6,2.5) Table 5.1 Maximum Frequency Error (Hz) of PLLs when subjected to arious Distortions. Faults are through impedances. 6 Conclusions The study and results in this paper summarize the two widely used techniques in phase detection: in-quadrature signal generation and adaptie filtering. The applications of these two techniques in both single phase PLLs and 3-phase PLLs hae been explained. The locking mechanism of different PLLs hae been explained and clarified in details. Modelling on single phase and 3-phase PLLs hae been undertaken in the PSCAD software package. The simulation results hae reealed the characteristics and responses of different PLLs when subjected to arious distortions. From the simulation results, qualitatie and quantitatie comparisons hae been deried. Both comparisons hae reealed that the EPLL, DSOGI-PLL and the DDSRF-PLL are able to recoer within balanced and unbalanced faults. The DDSRF-PLL is able to delier the best oerall performance. The SRF-PLL and the PSCADs PLL can only recoer within balanced fault conditions and hae shown similarities in their responses to different distortions. Acknowledgements The authors would like to thank the Engineering and Physical Sciences Research Council for supporting this work through grant EP/H018662/1 - Reference [1]. Hsieh, G. C., Hung, J. C., Phase-Locked Loop Techniques A Surey, IEEE Transactions on Industrial Electronics, Vol. 43, No.6, PP: , December [2]. Teodorescu, R., Liserre, M., Rodríguez, P., Grid Conerters for Photooltaic and Wind Power Systems, John Wiley & Sons, Ltd, ISBN: , [3]. Park, R. H., Two-Reaction Theory of Synchronous Machines Generalized Method of Analysis Part I, AIEE Transactions, Volume 48, No. 3, PP: , July [4]. Park, R. H., Two-Reaction Theory of Synchronous Machines II, AIEE Transactions, Vol. 52, No. 2, PP: , June [5]. Widrow, B., et al., Adaptie Noise Cancelling: Principles and Applications, Proceedings of the IEEE, Vol. 63, No. 12, PP: , December [6]. Karimi-Ghartemani, M., Iraani, M. R,. A Method for Synchronization of Power Electronic Conerters in Polluted and Variable-Frequency Enironments, IEEE Transactions on Power Systems, Vol. 19, No. 3, PP: , August [7]. Blaabjerg, F., et al., Oeriew of control and grid synchronization for distributed power generation systems, IEEE Transactions on Industrial Electronics, Vol. 53, No. 5, PP: , October [8]. Chung, S. K., Phase-locked loop for grid-connected three-phase power conersion systems, IEE Proceedings Electric Power Application, Vol. 143, No. 3, PP: , May [9]. Nicastri, A., Nagliero, A., Comparison and ealuation of the PLL techniques for the design of the grid-connected inerter systems, IEEE International Symposium on Industrial Electronics, [10]. Rodríguez, P., et al., New Positie-sequence Voltage Detector for Grid Synchronization of Power Conerters under Faulty Grid Conditions, 37th IEEE Power Electronics Specialists Conference, [11]. Rodríguez, P., et al., Decoupled Double Synchronous Reference Frame PLL for Power Conerters Control, IEEE Transactions on Power Electronics, Vol. 22, No. 2, PP: , March [12]. Karimi-Ghartemani, M., et al., Problems of Startup and Phase Jumps in PLL Systems, IEEE Transactions on Power Electronics, 2011.