2.4 Modeling and Analysis of Three Phase Four Leg Inverter

Transcription

1 2.4 Modeling and Analysis of Three Phase Four Leg Inverter The main feature of a three phase inverter, with an additional neutral leg, is its ability to deal with load unbalance in a standalone power supply system [7],[2]. The goal of the three phase four leg inverter is to maintain the desired sinusoidal output voltage waveform over all loading conditions and transients. It is ideal for applications like data communication, industrial automation, military equipment, which require high performance uninterruptible power supply. As shown in Figure.2, the three phase four leg inverter is used in the shipboard DC DPS to provide secondary AC power distribution. It can be utilized to supply utility power for combat equipment, radar and other critical electronic load. In this section, the modeling and control of a PEBB based three phase four leg inverter is described. Modeling of the four leg inverter has been discussed in the literature [7]. But, effect of power stage coupling and sampling delay on control design has not been addressed. This section investigates two control strategies and their limitations Principle of Operation Figure 2.7 shows the three phase four leg inverter composed of PEBBs. Four PEBB cells with integrated gate drives are configured to form the Four Leg Inverter power stage. The additional PEBB leg is connected to the neutral of the load. A DSP based local controller Chapter 2 36

2 V DC F I L T E R F I L T E R 3φ 3 Phase 4 Wire Driver Driver Driver Driver Sensor Board V ac DSP Interface Board V DC DSP (I,V Loop, PWM Generation) Hierarchical Control (Host Computer) Figure 2.7 : PEBB based Three Phase Four Leg Inverter : Four PEBB cells with integrated gate drives are configured to form the Inverter. The additional PEBB cell is connected to the neutral of the load. Chapter 2 37

3 supplies gate drive commands through a DSP interface board. The feedback control loop is implemented digitally using the DSP. The PEBB system includes a sensor board which senses the DC link voltage and output capacitor voltage and provides feedback to the local controller. The structure of the PEBB based system inverter (Figure 2.7) is similar to that of boost rectifier (Figure 2.3). Both of them have the same general purpose controller configuration. The difference lies in the control algorithm implemented in the local controller. Figure 2.8 shows the discrete switching model of three phase four leg inverter simulated using SABER. The PEBB cells are modeled as ideal switches with antiparallel diodes. The power stage comprises of four leg inverter with an output LC filter to attenuate the switching ripple in the output voltage. The additional PEBB leg is connected to the load neutral. As compared to the conventional inverter, the Four Leg Inverter has the additional freedom of controlling the load neutral potential. This allows it to maintain balanced output voltage in presence of unbalanced and nonlinear load [7]. The output filter capacitor voltages are sensed and fed back to the local controller (DSP). The voltages are converted from stationary coordinates to rotating coordinates to generate V d,v q,v 0. These are compared to the reference voltages and the error voltages are passed through a compensator. The controller is implemented in rotating coordinates. The output of the compensator, i.e. d d, d q, d 0 are inverse transformed to stationary coordinates to yield dα, d β, dγ. Finally, a complex 3 dimensional space vector modulation scheme yields the duty cycles for the 6 power switches [7]. Chapter 2 38

4 PEBB Output Filter Nonlinear Unbalanced Load Vdc F I L T E R a a a a L L N C Vφ Driver Driver Driver Driver V cap d αβγ 3D SVM Inverse Rotating Transformation Sampling Delay d dq0 Voltage Compensator abc/dq0 Rotating Transformation + V dq0 Voltage Reference Digital Processor Controller Figure 2.8 : Discrete Switching Model of the Four Leg Inverter : It provides time domain information. The output filter capacitor voltages are sensed and fed to the compensator. The controller is shown in the dotted box. Chapter 2 39

5 2.4.2 Power Stage Modeling Figure 2.20(a) shows the power stage model of the three phase four leg inverter with a second order load filter. The average model in stationary coordinates is shown in Figure 2.20(b). The power stage parameters are given in Appendix A. The output voltage and input current in the inverter can be represented as : V V V a n 0 0 b n 0 0 c n 0 0 = d d d an bn cn V g, I p = [ dan dbn dcn ] I I I a b c where, V in (i=a 0,b 0,c 0 ) are the inverter output voltages (lineneutral), I i (i=a,b,c) are line currents. And, d in (i=a,b,c) are the linetoneutral duty cycles The duty cycles d in (i=a,b,c) are controlled in a way so as to produce sinusoidal voltages at output of the filter irrespective of the load i.e. the load could be light, heavy, unbalanced or nonlinear. The system requirement can be represented as : V V V an bn cn cos( ωt) 0 = V t m cos( ω 20 ) 0 cos( ωt + 20 ) Chapter 2 40

6 POWER STAGE OUTPUT FILTER nonlinear and/or unbalanced load Vdc F I L T E R Vn Ln Va Vb Vc L C Vφ neutral (a) Discrete Switching Model POWER STAGE OUTPUT FILTER nonlinear and/or unbalanced load Vdc F I L T E R I p d an *V g d bn *V g d cn *V g a o b o c o n o L L L Ln Co c b n a Z (b) Average Large Signal Model Figure 2.9 : Power Stage Modeling in Stationary Coordinates: The process of averaging replaces the switches with controlled voltage and current sources. Chapter 2 4

7 where, V in (i=a,b,c) is the output load voltage and, V m = rated output voltage To produce the desired sinusoidal output voltages, the steady state duty cycles are timevarying and sinusoidal. But, to apply classical control techniques we need a DC operating point. Thus, we apply the transformation T, given in Appendix C, to get the power stage model in rotating coordinates. Figure 2.20 gives the power stage model in rotating coordinates and it is redrawn as a signal flow graph in Figure 2.2. The d and q subcircuits have coupled voltage and current sources, shown as the shaded region. The steady state output load voltages and the duty cycles are DC quantities and are given as : V V V d q o = V 0 0 m, where, V m = rated output voltage And, the duty cycles are given by : 2 D ( ω LC) V V d D ωli d = q D V g o 0 m g Chapter 2 42

8 ω LI q L I V d d d d *V g ω CV q I p d q *V g ω LI d I q ω L CV d V q L+3Ln d 0 *V g V 0 Figure 2.20 Power Stage Average Model in Rotating Coordinates : The d and q subcircuits have coupled voltage and current sources, shown as the shaded blocks. Chapter 2 43

9 R dd + + V g sl i Ld i cd ω L ωc sc V d dq ω L V g sl i Lq ωc i cq sc V q R R d0 + V g s( L+ 3Ln) i L0 + i c0 sc V 0 Figure 2.2 : Average Model represented as a Signal Flow Graph : The coupling in d and q sub circuits is shown as the shaded blocks. The load is represented as a resistive load (R). Chapter 2 44

10 The load of the system is represented as a disturbance and is assumed resistive. The Output power varies from 00% to % rated power. The system is designed for 50 kw rated output. Thus, the load varies from.53 ohm to 53 ohm. The Average Large Signal model, shown in Figure 2.20 is simulated using SABER and it is perturbed and linearized at an operating point to get Small Signal model. The small signal model is utilized for control design. The open loop control to output transfer function is shown in Figure 2.22 and Neglecting the coupling in the power stage, the open loop transfer function is approximated as: V d d d V g V g s L = R s 2 LC s s ω Q ω o 2 2 o Where, the resonant frequency is given by ω o = LC and is ~ 872 Hz. The Q of the circuit depends on R, thus we have large Q when R is large (Light Load). As shown in Figure 2.22, the control to output transfer function exhibits peaking for light load situation. The phase plot shows a steep drop by 80 0 near the resonant frequency. In case of heavy load situation, the controltooutput transfer function is well damped and it shows a phase drop of 90 0 at the resonant frequency. The controller is designed to satisfy the system performance for both heavy and light load situation. Chapter 2 45

11 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.22 : ControltoOutput Transfer Function for Light Load : The V d /d d transfer function for light load situation shows peaking around 872 Hz (Resonant Frequency). It has a steep phase drop of 80 0 at resonance. Chapter 2 46

12 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.23 : ControltoOutput Transfer Function for Heavy Load : The V d /d d transfer function for heavy load situation is well damped and does not exhibit peaking at resonance.. It has a phase drop of 90 0 at resonance. Chapter 2 47

13 Digital implementation of the current controller introduces a sampling delay, as discussed in [5]. The delay yields 80 0 phase lag at half the switching frequency and must be taken into account. It is given by: e st s T = 2 s T sT sT +, where T = Sampling Time The switching frequency of 20 khz introduces 80 0 phase delay at half the switching frequency and around 5 0 phase lag at the resonant frequency. The power stage is a highly coupled multivariable multiloop system. The coupling between the d and q channels of the power stage is represented as the shaded blocks, as shown in Figure 2.2. It has coupled voltage sources given byω L and current sources given by ω C. In order to independently control the dqo channels of the power stage, the power stage must be decoupled. The voltage sourceω L, is canceled by adding a factor (ω L/V g ) in the d and q channel duty cycles, as shown in the Figure The power stage cannot be fully decoupled due to the presence of the delay term at the output of the modulator as seen in Figure As a result, the power stage with nonideal decoupling is given by Figure Decoupling the power stage reduces the peaking in the controltooutput transfer function and improves the phase drop near resonant frequency. Chapter 2 48

14 Decoupling Circuit R ddc ωl Vg e st + + ω L ωc V g sl i Ld i cd sc V d dqc + ωl Vg e st ω L V g sl i Lq ωc i cq sc V q R R d0 e st + V g s( L + 3Ln) i L0 + i c0 sc V 0 Figure 2.25 : Power Stage Decoupling : The voltage source ω L which couples d and q subcircuits is canceled by introducing a term (ω L/V g ) in the controller. It is not possible to cancel the current sources ω C by this strategy. Chapter 2 49

15 R ddc e st + V g sl st ( ω L) ( 05. ) st + ( st) i Ld i cd ω C sc V d dqc e st st ( ω L) ( 05. ) st+ ( st) 2 V g sl + 2 i Lq ωc i cq sc V q R d0 e st V g s( L+ 3Ln) + i L0 + i c0 R sc V 0 Figure 2.26 : Partially Decoupled Power Stage : The voltage source ω L which couples d and q subcircuits cannot be totally eliminated due to the presence of delay term e st. It has been reduced by a factor (e st ). Chapter 2 50

16 2.4.3 Control Loop Design The Average Large Signal model with partially decoupled power stage, shown in Figure 2.25 is used to generate the small signal characteristics for the inverter. Figure 2.26 shows the control structure for capacitor voltage loop control. The output filter capacitor voltages are sensed and transformed from stationary to rotating coordinates. These are fed as feedback signals to dq0 channel voltage compensators. The voltage loop gain T V is given by: T V = Vd d H d V The control to output transfer function V d /d d is given in Figure 2.22 and Figure As discussed in the previous section, the effect of delay and light load places a severe constraint in the control loop design. Three phase four leg inverter is a multiloop and highly coupled multivariable system. As the first step, the dqo channel compensators are designed independently i.e with other 2 channels assumed open. After the compensators have been designed for all three channels, the loop gain in a channel is measured again with other 2 loops closed as shown in Figure This is to verify the stability of the system. Two control design strategies are presented in this section. The dynamic performance of the inverter with the two control strategies is presented in the next section. Chapter 2 5

17 R d d e st + V g sl st ( ω L) ( 05. ) st + ( st) i Ld i cd ω C sc V d d q e st st ( ω L) ( 05. ) st + ( st) 2 V g sl + 2 i Lq ωc i cq sc V q R d 0 e V + st g s( L + 3Ln) i L0 + i c0 R sc V 0 T V d d H V + V dref Voltage Compensator (dchannel) d q Voltage Compensator (qchannel) V q V qref d 0 Voltage Compensator (0channel) V 0 V 0ref Figure 2.26 : Capacitor Voltage Loop Control (dchannel): The power stage is shown inside the dotted box. While designing d loop, other two channels i.e. q and 0 channels are left open. Chapter 2 52

18 R d d e st + V g sl st ( ω L) ( 05. ) st + ( st) i Ld i cd ω C sc V d d q e st st ( ω L) ( 05. ) st + ( st) 2 V g sl + 2 i Lq ω C i cq sc V q R d 0 e V + st g s( L + 3Ln) i L0 + i c0 R sc V 0 T V d d H V + V dref Voltage Compensator (dchannel) d q V q Voltage Compensator (qchannel) V qref d 0 Voltage Compensator (0channel) V 0ref V 0 Figure 2.27 : Actual Loop Gain (dchannel) : After designing dq0 channel compensators, the actual d channel loop gain is measured by keeping q and 0 channels closed. Chapter 2 53

19 2.4.3 (a) Design Strategy I (PI Compensator) As shown in Figure 2.22, the controltooutput transfer function V d /d d has a large peaking at the resonant frequency of 872 Hz under light load situation. It has a phase drop of nearly 80 0 at resonance. One possibility is to use a PI compensator and close the voltage loop much below resonance so that the phase drop and peaking effect at resonance do not affect system stability. The compensator can be implemented as a PI. This is given by : H V K K i i = K p + = + s s s Ki K p Figure 2.28 shows the asymptotic plot of the loop gain. The controltooutput transfer function has a complex pole at 872 Hz, shown as the dotted curve. A pole is placed at the origin to give zero steady state error. The zero given by K i /K p is placed beyond the loop gain crossover. The crossover frequency is chosen low so that there is sufficient gain margin. Figure 2.29 shows the loop gain T V for the light load situation. It has a small bandwidth of the order of 0 Hz and has a gain margin of around 5 db. Figure 2.30 shows the loop gain for the heavy load situation. It is well damped and has 35 db gain margin and has a phase margin of around It shows that the design is not optimized for the heavy load situation. And, designing the same compensator for % 00% load yields a poor design if conventional PI compensator strategy is employed. Chapter 2 54

20 Gain (db) V d /d d Transfer Function ω z ω 0 2 f BW Gain Margin ω 0 = 872Hz add integrator and zero H f φ V BW m K = K p + s = 0Hz = 90 0 i k p =.2e5, k i = 0.07 Figure 2.28 : Asymptotic plot of Loop Gain (Design I) : An integrator is added to ensure zero steady state error. The cross over frequency is less than the resonant frequency. Chapter 2 55

21 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.30 : Loop Gain under Light Load (Design I) : The loop gain cross over frequency is 0 Hz and it has 5 db gain margin. The peaking under light load situation restricts the cross over frequency. Chapter 2 56

22 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.3 : Loop Gain under Heavy Load (Design I) : The loop gain cross over frequency is 0 Hz and it has 35 db gain margin. It has a phase margin of around Chapter 2 57

23 2.4.3 (b) Design Strategy II ( 4 zero/5 pole compensator) As discussed in the previous section, closing the loop gain below the resonance yields low system bandwidth and this results in a poor transient response. Another possibility is to close the system loop after resonance. It is investigated in this section. Figure 2.28 shows the asymptotic plot of the controltooutput transfer function which has a double pole at resonant frequency of 872 Hz. The effect of 80 0 phase lag at resonance and presence of delay at higher frequencies must be taken into account. A pole is placed at the origin to give zero steady state error. This yields 90 0 phase lag and thus we have around phase at resonance. This phase lag must be compensated by zero s in the compensator. If we choose to use a 2 zero/3pole compensator, then the two zeros must be placed one decade below resonance so that they yield 80 0 at resonance. As a result of peaking at light load, the loop gain around 20 Hz would be very small. The compensator finally chosen is 4 zero/5 pole given as : H V = K s s s s ( + )( + )( + )( + ) z z2 z3 z4 s s s s s( + )( + )( + )( + ) p p p p Where, z = 780 Hz, z 2 = 800 Hz, z 3 = 820 Hz, z 4 = 840 Hz and, K = 3.5, p = khz, p 2 = 2.5 khz, p 3 = 0 khz, p 4 = 0 Hz Chapter 2 58

24 Placing four zeros near resonance yields 45 0 from each zero and thus a total of Thus, we can compensate the phase lag due to the double resonant pole of the power stage. As seen in Figure 2.22, the Q of the power stage shows a peaking between 600 Hz to 500 Hz. Thus, the four zeros are placed in this region so as not to increase the peaking effect. Final placement of the zeros is chosen according to the tradeoff between cross over frequency and phase margin. In order to attenuate switching frequency ripple, 2 poles are placed at half the switching frequency. The other 2 poles are placed before the cross over frequency such that the loop gain crosses over with 20 db/decade slope. Figure 2.3 shows the asymptotic plot of the system loop gain with 4 zero/5 pole compensator. The four zeros are represented as z 4 and two poles are shown as p,2. The loop gain has a pole at origin and two poles at half the switching frequency. Figure 2.32 shows the loop gain for light load situation. The loop gain has a cross over frequency of 2 khz and phase margin of The phase of the system drops sharply after 2.5 khz due to the effect of the digital delay. Hence, as a precautionary measure taking into account parameter variability the bandwidth is chosen around 2 khz. It has around 2 db gain at 20 Hz. The significance of this will be seen in the later Figure 2.33 shows the loop gain for heavy load situation. The loop gain has same cross over frequency of 2 khz and phase margin of It has higher phase margin as the phase lag at resonance is not as steep as in light load situation. The phase of the system drops sharply after 2.5 khz due to the effect of the digital delay. It also has around 2 db gain at 20Hz. Chapter 2 59

25 Loop Gain Gain (db) f BW z,2,3,4 p,2 Frequency (Hz) ω 0 = 872Hz H f φ V BW m = K s s s s ( + )( + )( + )( + ) z z2 z3 z4 s s s s s( + )( + )( + )( + ) p p p p = 2kHz = Figure 2.3 : Asymptotic plot of Loop Gain (Design II) : An integrator is added to ensure zero steady state error. The cross over frequency is more than the resonant frequency. Chapter 2 60

26 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.32 : Loop Gain under Light Load (Design II) : The loop gain cross over frequency is 2 khz and it has a phase margin of The phase drops sharply after cross over due to the effect of digital delay. Chapter 2 6

27 Gain (db) Frequency (Hz) Phase (degrees) Frequency (Hz) Figure 2.33 : Loop Gain under Heavy Load (Design II) : The loop gain cross over frequency is 2 khz and it has 2 db gain at 20 Hz. It has a phase margin of around Chapter 2 62

28 2.4.4 Simulation Results The three phase four leg inverter, shown in Figure 2.8 is designed to supply 50 kw output power. The power stage parameters are given in Appendix A. The control design strategy II is chosen as the optimum strategy. The system operation is verified for load variation from % to 00% rated load. The switching frequency employed is 20 khz. Figure 2.34 shows the simulation results for light load situation. The system has a settling time of around 3 ms. The output load voltages are balanced sinusoids. Figure 2.35 shows the simulation results for heavy load situation. Again, the system has a settling time of around 3 ms. This is due to the fact that the loop gain are designed such that the cross over frequency is the same for both light and heavy load situation. The output load voltages are sinusoidal and the system has a good transient response for balanced load situation irrespective of the load value. Control design II is superior to design I as the cross over frequency in case II is much higher than case I. Dynamic simulations of inverter employing strategy I show that the settling time for output load voltages is of the order of 00ms. Figure 2.34 and 2.35 also show the plot of V d and V q. The compensator is designed in rotating coordinates and hence it controls V d and V q. The final output voltages is derived from them after applying the transformation T. The V 0 turns out to be 0 in these simulations as the load is taken as the balanced load. Chapter 2 63

29 Time (s) (a) V d, V q plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.34 : Dynamic Performance under Light Load (Design II) : The transient settles response settles in around 3ms. The output voltages are balanced sinusoids. Chapter 2 64

30 Time (s) (a) V d, V q plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.35 : Dynamic Performance under Heavy Load (Design II) : The transient settles response settles in around 3ms. The output voltages are balanced sinusoids. Chapter 2 65

31 2.4.5 Effect of Unbalanced and NonLinear Load The three phase four leg inverter is supposed to provide rated load voltage in presence of unbalanced and nonlinear load. Fig (a) shows the system with one phase loading. The average model in stationary coordinates is transformed to rotating coordinates using the transformation T, discussed in Appendix C. The unbalanced load represented by a resistor R results in a line current given by : I I I a b c ( ) Vm R = 0 0 cosω t The line currents can be transformed to positive, negative and zero sequence currents, explained in Appendix D [8]. These currents can then be transformed from stationary to rotating coordinates as given by : I I I d q 0 2 Vm = + cos ω t 3R sin2 ω t cos ω t Figure 2.37 (b) gives the power stage model in rotating coordinates with load represented as current sources. Chapter 2 66

32 POWER STAGE OUTPUT FILTER LOAD d an *V g a o L i a a I p d bn *V g b o L b d cn *V g c o n o L Ln Co i n c n R ω LI q I d L V d d d *V g ω CV q I Ld d q *V g ω LI d L V q I q ω CV d I Lq L+3Ln d 0 *V g V 0 I L0 Figure 2.36 ab : Unbalanced Load situation in Stationary & Rotating Coordinates Chapter 2 67

33 The steady state duty cycles required by the inverter are calculated as ; D D D d q 0 2 ( m ) ( ) V m ω LC ωl V sin 2ω t 3 R = L( Vm )( 2 ) Vg ω cos ω t 3 R L( Vm ω 3 R ) sin ω t The steady state duty cycles required by the system are DC quantities and a sinusoidal component at twice the output frequency i.e 20 Hz and the 0 channel has a sine term of 60 Hz. The unbalanced load presents a 2 nd order harmonic in d and q channels which must be attenuated by the loop gain at that frequencies. The system requires sufficient bandwidth to take care of unbalanced loads. The system performance with the two control strategies is investigated in this section. Figure 2.37 shows the dynamic performance with control design I. The system is loaded one phase with the rated load. It is seen that the output voltages are not balanced and have a low frequency oscillation. This is due to the presence of 20 Hz ripple in V d and V q and a 60 Hz ripple in V 0. These have not been attenuated due to insufficient loop gain at these frequencies. Figure 2.38 shows the dynamic performance with control design II. It can be seen that output voltages are sinusoidal and the control design meets the system specifications. The 20 Hz ripple in V d and V q and the 60 Hz ripple in V 0 have been attenuated due to Chapter 2 68

34 Time (s) (a) V d, V q,v 0 plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.37 : Dynamic Performance under Unbalanced Load (Design I) : The output voltages are not perfectly sinusoidal. V d and V q have large 20 Hz ripple. Chapter 2 69

35 Time (s) (a) V d, V q,v 0 plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.38 : Dynamic performance under Unbalanced Load (Design II) : The output voltages are balanced sinusoids. V d and V q have small 20 Hz ripple. Chapter 2 70

36 sufficient loop gain at these frequencies. The system performance is superior than previous case. It is the most suitable control design approach. The three phase four leg inverter is supposed to provide rated load voltage in presence of nonlinear load. Fig (a) shows the system feeding a typical nonlinear load, diode rectifier. Diode rectifier is a very popular topology used as a frontend in many electronic loads. Figure 2.39 (b) shows the current drawn by the rectifier when fed by an ideal sinusoidal voltage supply. It draws a current rich in harmonics. Figure 2.39 (c) shows the input current spectrum. The current has components at 5ω,7ω, ω and 3ω. Where, ω is the fundamental output frequency i.e. 60 Hz. The system performance with the two control strategies is investigated in this section. Figure 2.40 shows the dynamic performance with control design I. It is seen that the output voltages are distorted and have a voltage peak of 450 V. Thus the output voltages are around 5% over voltage and they do not meet the specifications. The V d and V q have large ripple. These have not been attenuated due to insufficient loop gain at these frequencies. Figure 2.4 shows the dynamic performance with control design II. It can be seen that output voltages are less distorted and do not have any significant over voltage. The system performance is not as good as in unbalanced case as the loop gain does not have sufficient bandwidth at high frequencies to reduce their effect on the outer load voltage. The system performance is superior than Design I. It is a better control design approach Chapter 2 7

37 Power Stage Output Filter Nonlinear Load Vdc F I L T E R Vn Ln Va Vb Vc L C Vφ Controller (a) Inverter feeding Diode Rectifier (NonLinear Load) (b) Input Current Drawn By the Rectifier (c) Input Current Harmonic Spectrum Figure 2.39 : Four Leg Inverter Feeding NonLinear Load : The diode rectifier is taken as the nonlinear load. The input current drawn by the rectifier has frequency components at 5,7, and 3 times fundamental frequency (60 Hz). Chapter 2 72

38 Time (s) (a) V d, V q,v 0 plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.40 : Dynamic Performance under NonLinear Load (Design I) : The output voltages are distorted and have harmonics. It has around 5% over voltage. Chapter 2 73

39 Time (s) (a) V d, V q,v 0 plot Time (s) (b) Output Voltages V a, V b, V c Figure 2.4 : Dynamic performance under NonLinear Load (Design II) : The output voltage distortion is reduced and it does not have any significant over voltage. Chapter 2 74

40 2.5 Summary This chapter presented the modeling and control of a PEBB based Boost Rectifier and Four Leg Inverter. The main feature of a PEBB based system is standardization and ease of design. It was shown that a common standardized controller can be used for both applications. This results in lower procurement cost and reduced spare parts inventory for typical medium power Navy applications and it justifies the additional material cost of the general purpose PEBB converter as compared to customdesigned converters. A three level modeling approach was adopted. Based on the small signal analysis, closed loop design guidelines for the Boost Rectifier are proposed. A DSP based discrete switching model of the Boost Rectifier was developed. The closed loop simulation of Boost Rectifier verified the controller design. Fault tolerance concept was demonstrated by ensuring stable system operation of the rectifier with one leg of the rectifier failed opencircuited. A PEBB based system has the ability to reconfigure in case of a fault condition. Whereas, the conventional system suffers from the drawback that if one of the legs of the rectifier switches fails then the system has to be shut down. Thus we need to have redundancy in the system and this increases the cost of the system. A PEBB based converter can assure reliable delivery of electric power to the loads, high system efficiency and flexibility in system operation. The local controller has communication ports to receive information regarding the system state and fault situation from the system controller and it can reconfigure the system in case one of the PEBB cell fails opencircuited. Chapter 2 75

41 Also, the issues in the modeling and control of four leg inverter were investigated in this chapter. The effect of power stage coupling and sampling delay on the control design has been studied. It was found that digital implementation of the controller introduces a sampling delay in the system and this places a severe constraint in control design. It was found that loading on the inverter changes the controltooutput transfer function and must be taken into account while designing the loop gain. Two control loop designs were presented. The performance of the inverter with the two designs was presented. The ability of a four leg inverter in dealing with unbalanced and nonlinear loads was presented. It was established that in order to deal with unbalanced load, the loop gain must have sufficient gain at 2ω where ω is the fundamental output frequency (i.e. 60 Hz). A diode rectifier was used as an example of a typical nonlinear load. The input current drawn by the rectifier has significant frequency components at ω, 5ω, 7ω, ω. It was shown that insufficient loop gain at these frequencies result in distorted output voltages. And, these voltage distortions can be reduced by designing a complex 4 zero 5 pole voltage loop compensator. Chapter 2 76