Chapter 11 Operational Amplifiers and Applications

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1 Chapter Operational Amplifiers and Applications

2 Chapter Goals Understand the magic of negatie feedback and the characteristics of ideal op amps. Understand the conditions for non-ideal op amp behaior so they can be aoided in circuit design. Demonstrate circuit analysis techniques for ideal op amps. Characterize inerting, non-inerting, summing and instrumentation amplifiers, oltage follower and first order filters. Learn the factors inoled in circuit design using op amps. Find the gain characteristics of cascaded amplifiers. Special Applications: The inerted ladder DAC and successie approximation ADC

3 Differential Amplifier Model: Basic Represented by: A = open-circuit oltage gain id = ( ) = differential input signal oltage R id = amplifier input resistance R o = amplifier output resistance The signal deeloped at the amplifier output is in phase with the oltage applied at the + input (non-inerting) terminal and 80 out of phase with that applied at the - input (inerting) terminal.

4 LM74 Operational Amplifier: Circuit Architecture Current Mirrors

5 Ideal Operational Amplifier The ideal op amp is a special case of the ideal differential amplifier with infinite gain, infinite R id and zero R o. = o id and lim = 0 A id A If A is infinite, id is zero for any finite output oltage. Infinite input resistance R id forces input currents i + and i - to be zero. The ideal op amp operates with the following assumptions: It has infinite common-mode rejection, power supply rejection, openloop bandwidth, output oltage range, output current capability and slew rate It also has zero output resistance, input-bias currents, input-offset current, and input-offset oltage.

6 The Inerting Amplifier: Configuration The positie input is grounded. A feedback network composed of resistors R and R 2 is connected between the inerting input, signal source and amplifier output node, respectiely.

7 Inerting Amplifier:Voltage Gain s is R i R o = But i s = i 2 and - = 0 (since id = = 0) i s s = R and A = o s = R 2 R The negatie oltage gain implies that there is a 80 0 phase shift between both dc and sinusoidal input and output signals. The gain magnitude can be greater than if R 2 > R The gain magnitude can be less than if R > R 2 The inerting input of the op amp is at ground potential (although it is not connected directly to ground) and is said to be at irtual ground.

8 Inerting Amplifier: Input and Output Resistances R out is found by applying a test current (or oltage) source to the amplifier output and determining the oltage (or current) after turning off all independent sources. Hence, s = 0 x = i R + i R 2 2 R in = s i s = R since =0 But i =i 2 x = i ( R + R ) 2 Since - = 0, i =0. Therefore x = 0 irrespectie of the alue of i x. R out =0

9 Inerting Amplifier: Example Problem: Design an inerting amplifier Gien Data: A = 20 db, R in = 20kΩ, Assumptions: Ideal op amp Analysis: Input resistance is controlled by R and oltage gain is set by R 2 / R. A db = 20log A 0, A =0 40dB/20dB =00 A minus sign is added since the amplifier is inerting. R = R = 20kΩ in A = R 2 R R 2 =00R = 2MΩ and A = -00

10 The Non-inerting Amplifier: Configuration The input signal is applied to the non-inerting input terminal. A portion of the output signal is fed back to the negatie input terminal. Analysis is done by relating the oltage at to input oltage s and output oltage o.

11 Non-inerting Amplifier: Voltage Gain, Input Resistance and Output Resistance Since i - =0 But id =0 and = R o s = R + R id 2 s = R + R 2 o = s R o R + R R A 2 2 = = = + R s R Since i + =0 R = s = in i + R out is found by applying a test current source to the amplifier output after setting s = 0. It is identical to the output resistance of the inerting amplifier i.e. R out = 0.

12 Non-inerting Amplifier: Example Problem: Determine the output oltage and current for the gien noninerting amplifier. Gien Data: R = 3kΩ, R 2 = 43kΩ, s = +0. V Assumptions: Ideal op amp Analysis: A =+ R 2 R =+ 43kΩ 3kΩ =5.3 o = A s =(5.3)(0.V)=.53V Since i - =0, i o.53v o = = = 33.3µ A R + R 2 43kΩ+ 3kΩ

13 Finite Open-loop Gain and Gain Error o = A = A( ) = id s A A = o = s + Aβ Aβ is called loop gain. For Aβ >>, A( s β o ) R = o = β o R + R 2 R β = is called the R + R 2 feedback factor. A β =+ R 2 R This is the ideal oltage gain of the amplifier. If Aβ is not >>, there will be Gain Error.

14 Gain Error is gien by Gain Error GE = (ideal gain) - (actual gain) For the non-inerting amplifier, GE = A = β + Aβ β(+ Aβ) Gain error is also expressed as a fractional or percentage error. FGE = β A + Aβ = + Aβ Aβ β PGE Aβ 00%

15 Gain Error: Example Problem: Find ideal and actual gain and gain error in percent Gien data: Closed-loop gain of 00,000, open-loop gain of,000,000. Approach: The amplifier is designed to gie ideal gain and deiations from the ideal case hae to be determined. Hence, β =. 0 5 Note: R and R 2 aren t designed to compensate for the finite open-loop gain of the amplifier. Analysis: A = A + Aβ = 06 =9.09x PGE= x %=9.09%

16 Output Voltage and Current Limits Practical op amps hae limited output oltage and current ranges. Voltage: Usually limited to a few olts less than power supply span. Current: Limited by additional circuits (to limit power dissipation or protect against accidental short circuits). The current limit is frequently specified in terms of the minimum load resistance that the amplifier can drie with a gien output oltage swing. Eg: i o = 5V 500Ω =0mA i o o o = i + i = + = L F R R + R L 2 R EQ = R L ( R + R ) 2 For the inerting amplifier, R = R EQ L R 2 o R EQ

17 Example PSpice Simulations of Non-inerting Amplifier Circuits

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22 The Unity-gain Amplifier or Buffer This is a special case of the non-inerting amplifier, which is also called a oltage follower, with infinite R and zero R 2. Hence A =. It proides an excellent impedance-leel transformation while maintaining the signal oltage leel. The ideal buffer does not require any input current and can drie any desired load resistance without loss of signal oltage. Such a buffer is used in many sensor and data acquisition system applications.

23 The Summing Amplifier Since i - =0, i 3 = i + i 2, o = R 3 R R 3 R 2 2 Since the negatie amplifier input is at irtual ground, i = i = 2 o R 2 R i = 2 3 R 3 Scale factors for the 2 inputs can be independently adjusted by the proper choice of R 2 and R. Any number of inputs can be connected to a summing junction through extra resistors. This circuit can be used as a simple digital-to-analog conerter. This will be illustrated in more detail, later.

24 The Difference Amplifier o = - i R = - i R R R + R - 2 = ( -) = 2 R R R Also, + = 2 R +R R 2 R Since - = + 2 o = R ( ) R 2 For R 2 = R o ( ) 2 This circuit is also called a differential amplifier, since it amplifies the difference between the input signals. R in2 is series combination of R and R 2 because i + is zero. For 2 =0, R in = R, as the circuit reduces to an inerting amplifier. For general case, i is a function of both and 2.

25 Difference Amplifier: Example Problem: Determine o Gien Data: R = 0kΩ, R 2 =00kΩ, =5 V, 2 =3 V Assumptions: Ideal op amp. Hence, - = + and i - = i + = 0. Analysis: Using dc alues, A dm = R 2 R = 00kΩ 0kΩ = 0 V o = A V dm V 2 = 0(5 3) V o = 20.0 V Here A dm is called the differential mode oltage gain of the difference amplifier.

26 Finite Common-Mode Rejection Ratio A real amplifier responds to signal common to both inputs, called the common-mode input oltage ( ic ). In general, + o = A ( )+ A 2 dm 2 cm 2 o = A ( )+ A dm id cm ( ic ) (CMRR) A(or A dm ) = differential-mode gain A cm = common-mode gain id = differential-mode input oltage ic = common-mode input oltage = + id = id ic 2 2 ic 2 An ideal amplifier has A cm = 0, but for a real amplifier, o = A + A cm ic dm id A dm = A + ic dm id CMRR CMRR= A dm A cm and CMRR(dB)= 20log 0 (CMRR)

27 Finite Common-Mode Rejection Ratio: Example Problem: Find output oltage error introduced by finite CMRR. Gien Data: A dm = 2500, CMRR = 80 db, = 5.00 V, 2 = V Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in db of 80 db corresponds to a CMRR of 0 4. Analysis: =5.00V 4.999V id ic = 5.00V+4.999V =5.000V 2 o = A + ic dm id CMRR = V =6.25V In the "ideal" case, o = A =5.00 V dm id % output error= %= 25% 5.00 The output error introduced by finite CMRR is 25% of the expected ideal output.

28 ua74 CMRR Test: Differential Gain

29 Differential Gain A dm = 5 V/5 mv = 000

30 ua74 CMRR Test: Common Mode Gain

31 Common Mode Gain A cm = 60 mv/5 V =.032

32 CMRR Calculation for ua74 CMRR= A dm = 000 A cm.032 = 3.25x04 CMRR(dB)= 20log 0 ( CMRR)= 89.9 db

33 Instrumentation Amplifier Combines 2 non-inerting amplifiers with the difference amplifier to proide higher gain and higher input resistance. ) b ( a 3 4 o = R R b 2 i ) i(2 2 i a = R R R 2 2 i R = ) 2 ( = R R R R o Ideal input resistance is infinite because input current to both op amps is zero. The CMRR is determined only by Op Amp 3. NOTE

34 Instrumentation Amplifier: Example Problem: Determine V o Gien Data: R = 5 kω, R 2 = 50 kω, R 3 = 5 kω, R 4 = 30 kω V = 2.5 V, V 2 = 2.25 V Assumptions: Ideal op amp. Hence, - = + and i - = i + = 0. Analysis: Using dc alues, A = R 4 + R 2 = 30kΩ dm R R 5kΩ +50kΩ 5kΩ = 22 3 V o = A (V V )= 22( )= 5.50V dm 2

35 The Actie Low-pass Filter Use a phasor approach to gain analysis of this inerting amplifier. Let s = jω. A = o (jω) ( jω) = Z 2 ( jω ) Z ( jω ) Z 2 ( jω)= R 2 jωc R 2 + jωc = R 2 jωcr 2 + A = R 2 R (+ jωcr 2 ) = R 2 R Z jω ( )= R e jπ (+ jω ω c ) ω c =2πf c = R 2 C f c = 2πR 2 C f c is called the high frequency cutoff of the low-pass filter.

36 Actie Low-pass Filter (continued) A = R 2 R e jπ (+ jω ) ω c = R 2 R 2 + ω ω c 2 e jπ e jtan (ω/ω c ) At frequencies below f c (f H in the figure), the amplifier is an inerting amplifier with gain set by the ratio of resistors R 2 and R. At frequencies aboe f c, the amplifier response rolls off at -20dB/decade. Notice that cutoff frequency and gain can be independently set. = R 2 R + ω ω c 2 e j[π tan (ω/ω c )] magnitude phase

37 Actie Low-pass Filter: Example Problem: Design an actie low-pass filter Gien Data: A = 40 db, R in = 5 kω, f H = 2 khz Assumptions: Ideal op amp, specified gain represents the desired lowfrequency gain. Analysis: A 40dB/20dB =0 = 00 Input resistance is controlled by R and oltage gain is set by R 2 / R. The cutoff frequency is then set by C. R = R = 5kΩ A in and = R 2 R =00R =500kΩ R 2 C = 2πf H R 2 = 2π(2kHz)(500kΩ) =59pF The closest standard capacitor alue of 60 pf lowers cutoff frequency to.99 khz.

38 Low-pass Filter Example PSpice Simulation

39 Output Voltage Amplitude in db

40 Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)

41 Cascaded Amplifiers Connecting seeral amplifiers in cascade (output of one stage connected to the input of the next) can meet design specifications not met by a single amplifier. Each amplifer stage is built using an op amp with parameters A, R id, R o, called open loop parameters, that describe the op amp with no external elements. A, R in, R out are closed loop parameters that can be used to describe each closed-loop op amp stage with its feedback network, as well as the oerall composite (cascaded) amplifier.

42 Two-port Model for a 3-stage Cascade Amplifier Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-port model. R R o = A inb A s A inc A R +R B R + R C outa inb outb inc Since R A = o out = 0 = A A A A B C s R in = R ina and R out = R outc = 0

43 A Problem: Voltage Follower Closed Loop Gain Error due to A and CMRR id = s o ic = s + o 2 ( ) o = A ( s o )+ s + o 2(CMRR) A = o s = A+ 2(CMRR) + A 2(CMRR) The ideal gain for the oltage follower is unity. The gain error here is: A GE= A = CMRR + A 2(CMRR) Since, both A and CMRR are normally >>, GE A CMRR Since A ~ 0 6 and CMRR ~ 0 4 at low to moderate frequency, the gain error is quite small and is, in fact, usually negligible.

44 Inerted R-2R Ladder DAC A ery common DAC circuit architecture with good precision. Currents in the ladder and the reference source are independent of digital input. This contributes to good conersion precision. Complementary currents are aailable at the output of inerted ladder. The bit switches need to hae ery low on-resistance to minimize conersion errors.

45 Successie Approximation ADC Binary search is used by the SAL to determine X. n-bit conersion needs n clock periods. Speed is limited by the time taken by the DAC output to settle within a fraction of an LSB of V FS, and by the comparator to respond to input signals differing by small amounts. Slowly arying input signals, not changing by more than 0.5 LSB (V FS /2 n+ ) during the conersion time (T T = nt C ) are acceptable. For a sinusoidal input signal with p-p amplitude = V FS, f f o c 2 n+2 (n+)π To aoid this frequency limitation, a high speed sample-and-hold circuit is used ahead of the successie approximation ADC. This is a ery popular ADC with fast conersion times, used in 8- to 6- bit conerters.

46 SAADC: Block Diagram

47 SAADC: Method of Operation

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