LOW-VOLUME STACKABLE FLYBACK CONVERTER

Transcription

1 LOW-OLUME STACKABLE FLYBACK CONERTER WITH NEAR MINIMUM DEIATION CONTROLLER Aleksandar Radić, Adrian Straka and Aleksandar Prodić Laboratory for Power Management and Integrated Switch-Mode Power Supplies ECE Department, Uniersity of Toronto, Toronto, CANADA Abstract This paper introduces a flyback-based low-olume modular conerter and complementary mixed-signal controller that proide input oltage and put current sharing as well as near optimal transient response. This serial-input parallelput switch-mode power supply (SMPS) is well suited for high-step down ratio applications where, compared to a conentionally used multi-phase buck, it requires a smaller put filter olume, lower MOSFET blocking oltages, and proides better dynamic response. The stackable flyback also has better power processing efficiency and proides inherent passie current sharing. These adantages are achieed by utilizing low-oltage flyback cells and a noel implementation of minimum deiation control method. Experiments with a -to--, 4-A, 500kHz -cell stacked flyback conerter prototype show that, compared to an equialent - -phase conentional buck with approximately the same inductor olume, the introduced conerter has 4% smaller put capacitor, up to 40% lower power losses, and 33% faster transient response. the conentional buck, the SC conerters utilize lower-oltage switches, smaller reactie components and proide improed efficiency oer a certain conersion range. Howeer, the absence of the inductor that stores energy during oltage and ariations [5] affects power processing efficiency and put oltage regulation. The MLB achiees miniaturization of its put reactie components with the introduction of a oltage attenuating capacitor [3, 4] minimizing inductor oltage swing and components stress. Howeer, those solutions require larger number of switches and high side gate driers making their integration challenging. The main goal of this paper is to introduce stacked flyback conerter with near minimum deiation controller of Fig. that, compared to the conentional multi-phase buck solutions, I. INTRODUCTION The miniaturization of switch-mode power supplies (SMPS) is of a key importance for olume and price-sensitie electronic applications. In these applications, to reduce a relatiely high internal bus oltage to low oltage leels, required by digital processors, multi-phase buck conerters with a limited controller bandwidth [] are usually used. The multi-phase buck solutions proide effectie oltage regulation but, at the same time, their reactie components take a significant amount of the oerall deice olume and printed circuit board (PCB) area. To minimize the olume of the reactie components a number of solutions hae been proposed []-[4] as alternaties to the conentional multi-phase buck. Arguably, among the most interesting are the switched capacitor (SC) [] and the multi-leel buck (MLB) based solutions [3, 4]. Compared to This work of the Laboratory for Power Management and Integrated Switch-Mode Power Supplies is sponsored by Texas Instruments Inc., Dallas, Texas, United States. Figure. Low oltage stacked flyback conerter and complementary minimum deiation controller /4/$ IEEE 948

2 has smaller put filter olume and achiees better processing efficiency with suffering from the drawbacks existing in SC and MLB solutions. This modular conerter structure also proides better transient response and inherent passie current sharing eliminating the need for phase currents measurements and balancing circuits. II. PRINCIPLE OF OPERATION In the conerter of Fig. the input filter capacitor, ineitably existing in the targeted applications, is replaced with a capacitie diider and the inputs of flyback cells are connected to each of the diider taps, such that the oltage between the cells is shared. The puts of the flyback cells are connected in parallel allowing put current sharing. A two-mode digital controller goerns the operation of all modules. During steady state, the system operates as an interleaed oltage mode controlled system where a single multi-phase digital pulse width modulator (DPWM) [6] produces control signals c (t) to c k (t) for the cells. The duty ratios of the signals are identical and determined based on the DPWM input control d[n], which is calculated by the PID once per switching cycle, using the digital put error oltage alue, e[n]. During transients the controller enters transient suppression mode to quickly recoer from the disturbance. A. olume Reduction The olume reduction adantages of the stacked conerter oer the multi-phase buck conerter can be determined through analysis of the effect of the number of modules on each indiidual conerter. For the multi-phase buck, addition of each module results in lower current stress of the components. On the other hand, for the stacked flyback an increase in the number of modules has a three-fold effect. It reduces both the oltage and current stress of components and, in addition, minimizes the inductor oltage swing, allowing for the use of smaller inductance alues [3, 4]. In fact, for a sufficiently large number of modules the flyback conerter based topology will be smaller and more efficient than the conentional buck. Quantitatiely, the effect of the inductor oltage swing reduction on the conerter olume can be described by analyzing the expression for the flyback magnetizing inductance alue [7]: where is the put oltage, f sw is the switching frequency, k is the number of flyback cells, and i Lm is the ripple amplitude. It can be seen that as the number of modules increase the inductor alue reduces. This reduction in the inductance alue, in turn, also allows for the minimization of the put capacitor, whose size in the targeted application depends on the transient performance. This is because, as shown in the following section, the ratio of the maximum oltage deiations of the buck and the stacked flyback under optimal, i.e. fastest possible, control is directly proportional to the ratio of their inductance. The total reduction in the oerall conerter olume can be described with the following expressions for total minimum olume of reactie energy storage components and the diagram of Fig. showing the olume ratios of an interleaed buck and the stacked flyback modules: fb buck L m L i kd' i k (+ k = ρl + C ρ + L fb g buck g 3 ) k k C g ρ, () C ρ, (3) C >>k (4) L m = k + g i Lm f sw, () Figure. olume as a function of input-to-put oltage conersion ratio and number of phases. 949

3 where, fb is the olume of a flyback module, buck is olume of the buck module, while, ρ L and ρ C are the inductor and capacitor energy density alues, respectiely. The results in Fig. obtained for typical reactie component energy density alues [8], show that for step down ratios larger than eight, the two-module flyback structure already results in a smaller olume than that of the conentional buck. inm g = k R + k R R eq + k R eqm a, (5) B. Inherent Current Sharing and Tap oltage Sharing In conentional multi-phase dc-dc conerters current sharing is often required to proide equal current or thermal stress across all phases [9]. The practical implementation of the current sharing systems often requires costly dedicated circuits for sensing or estimation of phase currents and an additional control loop for regulating the process. The stacked flyback proides inherent current sharing eliminating the need for a dedicated circuit. To explain this feature of the conerter, its dc aeraged model of Fig.3 can be obsered. In this model switching and conduction losses of indiidual phases are modeled with their secondary side equialent resistances Req. Analysis of this equialent circuit reeals two important inherent characteristics of the stacked-flyback: equal current and tight input oltage sharing. By looking at the model it can be seen that, all the current sources on the primary side are connected in series and, therefore, they must hae the same input current independent on the phase ariations. Consequently, for the identical duty ratios, the secondary side phase currents, labeled as I to I k are the same. By soling the circuit of Fig.3 for the tap oltages, i.e. oltages across dependent current sources [7], it can be found that inm, i.e. the oltage across the m th the tap is: Figure 3. Equialent dc circuit model of the stacked flyback conerter with k flyback cells. where R eq_a is the aerage lumped-sum equialent resistance, and R is the put resistance. This expression shows that, for a properly designed conerter, where R >> R eq equal oltage sharing among the capacitor taps is practically achieed III. NEAR OPTIMUM DEIATION CONTROLLER One of the main drawbacks of conentionally controlled flyback conerters is relatiely slow transient response, mostly caused by the conentional compensator design and the presence of the right half plane zero. To eliminate this problem and allow the stackable flyback to be used in the targeted applications, where the transient response of the controller is of a key importance, a near-minimum deiation controller is deeloped. This controller utilizes a modification of the minimum deiation control method, presented in [0, ] where, for a gien conerter topology, the controller suppresses transients with minimum possible put oltage deiation using ery simple hardware and requiring no knowledge of conerter parameters. In this two-step method, as soon as a disturbance is detected, the controller enters the transient suppression mode. During this mode the new steady state alues of the inductor current and its ripple are reconstructed oer one switching cycle. As a result the effect of the transient on the put oltage is reersed and the deiation limited to its minimum possible alue. After the current reconstruction is completed the control task is passed to a conentional PID regulator recoering oltage to its reference alue. In this case, to simplify the controller implementation and allow only secondary side control, the optimum deiation method is modified and the current reconstruction is performed oer seeral cycles, by monitoring polarity of the put capacitor current. Still, as it will be shown later, the transient performance of this system are better than that of the optimum-deiation controlled buck. A. Light-to-Heay Transient During light-to-heay transients the recoery is performed through a simple repetitie charge and check based procedure. This procedure can be explained with the help of diagrams shown in Figs. 4 and 5. For simplicity, the diagrams are shown 950

4 Figure 4. Finite state machine for light-to-heay and heay-to-light transients. for a -module case. As soon as the transient is detected, at t = t 0, the main switches of the flyback cells are turned on oer t on =DT sw period (labelled c in Fig. 5) and the inductor current is ramped up. At the end of the charging period, the MS transistors are turned off (SRs turned on) and the coupled inductors are discharged into the put node (labelled d in Fig. 5). During the discharging phase the polarity of the capacitor current is monitored by the controller. If a negatie current is detected within a time period equal to t min, the inductor charging mode (c) is reactiated. The charging and discharging procedure is repeated until a positie capacitie current alue is detected. This only occurs when the inductor current is larger than that of the, i.e. sufficiently high to reerse capacitor discharge and start the oltage recoery process. At that point the PID compensator is reactiated and the oltage is recoered to its reference alue in a monotonic fashion. B. Heay-to-Light Transient During heay-to-light transients the transient suppression logic operates as a non-modified minimum deiation controller [0]. After a transient is detected, at t=t, the SRs are turned on and the coupled inductors discharged into the put capacitor until the zero capacitor current crossing is detected. At that point initial alues of the duty ratios are reset, as described in [9], and the PID is reactiated. Figure 5. Main current and oltage waeforms during light-to-heay and heay-to-light transients. 95

5 Figure 6. Response to a 0.5-A.5-A 0.5-A step of the stacked flyback cell (left) and buck conerter phase (right). Ch.: Output oltage (t), 0m/di; Ch. : Inductor current i L(t), A/di; The time scale is 5µs/di for both waeforms. I. EXPERIMENTAL RESULTS To erify the conerter and controller an experimental prototype of a stackable flyback is created based on Figs., 4 and 5. The performances of this conerter are compared to that of a conentional buck. The prototype is designed to operate with or 3 cells. Each cell was designed for A maximum put current, 6 input oltage, -.5 put oltage and 500 khz switching frequency. The power stages are formed of discrete components, while the controller is based on a field-programmable gate array system (FPGA) and discrete components. The zero current detection circuit has self-tuning capability and utilizes simple design shown in []. The power stages also include actie snubber circuits [3]. The flyback inductors with : turns ratio hae magnetizing inductances of 3.3 µh [4]. The put capacitor alue of 40 µf is selected, ensuring less than 00 m oltage deiation during the worst case transient. Using the principles lined in subsection II.A, the buck conerter reactie components are selected such that the olume of the reactie components, related to the Li and C products, and inductor current ripple are the same for both conerters. The inductor size for such an optimization is 4.7 µh, assuming k =, the put capacitor 40 µf and the switching frequency 390 khz. In Fig. 6, the responses to a 0.5-A.5-A 0.5-A step (per cell) for a --to-- two-cell stacked flyback experimental prototype and two-phase buck conerter are compared. From Fig. 6 it can be seen that a 4% smaller oltage deiation and 33% shorter settling can be achieed with the stacked flyback, while utilizing a similar olume inductors. The improed put oltage deiation enables a similar reduction of the put capacitor size. Figure 7 plots the power processing efficiency (left) of the Figure 7. Power processing efficiency (left) the //3 Cell stacked flyback and -phase buck conerter prototypes and input capacitor oltages (right) of the stacked flyback conerter with respect to the put current. 95

6 stacked flyback and buck conerter experimental prototypes and the input capacitor oltage sharing (right) of the stacked flyback conerter. Compared to the -phase buck conerter, the -cell stacked flyback deliers up to 6.5% better power processing efficiency, i.e. 40% lower power losses. These results can allow for a further increase in switching frequency and thus an additional reduction of the inductor olume for the stacked flyback. Furthermore, tight passie input oltage sharing is maintained across the entire range of put leels, within 6% of the nominal alues. Also, near-linear efficiency scaling is obsered with respect to the number of cells.. CONCLUSIONS The paper introduced a modular solution for high step down conersion ratio applications that combines a stacked flyback conerter and noel near optimal deiation controller. For high step down ratios and relatiely small number of modules this topology requires smaller olume of reactie components than an equialent multi-phase buck and results in better power processing efficiency. This is due to three-fold effect of modularization that at the same time causes current sharing, oltage stress reduction, and inductor alue minimization. The near optimum deiation controller eliminates slow dynamic response problem characteristic for conentional flyback solutions and proides smaller oltage deiation than that of an optimally controlled buck. DC-DC conersion technologies," Control and Modeling for Power Electronics (COMPEL), 00 IEEE th Workshop on, ol., no., pp.-7, 8-30 June 00. [9] Z. Lukić, Design and Practical Implementation of Adanced Reconfigurable Digital Controllers for Low-Power Multi-Phase DC-DC Conerters. PhD thesis, Uniersity of Toronto, Canada, 0. [0] A. Radić, Z. Lukić, A. Prodić, and R. de Nie, "Minimum Deiation Digital Controller IC for DC-DC Switch-Mode Power Supplies," Power Electronics, IEEE Transactions on, ol.8, no.9, pp , Sept 03. [] M.M. Peretz, Hybrid Control Method for Optimal Transient Response and Output Filter Minimization for Buck-Boost type Conerters, PCIM- 03 Nuremberg, pp , May 03. [] A. Radić, D. Baik, A. Straka, A. Prodić, and R. de Nie, "Noninasie self-tuning put capacitor time constant estimator for low power digitally controlled dc-dc conerters," Applied Power Electronics Conference and Exposition (APEC), 03 Twenty-Fifth Annual IEEE, pp , 7- Mar. 03. [3] R. Watson, F.C. Lee, and G.-C. Hua, "Utilization of an actie-clamp circuit to achiee soft switching in flyback conerters," Power Electronics, IEEE Transactions on, ol., no., pp.6-69, Jan 996 [4] LPD MEB 3.3 µh Coupled Inductor Datasheet, Coilcraft Inc., Cary, IL, 06/03. REFERENCES [] oltage Regulator Module (RM) and Enterprise oltage Regulator- Down (ERD). Design Guidelines, Intel Corporation, Santa Clara, CA, Sept 009. []. W. Ng, M. D. Seeman, and S. R. Sanders, Minimum PCB footprint point-of- DC DC conerter realized with switched-capacitor architecture, in Proc. IEEE Energy Coners. Congr. Expo., pp , Feb [3] R. C. N. Pilawa-Podgurski, D. M. Giuliano, and D. J. Perreault, Merged two-stage power conerter architecture with soft charging switched capacitor energy transfer, in Proc. IEEE Power Electron. Spec. Conf., pp , Jun [4] T.A. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob, and M. Nahrstaedt, "Multicell conerters: basic concepts and industry applications," Industrial Electronics, IEEE Transactions on, ol.49, no.5, pp , Oct 00. [5] M. Shoyama, T. Naka, and T. Ninomiya, Resonant switched capacitor conerter with high efficiency, in Proc. IEEE Power Electron. Spec. Conf., pp , Jun [6] A.. Peterche, Jinwen Xiao, and S.R. Sanders, "Architecture and IC Implementation of a Digital RM Controller", IEEE Transactions on Power Electronics, ol. 8, no., pt., pp , Jan, 003. [7] R. W. Erickson and D. Maksimoić, Fundamentals of Power Electronics. New York, NY:Springer Sience+Business Media Inc., 00. [8] M.D. Seeman,.W. Ng, Le Hanh-Phuc, M. John, E. Alon, and S.R. Sanders, "A comparatie analysis of Switched-Capacitor and inductor-based 953