Chapter 5 Bipolar Amplifiers. EE105 - Spring 2007 Microelectronic Devices and Circuits. Bipolar Amplifiers. Voltage Amplifier

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1 EE05 - Spring 2007 Microelectronic Deices and ircuits hapter 5 Bipolar mplifiers 5. General onsiderations 5.2 Operating Point nalysis and Design 5.3 Bipolar mplifier Topologies 5.4 Summary and dditional Examples Lecture Bipolar mplifiers (Part ) 2 Bipolar mplifiers Voltage mplifier 3 In an ideal oltage amplifier, the input impedance is infinite and the put impedance zero. But in reality, input or put impedances depart from their ideal alues. 4

2 Input/Output Impedances Input Impedance Example I x V i The figure aboe shows the techniques of measuring input and put impedances. x x i x x r π When calculating input/put impedance, small-signal analysis is assumed. 5 6 Impedance at a Node Impedance at ollector r o When calculating I/O impedances at a port, we usually ground one terminal while applying the test source to the other terminal of interest. 7 With Early effect, the impedance seen at the collector is equal to the intrinsic put impedance of the transistor (if emitter is grounded). 8

3 Impedance at Emitter Three Master ules of Transistor Impedances x i x gm + r gm ( V ) The impedance seen at the emitter of a transistor is approximately equal to one oer its transconductance (if the base is grounded). π 9 ule # : looking into the base, the impedance is r π if emitter is (ac) grounded. ule # 2: looking into the collector, the impedance is r o if emitter is (ac) grounded. ule # 3: looking into the emitter, the impedance is /g m if base is (ac) grounded and Early effect is neglected. 0 Biasing of BJT D nalysis s. Small-Signal nalysis Transistors and circuits must be biased because () transistors must operate in the actie region, (2) their small-signal parameters depend on the bias conditions. First, D analysis is performed to determine operating point and obtain small-signal parameters. Second, sources are set to zero and small-signal model is used. 2

4 Notation Simplification Example of Bad Biasing Hereafter, the battery that supplies power to the circuit is replaced by a horizontal bar labeled V cc, and input signal is simplified as one node called V in. 3 The microphone is connected to the amplifier in an attempt to amplify the small put signal of the microphone. Unfortunately, there s no D bias current running through the transistor to set the transconductance. 4 nother Example of Bad Biasing Biasing with Base esistor I I B V VBE B V V β BE B The base of the amplifier is connected to V cc, trying to establish a D bias. Unfortunately, the put signal produced by the microphone is shorted to the power supply. 5 ssuming a constant alue for V BE, one can sole for both I B and I and determine the terminal oltages of the transistor. Howeer, bias point is sensitie to β ariations. 6

5 Improed Biasing: esistie Diider ccounting for Base urrent V I V S exp( ) + 2 VT Using resistor diider to set V BE, it is possible to produce an I that is relatiely independent of β if base current is small. X I V 7 With proper ratio of and 2, I can be insensitie to β; howeer, its exponential dependence on resistor deiations makes it less useful. I VThe IB The IS exp VT 8 Emitter Degeneration Biasing Design Procedure hoose an I to proide the necessary small signal parameters, g m, r π, etc. onsidering the ariations of, 2, and V BE, choose a alue for V E. With V E chosen, and V BE calculated, V x can be determined. The presence of E helps to absorb the error in V X so V BE stays relatiely constant. This bias technique is less sensitie to β (I >> I B ) and V BE ariations. 9 Select and 2 to proide V x 20

6 Self-Biasing Technique Self-Biasing Design Guidelines () (2) B >> β Δ V << V V BE BE This bias technique utilizes the collector oltage to proide the necessary V x and I B. One important characteristic of this technique is that collector has a higher potential than the base, thus guaranteeing actie operation of the transistor. 2 () proides insensitiity to β. (2) proides insensitiity to ariation in V BE. 22 Summary of Biasing Techniques PNP Biasing Techniques Same principles that apply to NPN biasing also apply to PNP biasing with only polarity modifications

7 Possible Bipolar mplifier Topologies Study of ommon-emitter Topology nalysis of E ore Inclusion of Early Effect Emitter Degeneration Inclusion of Early Effect E Stage with Biasing Three possible ways to apply an input to an amplifier and three possible ways to sense its put. Howeer, in reality only three of six input/put combinations are useful ommon-emitter Topology Small Signal of E mplifier 27 in g m π m in g m g 28

8 Limitation on E Voltage Gain Tradeoff between Voltage Gain and Headroom I VT V VT V V < V T BE Since g m can be written as I /V T, the E oltage gain can be written as the ratio of V and V T. V is the potential difference between V and V E, and V E cannot go below V BE in order for the transistor to be in actie region I/O Impedances of E Stage E Stage Trade-offs in X X rπ i i X X When measuring put impedance, the input port has to be grounded so that V in

9 Inclusion of Early Effect Intrinsic Gain g r V V T m O gm( ro) r O Early effect will lower the gain of the E amplifier, as it appears in parallel with. 33 s goes to infinity, the oltage gain reaches the product of g m and r O, which represents the maximum oltage gain the amplifier can hae. The intrinsic gain is independent of the bias current. 34 urrent Gain Emitter Degeneration I i iin β I E nother parameter of the amplifier is the current gain, which is defined as the ratio of current deliered to the load to the current flowing into the input. For a E stage, it is equal to β. 35 By inserting a resistor in series with the emitter, we degenerate the E stage. This topology will decrease the gain of the amplifier but improe other aspects, such as linearity, and input impedance. 36

10 Small-Signal Model Emitter Degeneration Example I gm + g m E + g Interestingly, this gain is equal to the total load resistance to ground diided by /g m plus the total resistance placed in series with the emitter. m E 37 g The input impedance of Q 2 can be combined in parallel with E to yield an equialent impedance that degenerates Q. m + E r π 2 38 Emitter Degeneration Example II Input Impedance of Degenerated E Stage g In this example, the input impedance of Q 2 can be combined in parallel with to yield an equialent collector impedance to ground. m r π 2 + E 39 V X rπ ix + E( + β ) ix X in rπ + ( β + ) i X With emitter degeneration, the input impedance is increased from r π to r π + (β+) E ; a desirable effect. E 40

11 Output Impedance of Degenerated E Stage apacitor at Emitter V π 0 π + + g π rπ π 0 X i in m E X Emitter degeneration does not alter the put impedance in this case. (More on this later.) 4 t D the capacitor is open and the current source biases the amplifier. For ac signals, the capacitor is short and the amplifier is degenerated by E. 42 Example: Design E Stage with Degeneration as a Black Box Degenerated E Stage with Base esistance V in i gm + ( rπ + gm) i gm Gm + g in m E If g m E is much greater than unity, G m is more linear. E 43 V. in in β rπ + ( β + ) + B + E + g β + in E B m 44

12 Input/Output Impedances Emitter Degeneration Example III V in rπ + ( β + ) E + r + ( β + ) in2 B π E in is more important in practice as B is often the put impedance of the preious stage. ( ) B gm β + in r π + ( β + ) Output Impedance of Degenerated Stage with Finite V Two Special ases [ ] + gm( E rπ ) ro + E r ro + ( gmro + )( E rπ ) r + g r [ ( )] O m E Emitter degeneration boosts the put impedance by a factor of +g m ( E r π ). This improes the gain of the amplifier and makes the circuit a better current source. π π 47 () (2) E >> rπ r ( + g r ) βr O m π O E << rπ ( + g ) r m E O 48

13 nalysis by Inspection Example: Degeneration by nother Transistor [ + g m ( r ] r 2 O ) π [ + g ( r )] r m 2 π O This seemingly complicated circuit can be greatly simplified by first recognizing that the capacitor creates an short to ground, and gradually transforming the circuit to a known topology. 49 [ ( )] + g r r r m O2 π O alled a cascode, the circuit offers many adantages that are described later in the book. 50 Bad Input onnection Use of oupling apacitor Since the microphone has a ery low resistance that connects from the base of Q to ground, it attenuates the base oltage and renders Q with a bias current. 5 apacitor isolates the bias network from the microphone at D but shorts the microphone to the amplifier at higher frequencies. 52

14 D and nalysis Bad Output onnection gm( ro) in rπ B r O oupling capacitor is open for D calculations and shorted for calculations. 53 Since the speaker has an inductor, connecting it directly to the amplifier would short the collector at D and therefore push the transistor into deep saturation. 54 Still No Gain!!! E Stage with Biasing In this example, the coupling indeed allows correct biasing. Howeer, due to the speaker s small input impedance, the oerall gain drops considerably. gm( ro) in rπ 2 r O 55 56

15 E Stage with obust Biasing emoal of Degeneration for Signals at V gm in r π 2 + E gm in r + + [ π ( β ) E ] 2 apacitor shorts E at higher frequencies and remoes degeneration omplete E Stage Summary of E oncepts L s 2 + E + g β + m 59 60