Experiment #12 BJT Differential Pairs
|
|
- Abraham Hamilton
- 5 years ago
- Views:
Transcription
1 Introduction: Experiment #1 BJT Differential Pairs Jonathan Roderick differential pair is a four port network that is shown in figure 1.1. These ports are labeled through D. However, a differential pair is nothing more than two identical amplifiers that are combined in a symmetric way to achieve a desired performance. lthough the first draw back to using a differential pair is that it requires the use of two amplifiers which doubles the power consumption. If power consumption is not a critical issue, it will be shown that the differential pair has other benefits that outweigh the increased power consumption. These benefits make the differential pair an established topology in the analog circuit design. This lab will present the basic differential pair, then it will show how to analyze a balanced differential pair through a technique called the half-circuit analysis. R S S1 R S B Differential mplifier C D o - L 01 DO + S Figure 1.1 Differential mplifier. This lab must use matched transistors for the differential pair. If matched devices on-chip are not readily available then in must be completed entirely in spice. Theory: It was mentioned above that differential pairs are nothing more than two amplifiers connected together. In figure 1. a schematic is shown of a typical differentia l pair. The amplifiers, depicted by the triangles, are ideal. The discussion that follows will not worry about the logistics of the amplifiers themselves. s it will be seen, the performance of the differential amplifier depends more on the topology in which the two amplifiers are connected, rather than the amplifiers themselves, assuming the amplifiers work relatively close to ideal and are identical. To prove this point, later on in the lab, the amplifiers symbols will be replace by simple common-emitter amplifiers.
2 R S mp #1 S1 R EE R K R EE R S mp # O L O1 S _ DO + Figure 1. differential pair configuration. In figure 1., the two sources, S1 and S, comprise of both signal and biasing. The differential amplifier, like everything else in science, receives its name from its performance. well-designed differential amplifier rejects signals that are common to both inputs and amplifies signals that are uncorrelated. The standard of measurement of how well a differential pair amplifies differential signals and rejects common signals is called the common mode rejection ratio (CMRR). The CMRR is calculated as follows CMRR diff com (1.1) Where diff is the differential gain and com is the common gain. Why is this important? good way to eliminate nois e from a system is to use a differential pair. If your differential pair topology is symmetric, then inherent electrical noise will be a common signal at both inputs. Thus, it is possible to cleanup your signal using a differential pair. nother example is the temperature dependence of devices. Ideally biasing is stable, but in real world applications the bias fluctuates with temperature. In a regular common-emitter amplifier, this change in bias also gets amplified. This is very undesirable and a differential pair is one very practicable solution. Half-circuit analysis: Now that the basics have been covered, an analysis of figure 1. will be shown as an example. The halfcircuit analysis is only valid for balanced differential pairs. Balanced means that is you drew a line through the middle of the topology that you would see exactly the same thing on both sides of the line. In
3 other words, the circuit is completely symmetric. The reason behind doing the half-circuit analysis is to break down the circuit into differential and common modes, so that the CMRR can be easily calculated. The first step is doing a half-circuit analysis is to break up the input signals into differential and common parts. di is defined as the differential input and it is calculated by di S1 S (1.) ci is the common input voltage. The common input voltage is nothing more then the average. ci + d1 d (1.3) Now that the common and differential inputs have been defined, the differential output and common output voltages, do and co respectively, can be addressed. do o1 o (1.4) co + o1 o (1.5) In was mentioned that S1 and S are made up of biasing, common, and signal, differential. Using the equations above and solving for S1 and S di S1 c 1 + (1.6) S c1 di (1.7) This satisfies equation 1.. Now the signals in figure 1. can be replaced with a common and differential mode parts. This is shown in figure 1.3. Now say for argument, the common mode was zero, ci 0. Now any differential signal across the inputs is going to cause one amplifier to amplify a certain amount, while causing the other amplifier to amplify the same amount but with opposite polarity, due to the polarity difference of the differential signals at the output in figure 1.3. Think of it as a seesaw. So if amplifier #1 gets a differential signal that causes it to pull up a certain amount, than amplifier # is going be pushed down that same amount.
4 Now for the case that differential mode is set to zero. ny signal change is going to raise or lower both amplifiers by the same amount. So the common mode can be though of as the fulcrum of the seesaw. _ + di R S mp #1 R EE R K + _ ci + di R S R EE mp # 0 L _ + DO o1 Figure 1.3 Differential pair with common and differential mode inputs. The whole advantage of the half-circuit method is you will be performing an analysis on only half of the original circuit. This will make the analysis and you life much easier. Using what you observe from the half circuit, you will be able to accurately model the entire differential pair. In order to calculate the CMRR of the differential pair, half-circuit calculations must be done for both the common and differential modes. These half-circuit models will yield the gain of the differential and common modes, thus allowing for the calculation of the CMRR. Differential mode half-circuit The differential half circuit is found by first setting the common mode to zero. Next, to breakup the topology into two halves, draw a virtual line through the entire differential pair so that the circuit is broken into two symmetric sides. Whatever signal you apply into amplifier #1 results in an equal magnitude, yet opposite polarity signal applied to amplifier #, causing an equal but opposite reaction throughout the entire circuit. This equal but opposite reaction combined with Kirchoff current laws (KCL) results with every node that the virtual line crosses becoming a virtual ground. For example in figure 1.3, a voltage 1 applied to mplifier #1 is going to cause a current, I1, to be generated in R EE connected to mplifier #1. voltage 1 applied to mplifier # will cause I1 to flow in R EE connected to mplifier #. Looking at the node connecting the two R EE and R K resistors and using KCL, the current flowing through R K is zero. This creates a virtual ground at the node that connects R EE to R K.
5 In order to complete the separation of the circuit into two halves, the same thing must be done at the output. This might not seem as trivial as the last case, but it really is. Divide L into two resistors of half the value connected in series. With this modification the virtual ground is found by inspection. The following differential half-circuit shown in figure 1.4 should result. Di R Di R S R EE mplifier R Do L Do Figure 1.4 The Differential mode half-circuit equivalent circuit of figure 1.. Now that the circuit has been simplified, the differential gain, D, may be calculated from the half-circuit equivalent with the following equation. Do Di Ci 0 Do Di D (1.8) Equation 1.8 indicates that the differential gain of the half circuit is the differential gain of the entire circuit. The differential mode input and output resistance is a straight forward process and is calculated using the differential half-circuit. Notice in figure 1.4, the input and output resistance calculated from the deferential mode half circuit is equal to R Di / and R Do /, respectively. These two resistance will be needed later for the input and output resistance of the entire topology. Common mode half circuit The first step in realizing the common mode half-circuit is to set the differential part of the signal to zero in figure 1.3, Di 0. Next, breakup the topology into two halves by drawing a virtual line, just like you did for the differential mode. Now that the common mode is being modeled, the analysis is a little different. Whatever signal you apply into amplifier #1 results in an equal magnitude and polarity in mplifier #. The common mode signal causes an equal action throughout both amplifiers.
6 The task of dividing the circuit into two halves in order to perform a half-circuit analysis is a little different from differential mode case. In the differential mode all nodes that the virtual line ran through became virtual grounds, this is not the case for the common mode half circuit. Using KCL and the fact that the common mode input voltage induces the same reaction throughout the topology; one can conclude that the value of R K in figure 1.3 must be doubled in the common mode half circuit. To explain why the value of R K is doubled refer back to figure 1.3. If a common mode input used as a perturbation for both amplifiers, then the same current will flow through both R EE resistors. Depending on the polarity of the common mode input, these two equal current will either flow to or from the node that connects both R EE resistors to R K. If one wants to insure the same current that flow through R EE in the half circuit, then R K, must be doubled. The output load is treated in much the same way. Once again, to accurately model the load resistance one must remember KCL and the fact that equal symmetrically reactions occur from a common mode input. Using this as a plan of attack, one can see that the output load is simply modeled by a single resistor,, tied to ground. This is because the common mode input voltage raises and lowers the output voltages, o1 and o, the same way and at the same rate. If o1 and o are equally affected by the input, then the voltage drop across L is zero and it can be removed from the half circuit. The common mode half-circuit equivalent is show in figure 1.5. R Ci R Co mplifier o1 Co R s R EE ci R K Figure 1.5 The Common mode half-circuit equivalent circuit of figure 1.. The common mode gain, C, can be calculated using the following equation. It can be seen that the gain calculated by the common mode half circuit equal to the common-mode gain. Using what was learned in the differential mode section, the common mode rejection ratio is easily calculated using equations 1.8 and 1.9.
7 Co Ci Di C 0 (1.9) Net Input and Output resistance of Network: The net input and output resistance will be derived from a two port perspective. The input and output can be model as a two port, then the contributions from the common mode and differential mode can be used to determine the net input and output resistance of the network. The input ports labeled and B from figure 1.1 can be modeled as the two port equivalent found in figure 1.6. R XI B R XX R XX Figure 1.6 Two-port equivalent of the input port of a differential amplifier. First consider the common mode contribution to the net input resistance. This is accomplished by following the same methodology that was used to determine the common and differential mode half circuits. For the common mode, two identical signals are hooked up to ports and B as shown in figure 1.7.
8 I s1 R in R XI B R in I s1 s1 R XX R XX s1 Figure 1.7 Common mode configuration for determining input resistance. The currents I s1 and I s are established by the applied voltage sources identical voltages s1 and s. If the common mode signal are the same then the voltages established at ports and B are identical. If the voltages at ports and B are the same, then no current flows through resistor R XI. Therefore figure 1.7 reduces to figure 1.8. For this one can see that R XX R Ci (1.10) I s1 R in B R in I s1 s1 R XX R XX s1 Figure 1.8 Calculating the common mode contribution to the net input res istance. Going back to figure 1.6 it can be sent that R XI still needs to be calculated in terms of common and differential mode resistances. Before two equal voltages were introduced to ports and B, now introduce two equal but opposite signals at these same ports. If we keep to the notation used earlier for differential mode analysis, two signal in opposite polarity equal to Di / would be hooked up to ports and B. This is equivalent to connecting one voltage source equal to Di between ports and B. This is shown in figure 1.9.
9 Di B R XI R XX R XX Figure 1.9 Differential mode configuration for determining input resistance. Calculating the resistance seen by Di is straight forward as is given in equation R R R Di (1.11) XI Ci R XI can be solved for using equation 1.11 and is stated below. R XI R R Ci Ci R Di R Di (1.1) The exact same type of analysis can be done for the output resistance using nodes C and D. The two port equivalent of the output is given in figure 1.10.
10 C R XO D R Co R Co Figure 1.10 Differential pair output resistance two-port equivalent. Where R Co is the common mode output resistance found through half circuit analysis and R XO is given below in equation R XO R R Co Co R Do R Do (1.13) Differential Pair Example: differential pair circuit is shown in figure Biasing has been neglected, but it is assumed that the transistors are all in linear operation.
11 + cc + cc L R s R s Q 1 Q R ee R ee s R K - ee Figure 1.11 Differential pair example using BJTs. pplying the techniques for half-circuit analysis, the CMRR of figure 1.11 will be calculated. Calculation of the network input and output resistance will be left as a prelab exercise. Differential mode: To find the differential mode half circuit we set the common mode input in figure 1.13 to zero. If we draw a line down the middle of the topology and place a ground at all the nodes this line hits, we will end up with the half circuit shown in figure 1.1. From what was learned from experiment #6, you should be able to determine the gain of this half-circuit virtually by inspection. The differential gain is give below. D Do Di r s + r b RLL β RL + r + ( β + 1)( r + R π e ee ) (1.14)
12 L R Di D0 R s R Do Di R ee Figure 1.1 Differential half-circuit Common mode: The common mode half circuit should also be constructed using the instruction that were given earlier. The first step is to set the differential contribution of the source, in figure 1.3, to zero. The resistors in both figure 1.3 and 1.11 have been named the same to assist in the recognition of how to construct the correct half circuit. Using KCL and the fact that the common mode input voltage induces the same reaction throughout the topology; one can conclude that the value of R K must be doubled in the common mode half circuit. The reason why R K is double is to insure same current that flow through R EE in the half circuit as it did in the complete topology. Next, the output has to be taken into consideration. It can be seen that the output load is simply modeled by a single resistor,, tied to ground. This is because the common mode input voltage raises and lowers the output voltages, o1 and o, the same way and at the same rate. If o1 and o are equally affected by the input, then the voltage drop across L is zero and thus it can be removed from the half circuit. The common mode half-circuit is shown in figure From this circuit the common mode gain is found to be: C Co Ci r s + r b + r π βr L + ( β + 1)( re + Ree + RK ) (1.14)
13 R Ci C R s R Co Ci R ee R K Figure 1.13 Common mode half-circuit Now the CMRR can be easily calculated. D CMRR (1.15) C Conclusion: Differentials pairs were presented along with a technique called half-circuit analysis. Half-circuit analysis allows a circuit designer to do analysis on only half the circuit, yet use these results to model the behavior of the entire circuit. Thus eliminating half the work involved. To be sure, half circuit analysis is only beneficial and valid when doing analysis on differential pair technology that is perfectly symmetric or balanced.
14 Reference reading 1) John Choma, Jr. EE348 lecture notes. University of Southern California. Spring 001.
15 Prelab 1) The biasing was neglected in explanation of figure Using ±5 voltage supply rails and given L 5kO, R EE 75O, and 1.5kO, I C 1m (each transistor), and the base voltage at the inputs should be 0, choose R K so that the differential pair is correctly biased. Why might designing the circuit with a base dc voltage of zero volts be a good idea for the testing this circuit in a lab? ) For the differential pair that you biased in problem #1, determine the common mode and differential mode input resistances, R Ci and R Di, respectively. Using the values calculated for R Ci and R Di, calculate the values for R XX and R Xi and construct the input two port model of the differential pair. 3) Repeat the procedure above and calculate the common and differential mode output resistance associated the differential pair. 4) Calculate the common mode gain, differential mode gain, and CMRR for the differential pair. Convert and express your answers in db. 5) How does R EE impact the performance of the differential pair? Choose five different values for R EE and run Spice with these values? Do the Spice results support your hypothesis? 6) erify your answers in question 1-4 with Spice. You will need to simulate common and differential mode gain separately. n easy way to simulate CMRR, it to simulate the gain of the common and differential modes in decibels and then subtract the common mode gain from the differential mode gain. 7) In terms of modifying element values in figure 1.11, how could you maximize the CMRR? If you wanted to increase CMRR without altering the collector current of the transistors, what simple element replacement could be used for the resistor R K that would ideally would give this differential pair a common mode gain of zero, thus making the CMRR equal to infinity? 8) Using your solution from problem #6, replace R K and re-simulate in Spice the common mode gain, differential mode gain, and CMRR. Ideally the CMRR of the altered differential pair would be infinite, why wasn t it? 9) The theory and analysis given in this experiment thus far assumed that the differential pair is a symmetric structure, a.k.a. balanced. So what happens if the structure isn t balanced? a. So far it has been assumed that the sources are ideal and have no series resistance associated with them. What would happen if the series resistance at one terminal was different then the other. Simulate this environment in Spice by measuring the differential gain while adding a 150 O resistor at one of the two input terminals. b. It was also pointed out that the two BJT transistors have to be matched. Simulate the differential gain with unmatched transistors by adding 100 O to the value of one R EE. This will simulate the hypothetical environment of one transistor having a larger internal emitter resistance than the other. What do you observe from the Spice simulation?
16 Lab Exercises 1) Build the circuit that you came up with for problem #1 of the prelab. erify its operation and that the transistors are biased properly. Measure and record the current in all the elements in the circuit. Calculate the actual power consumption of the circuit. ) Measure the common mode gain of the differential pair. How different is it from what you calculated by hand and what you simulated in Spice. Speculate on any discrepancies between your analysis and measured data. 3) Repeat the previous procedure for the differential mode gain. Warning: a common mode at the input must be established, so simply hooking up a source between the two inputs will not work. 4) Build the circuit you came up with for question #7 in the prelab and measure its CMRR. Compare the CMRR you measure for the two different topologies. 5) Build and confirm the Spice simulations from problem #9 of the prelab. What do you observe? Why might the utility of differential pairs be limed as front-ends in analog networks? Note: Note you must have matched transistors in order to perform these exercises correctly. If matched devices are not available, then this lab exercise must be completed in Spice.
Experiment #6 MOSFET Dynamic circuits
Experiment #6 MOSFET Dynamic circuits Jonathan Roderick Introduction: This experiment will build upon the concepts that were presented in the previous lab and introduce dynamic circuits using MOSFETS.
More informationExperiment #7 MOSFET Dynamic Circuits II
Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the
More informationAnalog Integrated Circuits. Lecture 4: Differential Amplifiers
Analog Integrated Circuits Lecture 4: Differential Amplifiers ELC 601 Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina anader@ieee.org maboudina@gmail.com Department of Electronics and Communications
More informationImproving Amplifier Voltage Gain
15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance
More informationChapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier
Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode
More informationI1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab
Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.
More informationEE320L Electronics I. Laboratory. Laboratory Exercise #2. Basic Op-Amp Circuits. Angsuman Roy. Department of Electrical and Computer Engineering
EE320L Electronics I Laboratory Laboratory Exercise #2 Basic Op-Amp Circuits By Angsuman Roy Department of Electrical and Computer Engineering University of Nevada, Las Vegas Objective: The purpose of
More informationHello, and welcome to the TI Precision Labs video series discussing comparator applications. The comparator s job is to compare two analog input
Hello, and welcome to the TI Precision Labs video series discussing comparator applications. The comparator s job is to compare two analog input signals and produce a digital or logic level output based
More informationLecture 7. ANNOUNCEMENTS MIDTERM #1 willbe held in class on Thursday, October 11 Review session will be held on Friday, October 5
Lecture 7 ANNOUNCEMENTS MIDTERM #1 willbe held in class on Thursday, October 11 Review session will be held on Friday, October 5 MIDTERM #2 will be held in class on Tuesday, November 13 OUTLINE BJT Amplifiers
More informationCurrent Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.
Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. For its analysis, we assume identical transistors and neglect
More informationSAMPLE FINAL EXAMINATION FALL TERM
ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need
More informationThe Differential Amplifier. BJT Differential Pair
1 The Differential Amplifier Asst. Prof. MONTREE SRPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s nstitute of Technology North Bangkok
More informationCHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS
CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal
More informationExperiment #2 OP-AMP THEORY & APPLICATIONS
Experiment #2 OP-MP THEOY & PPLICTIONS Jonathan oderick Scott Kilpatrick Burgess Introduction: Operational amplifiers (op-amps for short) are incredibly useful devices that can be used to construct a multitude
More informationMulti-Transistor Configurations
Experiment-3 Multi-Transistor Configurations Introduction Comment The objectives of this experiment are to examine the operating characteristics of several of the most common multi-transistor configurations,
More informationCMOS Analog VLSI Design Prof. A N Chandorkar Department of Electrical Engineering Indian Institute of Technology, Bombay
CMOS Analog VLSI Design Prof. A N Chandorkar Department of Electrical Engineering Indian Institute of Technology, Bombay Lecture - 10 Types of MOSFET Amplifier So let me now continue with the amplifiers,
More informationBJT Differential Amplifiers
Instituto Tecnológico y de Estudios Superiores de Occidente (), OBJECTIVES The general objective of this experiment is to contrast the practical behavior of a real differential pair with its theoretical
More informationChapter 5 Bipolar Amplifiers. EE105 - Spring 2007 Microelectronic Devices and Circuits. Bipolar Amplifiers. Voltage Amplifier
EE05 - Spring 2007 Microelectronic Deices and ircuits hapter 5 Bipolar mplifiers 5. General onsiderations 5.2 Operating Point nalysis and Design 5.3 Bipolar mplifier Topologies 5.4 Summary and dditional
More informationEach question is worth 4 points. ST07 One-hour Quiz #2 1 3/20/2007
Name: Date: DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139 Spring Term 2007 Quiz 2 6.101 Introductory Analog Electronics
More informationThe Difference Amplifier Sept. 17, 1997
Physics 63 The Difference Amplifier Sept. 17, 1997 1 Purpose To construct a difference amplifier, to measure the DC quiescent point and to compare to calculated values. To measure the difference mode gain,
More informationAnalog Integrated Circuit Design Exercise 1
Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationLecture 7. Possible Bipolar Amplifier Topologies
Lecture 7 OUTLINE Bipolar mplifier Topologies (1) Common-Emitter mplifiers Reading: Chapter 5.3.1 EE105 Spring 2008 Lecture 7, Slide 1 Prof. Wu, UC Berkeley Possible Bipolar mplifier Topologies Three possible
More informationObjectives The purpose of this lab is build and analyze Differential amplifier based on NPN transistors.
1 Lab 03: Differential Amplifier Total 30 points: 20 points for lab, 5 points for well-organized report, 5 points for immaculate circuit on breadboard NOTES: 1) Please use the basic current mirror from
More informationLaboratory 8 Operational Amplifiers and Analog Computers
Laboratory 8 Operational Amplifiers and Analog Computers Introduction Laboratory 8 page 1 of 6 Parts List LM324 dual op amp Various resistors and caps Pushbutton switch (SPST, NO) In this lab, you will
More informationEE 482 Electronics II
EE 482 Electronics II Lab #4: BJT Differential Pair with Resistive Load Overview The objectives of this lab are (1) to design and analyze the performance of a differential amplifier, and (2) to measure
More informationinverting V CC v O -V EE non-inverting
Chapter 4 Operational Amplifiers 4.1 Introduction The operational amplifier (opamp for short) is perhaps the most important building block for the design of analog circuits. Combined with simple negative
More informationBasic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati
Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Module: 3 Field Effect Transistors Lecture-8 Junction Field
More informationVideo Course on Electronics Prof. D. C. Dube Department of Physics Indian Institute of Technology, Delhi
Video Course on Electronics Prof. D. C. Dube Department of Physics Indian Institute of Technology, Delhi Module No. # 02 Transistors Lecture No. # 09 Biasing a Transistor (Contd) We continue our discussion
More informationExperiment 8 Frequency Response
Experiment 8 Frequency Response W.T. Yeung, R.A. Cortina, and R.T. Howe UC Berkeley EE 105 Spring 2005 1.0 Objective This lab will introduce the student to frequency response of circuits. The student will
More information(Refer Slide Time: 2:29)
Analog Electronic Circuits Professor S. C. Dutta Roy Department of Electrical Engineering Indian Institute of Technology Delhi Lecture no 20 Module no 01 Differential Amplifiers We start our discussion
More informationOperational amplifiers
Chapter 8 Operational amplifiers An operational amplifier is a device with two inputs and one output. It takes the difference between the voltages at the two inputs, multiplies by some very large gain,
More informationTransistor Configuration
Transistor Configuration 1 Objectives To review BJT biasing circuit. To study BJT amplifier circuit To understand the BJT configuration. To analyse single-stage BJT amplifier circuits. To study the differential
More informationThe Inverting Amplifier
The Inverting Amplifier Why Do You Need To Know About Inverting Amplifiers? Analysis Of The Inverting Amplifier Connecting The Inverting Amplifier Testing The Circuit What If Questions Other Possibilities
More informationChapter 8 Differential and Multistage Amplifiers
1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.
More informationDC Bias. Graphical Analysis. Script
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: Ist Year, Sem - IInd Subject: Electronics Paper No.: V Paper Title: Analog Circuits Lecture No.: 3 Lecture Title: Analog Circuits
More informationComponent modeling. Resources and methods for learning about these subjects (list a few here, in preparation for your research):
Component modeling This worksheet and all related files are licensed under the Creative Commons Attribution License, version 1.0. To view a copy of this license, visit http://creativecommons.org/licenses/by/1.0/,
More informationChapter 4: Differential Amplifiers
Chapter 4: Differential Amplifiers 4.1 Single-Ended and Differential Operation 4.2 Basic Differential Pair 4.3 Common-Mode Response 4.4 Differential Pair with MOS Loads 4.5 Gilbert Cell Single-Ended and
More informationUNIVERSITY OF UTAH ELECTRICAL ENGINEERING DEPARTMENT
UNIVERSITY OF UTAH ELECTRICAL ENGINEERING DEPARTMENT ECE 3110 LAB EXPERIMENT NO. 4 CLASS AB POWER OUTPUT STAGE Objective: In this laboratory exercise you will build and characterize a class AB power output
More information55:041 Electronic Circuits The University of Iowa Fall Exam 1 Solution
Exam 1 Name: Score /60 Question 1 Short takes. For True/False questions, write T, or F in the right-hand column as appropriate. For other questions, provide answers in the space provided. 1. Tue of false:
More informationHomework Assignment 06
Homework Assignment 06 Question 1 (Short Takes) One point each unless otherwise indicated. 1. Consider the current mirror below, and neglect base currents. What is? Answer: 2. In the current mirrors below,
More informationProf. Anyes Taffard. Physics 120/220. Diode Transistor
Prof. Anyes Taffard Physics 120/220 Diode Transistor Diode One can think of a diode as a device which allows current to flow in only one direction. Anode I F Cathode stripe Diode conducts current in this
More informationApplied Electronics II
Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter
More informationEXPERIMENT 12: SIMULATION STUDY OF DIFFERENT BIASING CIRCUITS USING NPN BJT
EXPERIMENT 12: SIMULATION STUDY OF DIFFERENT BIASING CIRCUITS USING NPN BJT AIM: 1) To study different BJT DC biasing circuits 2) To design voltage divider bias circuit using NPN BJT SOFTWARE TOOL: PC
More informationIntegrated Circuit: Classification:
Integrated Circuit: It is a miniature, low cost electronic circuit consisting of active and passive components that are irreparably joined together on a single crystal chip of silicon. Classification:
More informationUNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences. Discussion Notes #9
UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Discussion Notes #9 EE 05 Spring 2007 Prof. Wu BJT Amplifiers Recall from Chapter
More informationLab 2: Discrete BJT Op-Amps (Part I)
Lab 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and
More informationOperational amplifiers
Operational amplifiers Bởi: Sy Hien Dinh INTRODUCTION Having learned the basic laws and theorems for circuit analysis, we are now ready to study an active circuit element of paramount importance: the operational
More informationEE133 - Prelab 3 The Low-Noise Amplifier
Prelab 3 - EE33 - Prof. Dutton - Winter 2004 EE33 - Prelab 3 The Low-Noise Amplifier Transmitter Receiver Audio Amp XO BNC to ANT BNC to ANT XO CO (LM566) Mixer (SA602) Power Amp LNA Mixer (SA602) IF Amp
More informationWell we know that the battery Vcc must be 9V, so that is taken care of.
HW 4 For the following problems assume a 9Volt battery available. 1. (50 points, BJT CE design) a) Design a common emitter amplifier using a 2N3904 transistor for a voltage gain of Av=-10 with the collector
More informationExperiment 6: Biasing Circuitry
1 Objective UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Experiment 6: Biasing Circuitry Setting up a biasing
More informationEE301 Electronics I , Fall
EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials
More informationECE 255, Discrete-Circuit Amplifiers
ECE 255, Discrete-Circuit Amplifiers 20 March 2018 In this lecture, we will continue with the study of transistor amplifiers with the presence of biasing circuits and coupling capacitors in place. We will
More informationWhen input, output and feedback voltages are all symmetric bipolar signals with respect to ground, no biasing is required.
1 When input, output and feedback voltages are all symmetric bipolar signals with respect to ground, no biasing is required. More frequently, one of the items in this slide will be the case and biasing
More informationInverting input R 2. R 1 Output
nalogue Electronics 8: Feedback and Op mps Last lecture we introduced diodes and transistors and an outline of the semiconductor physics was given to understand them on a fundamental level. We use transistors
More informationPhysics S123 HW 3: Bipolar Transistors I
S123 HW 3: Bipolar Transistors I 1 Physics S123 HW 3: Bipolar Transistors I Total Points: 18 REV 0; June 27, 2008. DUE Thursday, July 3, 2008 If a question baffles you, email one of us. The fault may lie
More informationDescribe the basic DC characteristics of an op amp. Sketch a diagram of the op amp DC test circuit. Input Offset Voltage. Input Offset Current
Testing Op Amps Chapter 3 Goals Understand the requirements for testing Op Amp DC parameters. Objectives Describe the basic DC characteristics of an op amp. Select a test methodology for evaluating voltage
More informationOp-Amp Specifications
Op-Amp Specifications Getting Some Input Part of 4 In Part of this Microseries, Joe discusses specifications for input offset currents and voltages, as well as input bias current If lowfrequency and precision
More informationMini Project 3 Multi-Transistor Amplifiers. ELEC 301 University of British Columbia
Mini Project 3 Multi-Transistor Amplifiers ELEC 30 University of British Columbia 4463854 November 0, 207 Contents 0 Introduction Part : Cascode Amplifier. A - DC Operating Point.......................................
More informationShown here is a schematic diagram for a real inverter circuit, complete with all necessary components for efficient and reliable operation:
The NOT gate The single-transistor inverter circuit illustrated earlier is actually too crude to be of practical use as a gate. Real inverter circuits contain more than one transistor to maximize voltage
More informationLab 6 Prelab Grading Sheet
Lab 6 Prelab Grading Sheet NAME: Read through the Background section of this lab and print the prelab and in-lab grading sheets. Then complete the steps below and fill in the Prelab 6 Grading Sheet. You
More informationI C I E =I B = I C 1 V BE 0.7 V
Guide to NPN Amplifier Analysis Jason Woytowich 1. Transistor characteristics A BJT has three operating modes cutoff, active, and saturation. For applications, like amplifiers, where linear characteristics
More informationDifferential Amplifier Design
Differential Amplifier Design Design with ideal current source bias. Differential and common mode gain results Add finite output resistance to current source. Replace ideal current source with current
More informationPhysics 303 Fall Module 4: The Operational Amplifier
Module 4: The Operational Amplifier Operational Amplifiers: General Introduction In the laboratory, analog signals (that is to say continuously variable, not discrete signals) often require amplification.
More informationAnalysis and Design of a Simple Operational Amplifier
by Kenneth A. Kuhn December 26, 2004, rev. Jan. 1, 2009 Introduction The purpose of this article is to introduce the student to the internal circuits of an operational amplifier by studying the analysis
More informationLab 5: Multi-Stage Amplifiers
UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Lab 5: Multi-Stage Amplifiers Contents 1 Introduction 1 2 Pre-Lab
More informationLinear electronic. Lecture No. 1
1 Lecture No. 1 2 3 4 5 Lecture No. 2 6 7 8 9 10 11 Lecture No. 3 12 13 14 Lecture No. 4 Example: find Frequency response analysis for the circuit shown in figure below. Where R S =4kR B1 =8kR B2 =4k R
More informationINDIANA UNIVERSITY, DEPT. OF PHYSICS, P400/540 LABORATORY FALL Laboratory #5: More Transistor Amplifier Circuits
INDIANA UNIVERSITY, DEPT. OF PHYSICS, P400/540 LABORATORY FALL 2008 Laboratory #5: More Transistor Amplifier Circuits Goal: Use and measure the behavior of transistor circuits used to implement different
More informationExperiment 8 - Single Stage Amplifiers with Passive Loads - BJT
Experiment 8 - Single Stage Amplifiers with Passie Loads - BJT D. Yee, W.T. Yeung, C. Hsiung, S.M. Mehta, and R.T. Howe UC Berkeley EE 105 1.0 Objectie A typical integrated circuit contains a large number
More informationDifferential transistor amplifiers
Differential transistor amplifiers This worksheet and all related files are licensed under the Creative Commons Attribution License, version 1.0. To view a copy of this license, visit http://creativecommons.org/licenses/by/1.0/,
More informationBJT IC Design ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING. BJT IC Design. Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING BJT IC Design Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee/ 82 Lomb Memorial Drive Rochester, NY 146235604 Tel (585) 4752035 Email:
More informationExperiment 6: Biasing Circuitry
1 Objective UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Experiment 6: Biasing Circuitry Setting up a biasing
More informationA 3-STAGE 5W AUDIO AMPLIFIER
ECE 2201 PRELAB 7x BJT APPLICATIONS A 3-STAGE 5W AUDIO AMPLIFIER UTILIZING NEGATIVE FEEDBACK INTRODUCTION Figure P7-1 shows a simplified schematic of a 3-stage audio amplifier utilizing three BJT amplifier
More informationChip Name Min VolT. Max Volt. Min. Out Power Typ. Out Power. LM386N-1 4 Volts 12 Volts 250 mw 325 mw. LM386N-3 4 Volts 12 Volts 500 mw 700 mw
LM386 Audio Amplifier Analysis The LM386 Voltage Audio Power Amplifier by National Semiconductor and also manufactured by JRC/NJM, is an old chip (mid 70 s) that has been a popular choice for low-power
More informationINTEGRATED CIRCUITS. AN179 Circuit description of the NE Dec
TEGRATED CIRCUITS AN79 99 Dec AN79 DESCPTION The NE564 contains the functional blocks shown in Figure. In addition to the normal PLL functions of phase comparator, CO, amplifier and low-pass filter, the
More informationTransistor Configuration
Transistor Configuration 1 Objectives To review BJT biasing circuit. To study BJT amplifier circuit To understand the BJT configuration. To analyse single-stage BJT amplifier circuits. To study the differential
More informationOperational Amplifiers
Operational Amplifiers Table of contents 1. Design 1.1. The Differential Amplifier 1.2. Level Shifter 1.3. Power Amplifier 2. Characteristics 3. The Opamp without NFB 4. Linear Amplifiers 4.1. The Non-Inverting
More informationBASIC ELECTRONICS PROF. T.S. NATARAJAN DEPT OF PHYSICS IIT MADRAS
BASIC ELECTRONICS PROF. T.S. NATARAJAN DEPT OF PHYSICS IIT MADRAS LECTURE-12 TRANSISTOR BIASING Emitter Current Bias Thermal Stability (RC Coupled Amplifier) Hello everybody! In our series of lectures
More informationFinal Design Project: Variable Gain Amplifier with Output Stage Optimization for Audio Amplifier Applications EE 332: Summer 2011 Group 2: Chaz
Final Design Project: Variable Gain Amplifier with Output Stage Optimization for Audio Amplifier Applications EE 332: Summer 2011 Group 2: Chaz Bofferding, Serah Peterson, Eric Stephanson, Casey Wojcik
More informationES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016)
Page1 Name ES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016) Problem 1 (15 points) You are given an NMOS amplifier with drain load resistor R D = 20 k. The DC voltage (V RD
More informationSmall signal ac equivalent circuit of BJT
UNIT-2 Part A 1. What is an ac load line? [N/D 16] A dc load line gives the relationship between the q-point and the transistor characteristics. When capacitors are included in a CE transistor circuit,
More informationLaboratory Experiment 8 EE348L. Spring 2005
Laboratory Experiment 8 EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 1 EE348L, Spring 2005 B. Madhavan - 2 of 2- EE348L, Spring 2005 Table of Contents 8 Experiment #8: Introduction
More informationLast time: BJT CE and CB amplifiers biased by current source
Last time: BJT CE and CB amplifiers biased by current source Assume FA regime, then VB VC V E I B I E, β 1 I Q C α I, V 0. 7V Calculate V CE and confirm it is > 0.2-0.3V, then BJT can be replaced with
More informationChapter 11. Differential Amplifier Circuits
Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed
More informationCommon-Emitter Amplifier
Dr. Charles Kim Common-Emitter Amplifier A. Before We Start As the title of this lab says, this lab is about designing a Common-Emitter Amplifier, and this in this stage of the lab course is premature,
More informationOp-amp characteristics Operational amplifiers have several very important characteristics that make them so useful:
Operational Amplifiers A. Stolp, 4/22/01 rev, 2/6/12 An operational amplifier is basically a complete high-gain voltage amplifier in a small package. Op-amps were originally developed to perform mathematical
More information1. INTRODUCTION TO OPERATIONAL AMPLIFIERS. The standard operational amplifier (op-amp) symbol is shown in Figure (1-a):-
Subject:- Electronic II /1 st Semester Class: 3 rd (Communication & Power Eng.) Lecturer: - Dr. Thamer M. J. Electrical Eng. Dep. Technology Univ. (This subject is deal with analog electronic circuit design
More informationUNIT - 1 OPERATIONAL AMPLIFIER FUNDAMENTALS
UNIT - 1 OPERATIONAL AMPLIFIER FUNDAMENTALS 1.1 Basic operational amplifier circuit- hte basic circuit of an operational amplifier is as shown in above fig. has a differential amplifier input stage and
More informationV o2 = V c V d 2. V o1. Sensor circuit. Figure 1: Example of common-mode and difference-mode voltages. V i1 Sensor circuit V o
M.B. Patil, IIT Bombay 1 BJT Differential Amplifier Common-mode and difference-mode voltages A typical sensor circuit produces an output voltage between nodes A and B (see Fig. 1) such that V o1 = V c
More information55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point.
Exam 3 Name: Score /65 Question 1 Unless stated otherwise, each question below is 1 point. 1. An engineer designs a class-ab amplifier to deliver 2 W (sinusoidal) signal power to an resistive load. Ignoring
More informationChapter 6. BJT Amplifiers
Basic Electronic Devices and Circuits EE 111 Electrical Engineering Majmaah University 2 nd Semester 1432/1433 H Chapter 6 BJT Amplifiers 1 Introduction The things you learned about biasing a transistor
More information// Parts of a Multimeter
Using a Multimeter // Parts of a Multimeter Often you will have to use a multimeter for troubleshooting a circuit, testing components, materials or the occasional worksheet. This section will cover how
More information(Refer Slide Time: 02:05)
Electronics for Analog Signal Processing - I Prof. K. Radhakrishna Rao Department of Electrical Engineering Indian Institute of Technology Madras Lecture 27 Construction of a MOSFET (Refer Slide Time:
More informationExperiment #6: Biasing an NPN BJT Introduction to CE, CC, and CB Amplifiers
SCHOOL OF ENGINEERING AND APPLIED SCIENCE DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ECE 2115: ENGINEERING ELECTRONICS LABORATORY Experiment #6: Biasing an NPN BJT Introduction to CE, CC, and CB
More informationES330 Laboratory Experiment No. 9 Bipolar Differential Amplifier [Reference: Sedra/Smith (Chapter 9; Section 9.2; pp )]
ES330 Laboratory Experiment No. 9 Bipolar Differential Amplifier [Reference: Sedra/Smith (Chapter 9; Section 9.2; pp. 614-627)] Objectives: 1. Explore the operation of a bipolar junction transistor differential
More informationBasic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati
Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Module: 2 Bipolar Junction Transistors Lecture-1 Transistor
More informationEEE225: Analogue and Digital Electronics
EEE225: Analogue and Digital Electronics Lecture II James E. Green Department of Electronic Engineering University of Sheffield j.e.green@sheffield.ac.uk This Lecture 1 One Transistor Circuits Continued...
More informationPhysics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 12, 2017
Physics 623 Transistor Characteristics and Single Transistor Amplifier Sept. 12, 2017 1 Purpose To measure and understand the common emitter transistor characteristic curves. To use the base current gain
More informationAnalog Electronics (Course Code: EE314) Lecture 9 10: BJT Small Signal, Biasing, Amplifiers
Indian Institute of Technology Jodhpur, Year 08 Analog Electronics (ourse ode: EE34) Lecture 9 0: BJT Small Signal, Biasing, Amplifiers ourse Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationMinimizing Distortion in Operational Transconductance Amplifiers
1 Minimizing Distortion in Operational Transconductance Amplifiers openmusiclabs October 3, 015 I. INTRODUCTION The Operational Transconductance Amplifier (OTA) is perhaps one of the most indispensable
More information