Experiment #12 BJT Differential Pairs

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1 Introduction: Experiment #1 BJT Differential Pairs Jonathan Roderick differential pair is a four port network that is shown in figure 1.1. These ports are labeled through D. However, a differential pair is nothing more than two identical amplifiers that are combined in a symmetric way to achieve a desired performance. lthough the first draw back to using a differential pair is that it requires the use of two amplifiers which doubles the power consumption. If power consumption is not a critical issue, it will be shown that the differential pair has other benefits that outweigh the increased power consumption. These benefits make the differential pair an established topology in the analog circuit design. This lab will present the basic differential pair, then it will show how to analyze a balanced differential pair through a technique called the half-circuit analysis. R S S1 R S B Differential mplifier C D o - L 01 DO + S Figure 1.1 Differential mplifier. This lab must use matched transistors for the differential pair. If matched devices on-chip are not readily available then in must be completed entirely in spice. Theory: It was mentioned above that differential pairs are nothing more than two amplifiers connected together. In figure 1. a schematic is shown of a typical differentia l pair. The amplifiers, depicted by the triangles, are ideal. The discussion that follows will not worry about the logistics of the amplifiers themselves. s it will be seen, the performance of the differential amplifier depends more on the topology in which the two amplifiers are connected, rather than the amplifiers themselves, assuming the amplifiers work relatively close to ideal and are identical. To prove this point, later on in the lab, the amplifiers symbols will be replace by simple common-emitter amplifiers.

2 R S mp #1 S1 R EE R K R EE R S mp # O L O1 S _ DO + Figure 1. differential pair configuration. In figure 1., the two sources, S1 and S, comprise of both signal and biasing. The differential amplifier, like everything else in science, receives its name from its performance. well-designed differential amplifier rejects signals that are common to both inputs and amplifies signals that are uncorrelated. The standard of measurement of how well a differential pair amplifies differential signals and rejects common signals is called the common mode rejection ratio (CMRR). The CMRR is calculated as follows CMRR diff com (1.1) Where diff is the differential gain and com is the common gain. Why is this important? good way to eliminate nois e from a system is to use a differential pair. If your differential pair topology is symmetric, then inherent electrical noise will be a common signal at both inputs. Thus, it is possible to cleanup your signal using a differential pair. nother example is the temperature dependence of devices. Ideally biasing is stable, but in real world applications the bias fluctuates with temperature. In a regular common-emitter amplifier, this change in bias also gets amplified. This is very undesirable and a differential pair is one very practicable solution. Half-circuit analysis: Now that the basics have been covered, an analysis of figure 1. will be shown as an example. The halfcircuit analysis is only valid for balanced differential pairs. Balanced means that is you drew a line through the middle of the topology that you would see exactly the same thing on both sides of the line. In

3 other words, the circuit is completely symmetric. The reason behind doing the half-circuit analysis is to break down the circuit into differential and common modes, so that the CMRR can be easily calculated. The first step is doing a half-circuit analysis is to break up the input signals into differential and common parts. di is defined as the differential input and it is calculated by di S1 S (1.) ci is the common input voltage. The common input voltage is nothing more then the average. ci + d1 d (1.3) Now that the common and differential inputs have been defined, the differential output and common output voltages, do and co respectively, can be addressed. do o1 o (1.4) co + o1 o (1.5) In was mentioned that S1 and S are made up of biasing, common, and signal, differential. Using the equations above and solving for S1 and S di S1 c 1 + (1.6) S c1 di (1.7) This satisfies equation 1.. Now the signals in figure 1. can be replaced with a common and differential mode parts. This is shown in figure 1.3. Now say for argument, the common mode was zero, ci 0. Now any differential signal across the inputs is going to cause one amplifier to amplify a certain amount, while causing the other amplifier to amplify the same amount but with opposite polarity, due to the polarity difference of the differential signals at the output in figure 1.3. Think of it as a seesaw. So if amplifier #1 gets a differential signal that causes it to pull up a certain amount, than amplifier # is going be pushed down that same amount.

4 Now for the case that differential mode is set to zero. ny signal change is going to raise or lower both amplifiers by the same amount. So the common mode can be though of as the fulcrum of the seesaw. _ + di R S mp #1 R EE R K + _ ci + di R S R EE mp # 0 L _ + DO o1 Figure 1.3 Differential pair with common and differential mode inputs. The whole advantage of the half-circuit method is you will be performing an analysis on only half of the original circuit. This will make the analysis and you life much easier. Using what you observe from the half circuit, you will be able to accurately model the entire differential pair. In order to calculate the CMRR of the differential pair, half-circuit calculations must be done for both the common and differential modes. These half-circuit models will yield the gain of the differential and common modes, thus allowing for the calculation of the CMRR. Differential mode half-circuit The differential half circuit is found by first setting the common mode to zero. Next, to breakup the topology into two halves, draw a virtual line through the entire differential pair so that the circuit is broken into two symmetric sides. Whatever signal you apply into amplifier #1 results in an equal magnitude, yet opposite polarity signal applied to amplifier #, causing an equal but opposite reaction throughout the entire circuit. This equal but opposite reaction combined with Kirchoff current laws (KCL) results with every node that the virtual line crosses becoming a virtual ground. For example in figure 1.3, a voltage 1 applied to mplifier #1 is going to cause a current, I1, to be generated in R EE connected to mplifier #1. voltage 1 applied to mplifier # will cause I1 to flow in R EE connected to mplifier #. Looking at the node connecting the two R EE and R K resistors and using KCL, the current flowing through R K is zero. This creates a virtual ground at the node that connects R EE to R K.

5 In order to complete the separation of the circuit into two halves, the same thing must be done at the output. This might not seem as trivial as the last case, but it really is. Divide L into two resistors of half the value connected in series. With this modification the virtual ground is found by inspection. The following differential half-circuit shown in figure 1.4 should result. Di R Di R S R EE mplifier R Do L Do Figure 1.4 The Differential mode half-circuit equivalent circuit of figure 1.. Now that the circuit has been simplified, the differential gain, D, may be calculated from the half-circuit equivalent with the following equation. Do Di Ci 0 Do Di D (1.8) Equation 1.8 indicates that the differential gain of the half circuit is the differential gain of the entire circuit. The differential mode input and output resistance is a straight forward process and is calculated using the differential half-circuit. Notice in figure 1.4, the input and output resistance calculated from the deferential mode half circuit is equal to R Di / and R Do /, respectively. These two resistance will be needed later for the input and output resistance of the entire topology. Common mode half circuit The first step in realizing the common mode half-circuit is to set the differential part of the signal to zero in figure 1.3, Di 0. Next, breakup the topology into two halves by drawing a virtual line, just like you did for the differential mode. Now that the common mode is being modeled, the analysis is a little different. Whatever signal you apply into amplifier #1 results in an equal magnitude and polarity in mplifier #. The common mode signal causes an equal action throughout both amplifiers.

6 The task of dividing the circuit into two halves in order to perform a half-circuit analysis is a little different from differential mode case. In the differential mode all nodes that the virtual line ran through became virtual grounds, this is not the case for the common mode half circuit. Using KCL and the fact that the common mode input voltage induces the same reaction throughout the topology; one can conclude that the value of R K in figure 1.3 must be doubled in the common mode half circuit. To explain why the value of R K is doubled refer back to figure 1.3. If a common mode input used as a perturbation for both amplifiers, then the same current will flow through both R EE resistors. Depending on the polarity of the common mode input, these two equal current will either flow to or from the node that connects both R EE resistors to R K. If one wants to insure the same current that flow through R EE in the half circuit, then R K, must be doubled. The output load is treated in much the same way. Once again, to accurately model the load resistance one must remember KCL and the fact that equal symmetrically reactions occur from a common mode input. Using this as a plan of attack, one can see that the output load is simply modeled by a single resistor,, tied to ground. This is because the common mode input voltage raises and lowers the output voltages, o1 and o, the same way and at the same rate. If o1 and o are equally affected by the input, then the voltage drop across L is zero and it can be removed from the half circuit. The common mode half-circuit equivalent is show in figure 1.5. R Ci R Co mplifier o1 Co R s R EE ci R K Figure 1.5 The Common mode half-circuit equivalent circuit of figure 1.. The common mode gain, C, can be calculated using the following equation. It can be seen that the gain calculated by the common mode half circuit equal to the common-mode gain. Using what was learned in the differential mode section, the common mode rejection ratio is easily calculated using equations 1.8 and 1.9.

7 Co Ci Di C 0 (1.9) Net Input and Output resistance of Network: The net input and output resistance will be derived from a two port perspective. The input and output can be model as a two port, then the contributions from the common mode and differential mode can be used to determine the net input and output resistance of the network. The input ports labeled and B from figure 1.1 can be modeled as the two port equivalent found in figure 1.6. R XI B R XX R XX Figure 1.6 Two-port equivalent of the input port of a differential amplifier. First consider the common mode contribution to the net input resistance. This is accomplished by following the same methodology that was used to determine the common and differential mode half circuits. For the common mode, two identical signals are hooked up to ports and B as shown in figure 1.7.

8 I s1 R in R XI B R in I s1 s1 R XX R XX s1 Figure 1.7 Common mode configuration for determining input resistance. The currents I s1 and I s are established by the applied voltage sources identical voltages s1 and s. If the common mode signal are the same then the voltages established at ports and B are identical. If the voltages at ports and B are the same, then no current flows through resistor R XI. Therefore figure 1.7 reduces to figure 1.8. For this one can see that R XX R Ci (1.10) I s1 R in B R in I s1 s1 R XX R XX s1 Figure 1.8 Calculating the common mode contribution to the net input res istance. Going back to figure 1.6 it can be sent that R XI still needs to be calculated in terms of common and differential mode resistances. Before two equal voltages were introduced to ports and B, now introduce two equal but opposite signals at these same ports. If we keep to the notation used earlier for differential mode analysis, two signal in opposite polarity equal to Di / would be hooked up to ports and B. This is equivalent to connecting one voltage source equal to Di between ports and B. This is shown in figure 1.9.

9 Di B R XI R XX R XX Figure 1.9 Differential mode configuration for determining input resistance. Calculating the resistance seen by Di is straight forward as is given in equation R R R Di (1.11) XI Ci R XI can be solved for using equation 1.11 and is stated below. R XI R R Ci Ci R Di R Di (1.1) The exact same type of analysis can be done for the output resistance using nodes C and D. The two port equivalent of the output is given in figure 1.10.

10 C R XO D R Co R Co Figure 1.10 Differential pair output resistance two-port equivalent. Where R Co is the common mode output resistance found through half circuit analysis and R XO is given below in equation R XO R R Co Co R Do R Do (1.13) Differential Pair Example: differential pair circuit is shown in figure Biasing has been neglected, but it is assumed that the transistors are all in linear operation.

11 + cc + cc L R s R s Q 1 Q R ee R ee s R K - ee Figure 1.11 Differential pair example using BJTs. pplying the techniques for half-circuit analysis, the CMRR of figure 1.11 will be calculated. Calculation of the network input and output resistance will be left as a prelab exercise. Differential mode: To find the differential mode half circuit we set the common mode input in figure 1.13 to zero. If we draw a line down the middle of the topology and place a ground at all the nodes this line hits, we will end up with the half circuit shown in figure 1.1. From what was learned from experiment #6, you should be able to determine the gain of this half-circuit virtually by inspection. The differential gain is give below. D Do Di r s + r b RLL β RL + r + ( β + 1)( r + R π e ee ) (1.14)

12 L R Di D0 R s R Do Di R ee Figure 1.1 Differential half-circuit Common mode: The common mode half circuit should also be constructed using the instruction that were given earlier. The first step is to set the differential contribution of the source, in figure 1.3, to zero. The resistors in both figure 1.3 and 1.11 have been named the same to assist in the recognition of how to construct the correct half circuit. Using KCL and the fact that the common mode input voltage induces the same reaction throughout the topology; one can conclude that the value of R K must be doubled in the common mode half circuit. The reason why R K is double is to insure same current that flow through R EE in the half circuit as it did in the complete topology. Next, the output has to be taken into consideration. It can be seen that the output load is simply modeled by a single resistor,, tied to ground. This is because the common mode input voltage raises and lowers the output voltages, o1 and o, the same way and at the same rate. If o1 and o are equally affected by the input, then the voltage drop across L is zero and thus it can be removed from the half circuit. The common mode half-circuit is shown in figure From this circuit the common mode gain is found to be: C Co Ci r s + r b + r π βr L + ( β + 1)( re + Ree + RK ) (1.14)

13 R Ci C R s R Co Ci R ee R K Figure 1.13 Common mode half-circuit Now the CMRR can be easily calculated. D CMRR (1.15) C Conclusion: Differentials pairs were presented along with a technique called half-circuit analysis. Half-circuit analysis allows a circuit designer to do analysis on only half the circuit, yet use these results to model the behavior of the entire circuit. Thus eliminating half the work involved. To be sure, half circuit analysis is only beneficial and valid when doing analysis on differential pair technology that is perfectly symmetric or balanced.

14 Reference reading 1) John Choma, Jr. EE348 lecture notes. University of Southern California. Spring 001.

15 Prelab 1) The biasing was neglected in explanation of figure Using ±5 voltage supply rails and given L 5kO, R EE 75O, and 1.5kO, I C 1m (each transistor), and the base voltage at the inputs should be 0, choose R K so that the differential pair is correctly biased. Why might designing the circuit with a base dc voltage of zero volts be a good idea for the testing this circuit in a lab? ) For the differential pair that you biased in problem #1, determine the common mode and differential mode input resistances, R Ci and R Di, respectively. Using the values calculated for R Ci and R Di, calculate the values for R XX and R Xi and construct the input two port model of the differential pair. 3) Repeat the procedure above and calculate the common and differential mode output resistance associated the differential pair. 4) Calculate the common mode gain, differential mode gain, and CMRR for the differential pair. Convert and express your answers in db. 5) How does R EE impact the performance of the differential pair? Choose five different values for R EE and run Spice with these values? Do the Spice results support your hypothesis? 6) erify your answers in question 1-4 with Spice. You will need to simulate common and differential mode gain separately. n easy way to simulate CMRR, it to simulate the gain of the common and differential modes in decibels and then subtract the common mode gain from the differential mode gain. 7) In terms of modifying element values in figure 1.11, how could you maximize the CMRR? If you wanted to increase CMRR without altering the collector current of the transistors, what simple element replacement could be used for the resistor R K that would ideally would give this differential pair a common mode gain of zero, thus making the CMRR equal to infinity? 8) Using your solution from problem #6, replace R K and re-simulate in Spice the common mode gain, differential mode gain, and CMRR. Ideally the CMRR of the altered differential pair would be infinite, why wasn t it? 9) The theory and analysis given in this experiment thus far assumed that the differential pair is a symmetric structure, a.k.a. balanced. So what happens if the structure isn t balanced? a. So far it has been assumed that the sources are ideal and have no series resistance associated with them. What would happen if the series resistance at one terminal was different then the other. Simulate this environment in Spice by measuring the differential gain while adding a 150 O resistor at one of the two input terminals. b. It was also pointed out that the two BJT transistors have to be matched. Simulate the differential gain with unmatched transistors by adding 100 O to the value of one R EE. This will simulate the hypothetical environment of one transistor having a larger internal emitter resistance than the other. What do you observe from the Spice simulation?

16 Lab Exercises 1) Build the circuit that you came up with for problem #1 of the prelab. erify its operation and that the transistors are biased properly. Measure and record the current in all the elements in the circuit. Calculate the actual power consumption of the circuit. ) Measure the common mode gain of the differential pair. How different is it from what you calculated by hand and what you simulated in Spice. Speculate on any discrepancies between your analysis and measured data. 3) Repeat the previous procedure for the differential mode gain. Warning: a common mode at the input must be established, so simply hooking up a source between the two inputs will not work. 4) Build the circuit you came up with for question #7 in the prelab and measure its CMRR. Compare the CMRR you measure for the two different topologies. 5) Build and confirm the Spice simulations from problem #9 of the prelab. What do you observe? Why might the utility of differential pairs be limed as front-ends in analog networks? Note: Note you must have matched transistors in order to perform these exercises correctly. If matched devices are not available, then this lab exercise must be completed in Spice.

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