EE 171. MOS Transistors (Chapter 5) University of California, Santa Cruz May 1, 2007

Transcription

1 EE 171 MOS Transistors (Chapter 5) Uniersity of California, Santa Cruz May 1, 007

2 FET: Fiel Effect Transistors MOSFET (Metal-Oxie-Semiconuctor) N-channel (NMOS) P-channel (PMOS) Enhancement type (V to > 0, nee a gate oltage to conuct) Depletion type (V to < 0, alreay conucting) JFET (Junction FET) N-channel P-channel

3 NMOS Transistor Four eice terminals: rain (D), gate (G), source (S), an boy (B) Gate is insulate from the substrate by thin oxie ith a sufficiently large + gate oltage, an n-type channel (electrons) is inuce uner the gate which connects the rain an the source Apply a rain to source oltage to conuct current n-channel enhancement MOSFET showing channel length L an channel with.

4 Cutoff egion For the gate-source alues V GS < V to there will be no channel forme uner the gate area Drain to boy junction reerse biase No current will flow 0 ( V < GS Vto ) For GS < V to the pn junction between rain an boy is reerse biase an i D 0.

5 Trioe (Linear) egion For gate source oltages V GS > V to an small V DS alues, the n-type channel behaes like a ariable resistor Current epens on V DS an excess gate oltage V GS - V to (: into page) L KP Electron mobility µ C n ox µ nε t ox ox Oxie thickness KP L (V GS V to ( VDS < VGS Vto) )V DS V DS Negligible for small V DS channel V DS KP L (V 1 GS V to )V DS For GS >V to a channel of n-type material is inuce in the region uner the gate. As GS increases, the channel becomes thicker. For small alues of DS,i D is proportional to DS.. The eice behaes as a resistor whose alue epens on GS.

6 Saturation egion As V DS increases, the channel pinches own at the rain en an D increases more slowly V DS term becomes more ominant in linear equation Finally for V DS > V GS V to, D becomes constant Channel pinches off (V GD V to ) KP (VGS Vto) L ( VDS > VGS Vto)

7 NMOS V Cures KP V DS L KP L (V GS V (parabolic shape) to )V DS V DS L KP (VGS Vto) (constant s. V DS ) Cutoff: V GS < V to Trioe: V GS > V to an V DS < V GS V to Saturation: V GS > V to an V DS > V GS V to 0 Characteristic cures for an NMOS transistor (V to )

8 More Accurate NMOS V Cure n saturation, is not completely horizontal Output resistance not infinitely large ntrouce a channel length moulation parameter, λ KP L (V GS V to )V DS VDS (1+ λv DS ) KP L (V GS V to ) (1 + λv DS )

9 NMOS common Source Amplifier The DC sources (V GG an V DD ) bias the amplifier at a suitable operating point for amplification (saturation) Varying sinusoial signal at the gate changes the rain current Change in rain current results change in oltage rop across an a change in V DS (output) V D DD D 1 D D V + DS V DS V + DD D Simple NMOS amplifier circuit.

10 Loa Line Analysis Output is inerte an amplifie Also istorte (unequal swings from Q-point) This is just the first step of amplifier analysis DC analysis: etermine the Q-point Use small signal equialent circuit to fin the gain an impeances. 1 D VDS + D V DD D Drain characteristics an loa line for the circuit

11 Fixe-Plus Self-Bias Circuits Use to establish Q-points that are relatiely inepenent of eice parameters mplementation similar to BJTs G 0 (gate is an insulator) Don t nee to erify that G << 1 an V GS is not constant BJT analysis: V BE 0.7 in actie moe (moel: battery) Here, use the MOS V equation (sole a quaratic equation to get the bias point)

12 Fixe-Plus Self-Bias Circuits: Q-Point Assume MOS transistor is in saturation (nees to be erifie later) V D DD s V GS D + V s DD + V 1 GS + 1 s Set equations equal to each other an sole for V GS V G Graphical solution of Equations. (not V DS )

13 Graphical analysis of operating point High alue of V G results in less ariation in D between the high current eice an the low current eice Bias point inepenent of transistor Howeer, a high V G alue woul lea to a high oltage rop across s V S is a fraction of V G (KVL) V DD fixe esults in less V DS for the eice ant to keep MOS transistor in saturation The more nearly horizontal bias line results in less change in the Q-point.

14 Small Signal Analysis Again after proper biasing we insert small ac signal into our amplifier. D id(t) DQ + i (t) Total DC AC

15 Small Signal Equialent Circuit No gate current ( G 0) Moel as an open circuit (no r π resistor) Assume MOS transistor operates in saturation DQ L DQ + i (t) KP (VGSQ + gs (t) Vto ) + L L L KP (VGS Vto) [ (t ] DQ + i (t) KP (VGSQ Vto) + KP (VGSQ Vto )gs(t) KP gs ) L negligible (small signal) i (t) KP (VGSQ Vto ) gs (t) g L m gs (t) g KP L m DQ For high gm, use high DQ Also, notice that: g m i gs

16 Small Signal Circuit: mproements A more accurate moel accounts for finite output resistance of the eice A similar effect can be introuce into the BJT small signal moel To fin g m an r, use the V characteristics aroun the Q point Alternatiely, use g r m DQ λ 1 DQ KP L g m KCL: i gs i g + m gs r s + s Change in in the ertical irection 1 r i s 1/slope of the V characteristics See Example 5.5 an Exercises

17 Common Source Amplifier Similar to BJT common emitter amplifier Coupling capacitors C 1 an C an bypass capacitor C s hae small impeances for the AC signal (esigne this way) DC analysis: 4 resistor bias circuit Use to fin operating point Use V cures to fin g m an r for small circuit moel

18 Common Source Amplifier: AC Analysis Use the AC small signal equialent circuit to fin the gain an input impeance A ( r ) o in g m D L Z in 1 in iin i in in 1 g o m in ( r ) D L

19 Common Source Amplifier: Output mpeance n orer to fin the output impeance short the input source at the input sie KVL: + G 0, so 0 an gs 0 o r i O D o

20 FET Source Follower Generate the small signal equialent circuit to figure out A an Z in A o in g g m m ( r S L ) ( r ) + S L in gs o g o in Z in iin m gs ( r ) 1 For g m (r s L ) >> 1 S L

21 Source Follower: Output mpeance Short the source at the input sie KVL: + gs 0 KCL: x (V gs! 0 this time) x s + r x i x + g m gs Equialent circuit use to fin the output resistance of the source follower. x 1 1 O S r i g g x m m "Low" Output esistance (g m esigne to be large) See Example 5.8

22 See Exercise 5.1 Common Gate Amplifier A o V m L in in O g 1 1 S g g m D ' m Common-gate amplifier.

23 n-channel Depletion MOSFET n-channel is forme uner the gate uring the fabrication process Deice will conuct for zero gate-source oltage Apply a negatie gate-source oltage to shut own the eice Soli n line n-channel epletion MOSFET.

24 Depletion s. Enhancement V Cures Drain current ersus GS in the saturation region for n-channel eices.

25 PMOS Transistors Makes CMOS (an igital logic) possible Eerything reerses Boy: n-type substrate Source/rain junctions: p-type V to < 0 for an enhancement eice Nee a negatie gate oltage to turn the eice on V GS < V to both negatie Attracts + carriers to the surface Saturation: V DS must be large an negatie V DS < V GS V to (all oltages are negatie here) p-channel FET circuit symbols. These are the same as the circuit symbols for n-channel eices, except for the irections of the arrowheas. Think of P type eices as upsie own N type eices (often rawn this way) Similar to PNP bipolar transistors

26 Figure 5.49 Drain current ersus GS for seeral types of FETs. i D is reference into the rain terminal for n-channel eices an out of the rain for p-channel eices. hile the large signal bias conitions iffer for all the ifferent FET flaors the goo news is that their small signal moels are all the same.

27 Summary of the FET Family