Lecture 9. Bipolar Junction Transistor (BJT) BJT 1-1

Transcription

1 Lecture 9 ipolar Junction Transistor (JT) JT 1-1

2 Outline ontinue JT JT iasing D analysis Fixed-bias circuit mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback circuit JT switching time JT 1-2

3 JT iasing Definition: The D voltages applied to a transistor in order to turn it on so that it can amplify the A signal Good ias No ias JT 1-3

4 JT ircuits at D The JT operation mode depends on the voltages at J and J The - characteristics are strongly nonlinear Simplified models and classifications are needed to speed up the hand-calculation analysis JT 1-4

5 D analysis of JT circuits Step 1: assume the operation mode Step 2: use the conditions or model for circuit analysis Step 3: verify the solution Step 4: repeat the above steps with another assumption if necessary JT 1-5

6 D iasing ircuits Fixed-bias circuit mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback circuit JT 1-6

7 Fixed-bias circuit ase-mitter Loop From Kirchhoff s voltage law: + = 0 Solving for base current: ollector-mitter Loop ollector current: / From Kirchhoff s voltage law: JT 1-7

8 xample (1) Design the following circuit so that c = 2 ma and c = 5. For this particular transistor, β =100 and =0.7 JT 1-8

9 Solution To design the circuit, we need to determine values of and We assume JT works in active mode c = 2 ma = (15- c )/ then = 5 kω = 0, = 0.7 = = = = ( -(-15))/ = (β +1)/ β c = 2.02 ma = 14.3/2.02 = 7.07 kω JT 1-9

10 Load Line Analysis The end points of the load line are: sat = / = 0 cutoff = = 0 ma The Q-point is the operating point that sets the values of and JT 1-10

11 ircuit alues Affect the Q-Point JT 1-11

12 ircuit alues Affect the Q-Point JT 1-12

13 ircuit alues Affect the Q-Point JT 1-13

14 xample (2) Given the load line and the defined Q-point, as shown in figure 2-a, determine the required values of,, and for a fixed-bias configuration as depicted at figure 2-b. Figure 2-b Figure 2-a JT 1-14

15 Solution JT 1-15

16 mitter-stabilized ias ircuit Adding a resistor ( ) to the emitter circuit The addition of the emitter resistor to the dc bias of the JT provides improved stability the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions (e.g., temperature) change JT 1-16

17 mitter-stabilized ias ircuit ase-mitter Loop From Kirchhoff s voltage law: Since = ( + 1) : - - ( 1) 0 Solving for : - - ( 1) - / JT 1-17

18 mitter-stabilized ias ircuit ollector-mitter Loop From Kirchhoff s voltage law: 0 Since : Also: ( - ) JT 1-18

19 oltage Divider ias ircuit This is a very stable bias circuit. The currents and voltages are nearly independent of any variations in. JT 1-19

20 Approximate Analysis of oltage Divider ias ircuit Where << 1 and 1 2 : Where > 10 2 : ondition to be tested From Kirchhoff s voltage law: ( ) JT 1-20

21 Problem Design the bias network for the silicon npn JT circuit such that = 1mA, 1 =22k Ω and 2 =2.2kΩ, if the transistor has β equals 100. JT 1-21

22 D ias with oltage Feedback ircuit Another way to improve the stability of a bias circuit is to add a feedback path from collector to base n this bias circuit the Q-point is only slightly dependent on the transistor beta, JT 1-22

23 D ias with oltage Feedback ircuit ase-mitter Loop From Kirchhoff s voltage law: 0 Where << : ' Knowing = and, the loop equation becomes: 0 Solving for : ( ) JT 1-23

24 D ias with oltage Feedback ircuit ollector-mitter Loop Applying Kirchoff s voltage law: + + = 0 Since and = : ( + ) + =0 Solving for : = ( + ) JT 1-24

25 Transistor Switching Networks Transistors with only the D source applied can be used as electronic switches JT 1-25

26 Switching ircuit alculations Saturation current: sat To ensure saturation: sat dc mitter-collector resistance at saturation and cutoff: sat cutoff sat sat O JT 1-26

27 Switching Time Transistor switching times: t on t r t d t off t s t f Times in range of nano-seconds xample Note: npn JT has faster switching time than pnp JT JT 1-27

28 Lecture Summary overed material ontinue JT iasing D analysis Fixed-bias circuit mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback JT switching time Material to be covered next lecture ontinue JT ontinue D analysis More examples ntroduction to ac signal analysis JT 1-28