Lecture 14. Bipolar Junction Transistor (BJT) BJT 1-1

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1 Lecture 14 ipolar Junction Transistor (JT) JT 1-1

2 Outline ontinue JT iasing D analysis Fixed-bias circuit (revision) mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback circuit JT switching time JT 1-2

3 Test Yourself ompare between npn and pnp JT transistors clarifying the main differences Which JT transistor type is more suitable for high speed applications? JT 1-3

4 Quick evision on JT Fixed iasing JT 1-4

5 Load Line Analysis The end points of the load line are: sat = / = 0 cutoff = = 0 ma The Q-point is the operating point that sets the values of and at certain value JT 1-5

6 ircuit alues Affect the Q-Point JT 1-6

7 ircuit alues Affect the Q-Point JT 1-7

8 ircuit alues Affect the Q-Point JT 1-8

9 xample (1) Given the load line and the defined Q-point, as shown in figure 2-a, determine the required values of,, and for a fixed-bias configuration as depicted in figure 2-b. Figure 2-b Figure 2-a JT 1-9

10 Solution JT 1-10

11 mitter-stabilized ias ircuit Adding a resistor ( ) to the emitter circuit The addition of the emitter resistor to the dc bias of the JT provides improved stability the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions (e.g., temperature) change JT 1-11

12 mitter-stabilized ias ircuit ase-mitter Loop From Kirchhoff s voltage law: Since = ( + 1) : Solving for : - - ( 1) ( 1) - / Affected with temperature JT 1-12

13 mitter-stabilized ias ircuit ollector-mitter Loop From Kirchhoff s voltage law: 0 Since : Also: ( - ) JT 1-13

14 xample (2) A bipolar junction transistor having S = A is biased in the forward active region with =750 m. f the current gain (or β) varies from 50 to 200 due to manufacturing variations, calculate the minimum and maximum terminal currents of the device. JT 1-14

15 Solution For a given, the collector current remains independent of β The base current varies from /200 to /50: the emitter current experiences only a small variation because (β+ 1)/β is near unity for large β: JT 1-15

16 oltage Divider ias ircuit This is a very stable bias circuit. The currents and voltages are nearly independent of any variations in. JT 1-16

17 Approximate Analysis of oltage Divider ias ircuit Where << 1 and 1 2 : Where > 10 2 : ondition to be tested From Kirchhoff s voltage law: ( ) JT 1-17

18 Problem Design the bias circuit shown in the figure for the silicon npn JT such that = 1mA, 1 =22k Ω and 2 =2.2kΩ, if the transistor has β equals 100. JT 1-18

19 D ias with oltage Feedback ircuit Another way to improve the stability of a bias circuit is to add a feedback path from collector to base n this bias circuit the Q-point is only slightly dependent on the transistor beta, JT 1-19

20 D ias with oltage Feedback ircuit ase-mitter Loop From Kirchhoff s voltage law: 0 Where << : ' Knowing = and, the loop equation becomes: 0 Solving for : ( ) Then / ( ) JT 1-20

21 D ias with oltage Feedback ircuit ollector-mitter Loop Applying Kirchoff s voltage law: + + = 0 Since and = : ( + ) + =0 Solving for : = ( + ) JT 1-21

22 Transistor Switching Networks Transistors with only the D source applied can be used as electronic switches JT 1-22

23 Switching ircuit alculations Saturation current: sat To ensure saturation: sat dc mitter-collector resistance at saturation and cutoff: sat cutoff sat sat O JT 1-23

24 Switching Time Transistor switching times: t on t r t d t off t s t f Times in range of nano-seconds xample Note: npn JT has faster switching time than pnp JT JT 1-24

25 Lecture Summary overed material ontinue JT iasing D analysis Fixed-bias circuit mitter-stabilized bias circuit oltage divider bias circuit D bias with voltage feedback JT switching time Material to be covered next lecture ontinue JT ontinue D analysis More examples ntroduction to A signal analysis JT 1-25

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