3. RESISTOR - TRANSISTOR LOGIC CIRCUITS 3.1 AN RTL NOT GATE

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1 3. ESSTO - TANSSTO LOG UTS When a transistor is used in conjunction with resistors to create a logic circuit, it is usually referred to as a resistor-transistor logic or TL for short. n a logic circuit, the transistor operates as a switch. n order to simulate an open switch, the transistor current must be zero. n other words, the transistor must operate at its cut-off point. This condition is met when the base current is zero. We also know that when the transistor operates in the saturation region, the collector-toemitter voltage drop is very small (usually 0.2 V or so). The operation of the transistor in the saturation region corresponds to the closed position of the switch. This condition is met when i << β where β is the unsaturated common-emitter current gain of the transistor, i is the i total collector current, and i is the total base current. For example, let us assume that i = 0.1 ma and β = 100. Then, i would be 10 ma when the transistor operates in the active region and the collector-to-emitter voltage is usually greater than V E(sat). However, if i is only 5 ma when i is still 0.1 ma, the transistor then operates in the saturation region. The collector-to-emitter voltage drop is equal to V E(sat). n this case, the saturated common-emitter current gain βsat is 50. Thus, when the transistor operates in the saturation region, βsat < β. This criterion can be used to design a transistor circuit that operates as a switch. 3.1 AN TL NOT GATE As defined earlier, the output signal of a NOT logic (gate) is the complement of the input signal. That is, when the input signal is low [0], the output signal is high [1] and vice versa. A NOT gate can be easily obtained by means of an inverting amplifier circuit as shown in Figure 3.1. Design Example efore we design the components of the circuit given in Figure 3.1, let us define some reference voltages. To turn ON a transistor that is in its OFF state, we need a relatively small baseto-emitter voltage called the cut-in or turn-on voltage. We will denote it as V E(ON) and assume it to be 0.6 V. Once the transistor is ON and operates in the active region, it is common to assume V E = 0.7 V. As the input voltage increases and moves the transistor operation in the saturation region, its base-to-emitter voltage changes as well. Unless it is mentioned otherwise, we will assume that the base-to-emitter voltage in the saturation region is V E(sat) = 0.8 V. The increase in the base-to- 11

2 emitter voltage in the saturation region is attributed to the increase in the charge stored by the base-emitter junction capacitance. Likewise, we will assume that the cut-in voltage for the diode is also 0.6 V because most diodes in the chip are created by connecting the base and collector terminals together. When the diode is conducting, we will assume that the voltage drop across it is 0.7 V. All this information is given in Table 3.1. Table 3.1: eference voltages for a diode and a JT Diode: ut-in (turn-on) voltage V D(ON) 0.6 V Forward voltage drop V D 0.7 V Transistor: ase-to-emitter cut-in (turn-on) voltage V E(ON) 0.6 V ase-to-emitter voltage in the active region V E 0.7 V ase-to-emitter voltage in the saturation region V E(sat) 0.8 V ollector-to-emitter voltage in the saturation region V E(sat) 0.2 V n the above table, the values are given for the NPN transistor. They are also valid for a PNP transistor for the reversed subscripts. That is VE(ON) = 0.6 for a PNP transistor. v V 0 in t v in + V v o V v o v E(sat) t Figure 3.1: JT as a NOT gate 12

3 We are now ready for the design. Let us assume that V = 5 V, V = 5 V, and β = 100. Since there is no other constraint upon the selection of resistors in the circuit, let us select that the resistance in the base circuit is = 10 kω. When the input voltage v in is equal to V = 5 V, we can compute the base current in ma as = = 0.42 ma 10 For the transistor to operate in the active region, the collector current must be 42 ma (β ). Since we would like to insure that the transistor operates in the saturation region, the collector current must be less than 42 ma. The minimum value of the collector resistance that would force the transistor to operate at the verge of saturation is = = kω 42 ma Any standard value for greater than kω will force the transistor to operate in the saturation region. The selection of may also depend upon some other constraints. Since these constraints are not given, we can choose any value greater than kω. We know that the common-emitter current gain can vary from 50% to 150% of its typical value. Taking that into consideration, let us select a standard value of 470 Ω for this application. For = 470 Ω, ( sat ) = = ma The common-emitter current gain (saturation region): β sat = = The output of this circuit is 0.2 V when the input signal is 5 V. This, therefore, is the low value of the output signal. On the other hand, when the input signal is 0 V, the output voltage is 5 V. This is the high value of the output signal. The power dissipation when the transistor operates in the saturation region is P D = ( 5 V )( ma ) + ( 5 V )( 0.42 ma ) = mw The transistor does not dissipate power when the input voltage is low and the transistor operates in the cutoff region. 13

4 VOLTAGE TANSFE HAATEST The voltage transfer characteristic is nothing but a sketch of the output voltage as a function of the input voltage. n this case, the input voltage is increase from 0 to its maximum value (V ). When the input voltage is zero, the transistor is OFF and the output voltage is 5 V. This is the maximum output voltage that we can obtain for this circuit. Let us label this voltage as V OH. The transistor remains in its cutoff state (OFF) as long as the input voltage is less than 0.6 V. As soon as the input voltage reaches 0.6 V, the transistor is ready to turn ON. Thus, 0.6 V is the maximum input voltage that we can apply to the transistor and keep it in its cutoff mode. Let us label it is V L. These voltages are shown in Figure 3.2. v o (V) V = 5 OH V = 5 OL Figure 3.2: V = 0.6 L V = 1.82 H Transfer characteristic of an TL gate v in (V) When the input voltage increases above 0.6 V, the transistor enters its active region. As soon as the input voltage goes above 0.7 V, the base-to-emitter voltage in the active region is 0.7 V. The remainder of the applied voltage is the voltage drop across, which results in the base current and thereby the collector current. As the collector current begins to flow in the transistor, the output voltage begins its decline. As the input voltage increases, the base current increases, the collector current increases, and the collector-to-emitter voltage decreases. The operation in the active region continues until the collector-to-emitter voltage becomes equal to its saturation voltage. The transistor is now at the verge of saturation. The collector current is ma. f β = 14

5 100, the base current is ma. Let us denote the input voltage that forces the transistor to enter the saturation region as V H. Note that V H is the minimum value of the high-input voltage and is given as V ) H = + VE(SAT = ( ma)(10 kω) = 1.82 V f we denote the corresponding low output voltage as V OL, then V OL = V E)sat) = 0.2 V. These voltages are also shown in Figure 3.2. As the input voltage increases above 1.82 V, the output remains at 0.2 V and the transistor goes into deep saturation. The operation in the deep saturation region continues until the input voltage reaches its maximum value. Summary: n the above discussion we have defined some terminology pertaining to the TL circuit. We will use this terminology for all types of gates. Therefore, let us formally define it. V OH = Nominal High Output Voltage This is the output voltage that corresponds to logic 1 (high) and it may vary with the loading and temperature. The manufacturers usually specify its minimum value in order to compensate for the component tolerances and variations in the loading conditions. V OL = Nominal Low Output Voltage This is the gate output voltage that corresponds to logic 0 (low). The manufacturers usually specify its maximum value. V H = High input voltage at which dvo/dt = 1 The minimum input voltage that is interpreted as logic 1 (high) by the gate. V L = Low input voltage at which dvo/dt = 1 The maximum input voltage that is interpreted as logic 0 (low) by the gate. Transition egion: The region between V L and V H is called the transition region. Transition region is mostly the active region and it is the forbidden region for the logic circuit. The input voltage should either be low (less than or equal to V L ) or high (greater than or equal to V H ). f there is a random noise in the system, it should be small enough such that it does not drive the transistor into the forbidden region. Transition Width: t is the difference between the two input voltages (V H V L ). For TL gate, the transition width is 1.22 V. Logic Swing: The difference between the two output voltages (V OH V OL ) is designated as the logic swing. For the TL under discussion, the logic swing is 4.8 V. 15

6 NOSE MAGNS The input signal to a gain can be corrupted by some unwanted and unexpected signal. f the gate is not properly designed the unwanted signal can force the gate to malfunction. A noise margin is the figure of merit for the gate. The higher the noise margin, the less susceptible the gate to malfunction. We define the noise margin for each level of the input signal. Thus, we have the definitions for the lower- and upper-noise margins for the low- and high-level of the input signal. These margins are defined as follows: The Lower Noise Margin: NML = V L V OL y definition, it is the difference between the maximum allowed input voltage that can be interpreted as low by the gate and the actual low output voltage of the preceding stage driving the gate. For the TL circuit we just analyzed, the maximum input voltage that can be interpreted by the gate as low is 0.6 V. The gate usually receives the input signal from the other gate whose minimum output is 0.2 V. Then the lower noise margin is 0.4 V ( ). Keep in mind that each gate generates a random noise voltage, however small it may be. For the TL gate under discussion, the largest random noise voltage that can corrupt the low input signal is 0.4 V. The reason, of course, is that when the random noise voltage is added to the input voltage, the total voltage should be less than or equal to the maximum input voltage that is interpreted as low by the gate. Since the actual input signal voltage is 0.2 V, the maximum input voltage that can be added to it is 0.4 V, which is simply the lower noise margin. The Upper Noise Margin: NMH = VOH VH y definition, it is the difference between the actual output voltage of the preceding stage driving the gate and the minimum value of the input voltage that can be interpreted as high by the gate. For the TL gate under discussion, the maximum input voltage is V = 5 V. The minimum input voltage that the gate can interpret as high is 1.82 V. Then, the upper noise margin is 3.18 V (5 1.82). This simply means that the largest random noise voltage that the gate can tolerate is 3.18 V. The logic circuit should still be able to interpret the input voltage as high when the upper noise margin is subtracted from the input signal. All our discussion pertains to a single TL circuit. When it is used as a driver for other gates, its noise margins are bound to change, as we will show later. 16

7 3.2 AN TL NO GATE As mentioned earlier, a NO logic (gate) is nothing but an O logic followed by a NOT logic. esistor-transistor logic can be designed to easily perform both functions. For instance, a two-transistor JT NO gate can be set up as shown in Figure V A 1 Q 1 2 Q 2 Figure 3.3: A TL NO gate Let us assume that the two transistors are identical, the two base resistors are equal (1 = 2), and the two input signals vary between the same minimum and maximum values. The operation of the circuit can now be explained as follows: 1. When inputs A and are low [0], both transistors Q1 and Q2 are cut-off and the output voltage is V [high, 1]. 2. When both inputs are high [1], both transistors are saturated and carry equal currents, and the output voltage is V E(sat) [low, 0] 3. When one of the inputs is high [1] and the other is low [0], then the transistor with the high input operates in the saturation region while the other is cutoff. The transistor that operates in the saturation region carries the current and the voltage drop across it is V E(sat) [low, 0]. Thus, the output is low [0]. 17

8 The voltage levels for each logical possibility are tabulated below when V = 5 V. We have also assumed that the maximum value of each input signal is 5 V. The corresponding truth table is also shown where 0.2 V is interpreted as 0 and 5 V as 1. Voltage levels Truth table A A The examination of the logical entries for the output signal reveals that the output signal is high only when both the inputs are low. For all other logical combinations, the output signal is low. These are the traits of a NO (NOT-O) logic circuit. We can express the NO operation in terms of oolean algebra as = A + We can use the components of the NOT circuit designed earlier (Figure 3.1) for the NO gate under discussion. The collector current when only one transistor operates in the saturation region is still ma. The corresponding base current is 0.42 ma. n this case, the operation in the saturation region of the transistor is not affected at all. On the other hand, when both transistors operate in the saturation region, the collector current in each transistor is ma and the base current is still 0.42 ma. onsequently, βsat is now This represents the highest level of saturation for each transistor. From the above discussion we conclude that the level of saturation of a JT transistor in the NO logic circuit increases with the increase in the number of input stages when all transistors operate in saturation region. 18

9 3.3 AN TL NAND GATE An TL NAND (NOT AND) circuit for three input signals A,, and is given in Figure 3.4. The output voltage D is low only when all the inputs are high. When the input to any one of the three transistors is low, that transistor operates in the cut-off region and behaves like an open circuit and the output voltage is high. These are the traits of the NAND logic. + 5 V D A Q 1 Q 2 Q 3 Figure 3.4: An TL NAND gate where D = A Example: TL NAND Gate n the circuit of Figure 3.4, = 50 kω, = 2.2 kω, the common-emitter gain in the active region is 100, V E(sat) = 0.8 V, and V E(sat) = 0.2 V. Show that all the transistors operate in the saturation region when they conduct. Assume that the maximum value of each input signal is 5 V. Solution: The three transistor conduct only when all the inputs are high, i. e., A = = = 5 V. Let us assume that each transistor operates in the saturation region when it conducts (ON). Then the collector-to-emitter voltage for each transistor is 0.2 V. 19

10 n the following calculations, all currents are in ma and all resistors are in kω. Let us use subscripts 1, 2, and 3 for Q1, Q2, and Q3, respectively. The collector and base currents for Q1 is Thus, = = 2 ma = = ma 50 2 β sat, Q1 = = Since βsat,q1 is less than the given value of 100 in the active region, Q1 operates in the saturation region. The collector and base currents for Q2 are Thus, = ma = = 0.08 ma β at, Q2 = = The transistor Q2 also operates in the saturation region. The collector and base currents for Q3 are Thus, = ma = = ma β at, Q3 = = Thus, Q3 also operates in the saturation region. Therefore, our assumption is verified. When all the three transistors are ON, the output voltage is 0.6 V. As long as 0.6 V is recognized as a low, the logical output for D is 0. n all other cases, the output voltage is 5 V and that can be recognized as a logical output for D as 1. 20

11 A MULT-NPUT TL-NO GATE WTH A APATVE LOAD Figure 3.5 shows a simple TL-NO gate with three inputs. t drives a capacitive load as shown where T is not only the stray capacitance of the gate but also includes the effective capacitance of the N base-to-junction capacitors of the gates driven by it. V V o A Q1 Q2 Q3 T Figure 3.5: A three-input TL-NO gate with capacitive load Let us assume that at least one of the three inputs is high [1] and that transistor is in saturation. Therefore, the output voltage across T is the collector-to-emitter saturation voltage of that transistor [V E(sat) 0.2 V]. Therefore, the output voltage V O of the gate is low [0] and it will remain in that state as long as one of the three inputs is high. Let us now suppose that all the three inputs are low [0]. We expect the output voltage V O to be high [1] because each transistor would be in its cutoff mode. t is a known fact that the voltage drop across a capacitor (when there is a resistor in series with it) cannot change suddenly from V O to V. The output voltage across T rises toward V with a time constant τ such that τ = T. For all practical purposes, it takes about 5τ for the capacitor to charge to V. The smaller the value of, the faster is the rate of charge of the capacitor. However, the power dissipation increases with the decrease in. ommercially available TL gates are rated as medium-power TL-gate (MTL) and low-power TL gate (LTL). Typical values of the resistors in these gates are tabulated below. 21

12 These gates are designed to operate from a 3-V dc supply. The low output voltage is usually about 0.2 V (200 mv). However, when the transistor is in its extreme saturation mode, it can drop to as low as 60 mv. Gate-type (Ω) (Ω) MTL LTL The resistor is referred to as the pull-up resistor because it helps the capacitor to attain its high voltage. Since the resistor is a passive element, the pull-up resistor is also known as the passive pull-up resistor. V V A N N (a) (b) Figure 3.6: (a) TL gate with a fan out of 5, and (b) its equivalent circuit 22

13 With the passive pull-up resistor, the manufacturer conservatively specifies the fan out as 5. The base-to-emitter junction capacitance is generally specified as 5 pf. The circuit with a fan out of 5 is shown in Figure 3.6. When the fan out is 5, the total capacitance is then T = 25 pf. For the MTL gate, the base resistance is 450 Ω. When the fan out is 5, the equivalent base resistance is 90 Ω (450/5). The total resistance in the charging circuit is 730 Ω [ + /N, where N is the fan out]. Thus, the time constant is about ns. 3 V 3 V 640 Ω 100 Ω 450 Ω Q2 A 450 Ω Q1 O O 450 Ω 450 Ω Q3 Figure 3.7: An TL buffer Fan out The charging time can be considerably improved by using an active pull-up circuit of the type given in Figure 3.7. This circuit is referred to as an TL buffer. This is how it works. When the input at A is high, Q1 operates in the saturation region and Q2 is OFF. The saturation level of Q3 is in its extreme and the output is low. 23

14 When the input A is low, Q1 and Q3 are OFF. Q1 is a logic inverter and it helps Q2 to turn ON when the input is low. When Q2 operates in the saturation mode, there is about 0.2-V drop across it. The transistor Q2 now supplies the charging current to the N gates. Since Q2 is an active device, it is called the active pull-up transistor. nstead of a 640-Ω resistor for to control the current in the circuit, we now have a 100-Ω resistor. A low value of helps improve the time constant. For N = 5, the improved time constant is 4.75 ns. We can also look at the improved version from a different perspective. What is fan out of the active pull-up TL-buffer if its time constant is the same as that for the passive pull-up gate with a fan out of 5? The time constant for a passive pull-up TL gate has already been computed as ns. Let N A be the fan out for the active pull-up buffer for its time-constant to be the same as that for the passive pull-up TL gate. That is, N N A A = Substituting = 5 pf, we obtain N A = 32. Thus, the active pull-up buffer has improved the fan out by a factor of 6.4 (32/5). The conservative fan out for the TL buffer as specified by its manufacturer is 25. How do we really know that Q2 is in saturation when the input at A is low? To answer this question, let us first imagine that Q2 operates in the active region. Let us assume that its β = 50. Then the output current O for a fan out of N is N O = = ma (3.1) N N Now let us assume that Q2 is saturated and its collector-to-emitter saturation voltage is 0.2 V. We have to write coupled equations in terms of the collector current (sat) and the base current (sat) for Q2 as follows N N 9 = (sat) (sat) = 0.45 N Solving these equations, we obtain N = (sat) (sat) =

15 (sat) 140 N 270 = 109 N ma and (sat) 2180 N = 109 N ma Finally, the output current, when Q2 is saturated, is = + O(sat) (sat) (sat) O(sat) 2320 N N = = ma (2) 109 N N We can now compute the currents for various values of N. The following table shows these calculations for N = 1, 2, and 3. N Active region Saturation region onclusion ma 3.6 ma Active region ma ma Approaching saturation ma ma Saturation Since βsat β when the transistor operates in the saturation mode, we expect O(sat) to be lower in the saturation region than O in the active region. Note that when N = 1, the transistor operates in the active region because the computed current in the saturation region is more than that in the active region. This operation does not pose a problem because the fan out is usually more than 1. The transistor operates almost near the saturation region as soon as the fan out is 2. The transistor definitely operates in the saturation mode for N = 3. Thus, as long as N 3, the transistor Q2 operates in the saturation region. 25