Session 4: Analog Circuits. BJT Biasing Single stage amplifier

Transcription

1 Session 4: Analog ircuits JT iasing Single stage amplifier 1

2 Outline JT Amplifier 2

3 JT: ipolar Junction Transistor i D A p D n R F F : Forward R : Reverse V D p n p n p n : F 2 : R Active V 1 : F 2 : F Saturation 1 2 Qp utoff 1 : R 2 : R Reversed 1 : R 2 : F V Qn 3

4 JT: ipolar Junction Transistor A p D n i D V D Qn / Δ Δ2 2 / / Δ Δ2 2 / 4

5 JT onfigurations : ommon mitter : ommon ase : ommon ollector Qn Qn Qn Input haracteristic vs. for different Output haracteristic vs. for different or Transfer haracteristic vs. or for different 5

6 : ommon mitter Qn Input haracteristic 0 0 very little dependence to output voltage Output haracteristic arly voltage Saturation Active: Active utoff 6

7 : Transistor Model Qn Saturation utoff Output haracteristic SOA: Safe Operatin g Area 0.2 7

8 : Output haracteristic Ideally linear: SPI Qn 1 Saturation utoff 1 8

9 eta : urrent Gain 9

10 : ommon ase Qn Output haracteristic Saturation 0.4 Input haracteristic Active utoff Active: 1 very little dependence to output voltage Δ Δ2 10

11 Large Signal Model Qn Saturation 2 1 Active Saturation 0.2~ ideal ideal

12 Voltage Amplifier Qn 0.1v 10v 1 cutoff active saturation 12

13 iasing: V = cte 0.1v 10v cutoff active saturation 13

14 iasing: I = cte For max swing: For max gain: ~ 5 ~ ~ 5Ω ~ 9.7Ω Ω What is the problem? Replace it with transistor with

15 iasing: I = cte For max swing: ~ 5 430Ω Negative feedback! 15

16 iasing: I = cte independent of ~ 2.7 4Ω Ω 10 5Ω 10v Where is the tradeoff?

17 iasing: I = cte Ω Ω Assume: Ω Ω 4Ω Ω? This is for design how about analysis 17

18 iasing: I = cte Ω Ω Ω 1 2Ω Assume: What if was 10! 10 KVL / 1 1 For the above numbers:

19 iasing: I = cte D similar Only in Integrated ircuits! / 1 / 1 area 19

20 iasing: xample 01 15V kΩ Q1 5.6kΩ Q2 3.9kΩ [ma] [V] kΩ / kΩ 3.3kΩ 1 15V Q1 5.6kΩ kΩ 9.89 KVL / 15V Q2 3.9kΩ kΩ KVL 3.3kΩ /

21 iasing: xample 02 Vcc=10V kΩ Q [ma] [V] Q Ω

22 iasing: xample Vcc=9V 3.3 kω 2.2 kω Q Q [ma] [V] 3.3 kω V 2.2 kω kΩ kω Q1 0.7 Q2 47kΩ kω 22

23 iasing: xample 04 Vcc=10V kω kω kω Q2 Q1 3.9 kω kω 1.1 [ma] [V] Find bias points if 8.2 Ω Q2 8.2 kω [ma] [V]

24 Linear JT Amplifier V V in R Qn V o 1 sin 1 sin 2 sin sin 24

25 JT Small Signal Model (hπ) Qn Input resistance: Output resistance: Tranceonductance: 1 25

26 xample 01 D: A: Ω Assume Design for Find,, window for ~ cutoff saturation and maximum swing 10? 5 5Ω 0.2~0 ~ ollector resistance mitter s circuit resistance if 0: 26

27 xample 02 1Ω Ω Ω 6 2 2Ω 4Ω 1 Assume A circuit 100 ~ Find,, : ~20Ω

28 xample 02 1Ω 10 73Ω 27Ω 4Ω 2Ω 1.8 How we can increase gain? 1Ω 10 73Ω 27Ω 4Ω 2Ω ypass capacitance 28

29 xample Design a buffer A circuit : 1 window for saturation cutoff 5Ω 0 9.3~10? Ω ~1 29

30 xample

31 xample 04 Multistage Amplifier 1Ω 73Ω 27Ω 10 2Ω 930Ω Design an amplifier: Ω Ω 10 1Ω A circuit 1Ω 20Ω Ω 930Ω 5Ω Ω 1Ω buffer 5Ω 31

32 xample 05,, A circuit ?

33 ommon ase

34 xample 05,, Ω 34

35 ascode Amplifier, neglecting base current A circuit:

36 Some Notes: 36

37 Summary

38 ? V A

39 Input / Output Impedances Input port Output port 39