Pb-free lead plating; RoHS compliant. PG-DIP-14-1 Adjustable reference voltage V Stab. Type Ordering Code Package

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1 Window iscriminator T 965 Pb-free lead plating; RoHS compliant ipolar I Features Two window settings direct setting of lower and upper edge voltage (window edges) indirect setting by window center voltage and half window width djustable hysteresis igital outputs with open collectors for currents up to 5 m PG-IP-4- djustable reference voltage Stab Type Ordering ode Package T 965 Q6- PG-IP-4- Not for new design The window discriminator compares an input voltage to a defined voltage window. The digital outputs show whether the input voltage is below, within or above this window. The T 965 window discriminator is especially suitable as a tracking or compensating controller with a dead band in control engineering and for the selection of voltages within a certain tolerance of the required setpoint value in measurement engineering. When it is used as a Schmitt trigger, switching frequencies up to a typical value of 5 khz are possible. Semiconductor Group 5--

2 _< T 965 Functional escription mplifier mp increases the voltage of the reference source R to Stab = x REF. The amplification factor can be altered by external wiring. With direct setting of the window, the input voltage appears on amplifier mp ( ), the upper edge voltage on comparator K ( 6 ) and the lower edge voltage on comparator K ( ). With indirect setting of the window, the input voltage appears on inputs 6 and, while the center voltage is connected to amplifier ( ). The voltage applied to the input ( 9 ) of amplifier mp is subtracted symmetrically from the output voltage of amplifier mp and added. The comparators switch with hysteresis. The logic gates have open-collector outputs. If the inhibit input or is connected to ground, output or will always be high. +S REF 5 k Ω k Ω R mp _ + Stab _ + + _ K 4 Inhibit mp = mp = _ + + _ K 4 Inhibit IE9 Outputs,,, are open-collector lock iagram Semiconductor Group 5--

3 T 965 Pin onfiguration (top view) T 965 GN 4 Inhibit REF IEP9 Inhibit + S Stab 9 Pin efinitions and Functions Pin Symbol Pin Function in irect Setting Indirect Setting 4 5 GN Inhibit REF of Window GN Logic output Logic output (N) onnected to GN: logic output = HIGH Internal REF = Upper edge voltage Lower edge voltage Input voltage GN Input voltage 6/ Input voltage 6/ enter voltage Half window width 4 Stab + S Inhibit Internal Stab = 6 Supply voltage onnected to GN: logic output = HIGH Logic output (NN) Logic output Semiconductor Group 5--

4 T 965 bsolute Maximum Ratings Maximum ratings for ambient temperature T = 5 to 5 Parameter Symbol Limit alues Unit min. max. Supply voltage (pin ) ifference in input voltage between pins 6,, Input voltage (pins 6,,, 9) S I I 5 Output current (pins,,, 4) I Q 5 m Output voltage (pins,,, 4) independent of S oltage on REF (pin 5) Q R Output current of stabilized voltage (pin ) I m Inhibit input voltage (pins 4, ) IH Junction temperature Storage temperature T j T stg Thermal resistance system - air PG-IP-4- R th S K/W Operating Range Supply voltage S 4.5 mbient temperature T 5 5 Semiconductor Group 4 5--

5 T 965 haracteristics S = ; T = 5 Parameter Symbol Limit alues Unit Test ondition min. typ. max. Test ircuit urrent consumption Input current (pins 6,, ) Input current, pin 9 I S I I I I m n n, = QH Input offset voltage in direct setting of window Input offset voltage in indirect setting of window Input-voltage range on pins 6,, Input-voltage range on pin 9 ifferential input voltage IO IO I I 6 ( 9 ) ( + 9 ) S S / m m m I < Reference voltage Stabilized voltage on pin T of reference voltage Sensitivity of reference voltage to supply-voltage variation 5 α 5 5 / S m/k m/ I REF = S >.9 Output reverse current I QH µ Output saturation voltage Hysteresis of window edges Inhibit threshold QL U L 4, 5 5. m m m I Q = m I Q = 5 m Inhibit current I 4, µ Switching frequency f dir f ind 5 khz khz Semiconductor Group 5 5--

6 T 965 S Ι S R L R L R L R L Ι 6 6 Ι QH Ι QH Ι QH Ι T Ι QH4 Ι 5 = = = QL4 QL QL QL Ι 9 IES6 = = 4 Test ircuit irect Setting of Window Semiconductor Group 6 5--

7 T 965 S Ι S R L R L R L R L 6 Ι QH 9 T Ι QH Ι QH Ι QH4 = = = 6/ QL4 QL QL QL = = 4 IES Test ircuit Indirect Setting of Window by enter oltage and Half Window Width Semiconductor Group 5--

8 T 965 Inhibit Inputs 4, S 4, Outputs, 4, Ω k Ω GN High > Not permitted open Normal function >. Low Inputs 6,, Input 9 6,, kω 9 Outputs,,, 4 Outputs REF, Stab Stab R Q REF IES Schematic ircuit iagrams Semiconductor Group 5--

9 T 965 S R R R T 965 R 5 Ι R 6 4 R R IES94 To increase the switching frequency, pin 9 may be grounded via R ( 9 approx....4 m). pplication ircuit irect Setting of Lower and Upper Edge oltages 6 9 = Upper edge voltage + 9 = Lower edge voltage = Input voltage Semiconductor Group 9 5--

10 T 965 L U t IES96 efinition of the Offset oltage IO L + U = Semiconductor Group 5--

11 T 965 Upper Edge 6 Lower Edge t L t U t Pin 4 on GN Inhibit. < Pin 4 < Pin on GN Inhibit. < Pin < t L t U t L t U IES95 pplication ircuit irect Setting of Lower and Upper Edge oltages Semiconductor Group 5--

12 T 965 S R R R 5 R T 965 Ι R R R 4 IES9 pplication ircuit Indirect Setting of Window by enter oltage and Half-Window Width 6 = = Input voltage = enter voltage 9 = Half window width Semiconductor Group 5--

13 T 965 L U t - 9 = L - U - ( - 9 ) IES99 efinition of the Offset oltage IO L + U = ( 9 ) Semiconductor Group 5--

14 T 965 Upper Edge 6 Lower Edge t L t U t Inhibit Pin 4 on GN. < Pin 4 < Inhibit Pin on GN. < Pin < t L t U t L t U IE9 pplication ircuit Indirect Setting of Window by enter oltage and Half-Window Width Semiconductor Group 4 5--

15 T 965 S R R L R L R L 6 4 Ι R T 965 R 4 9 R P= R 5 H H 6 IES9 pplication ircuit Symmetrically Enlarged Edge Hysteresis in irect Setting of Window alculation of Hysteresis H R H 5 = R 4 + R R 4 + R m R + R + R Semiconductor Group 5 5--

16 T 965 S R R L R L R L Ι 6 T R 5 R R R 4 9/ 9/ H = 9/ - 9/ 6/ IES9 pplication ircuit 4 Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window alculation of Hysteresis H H = 9/ 9/ R 9/ 4 R 5 = R + R 4 R 5 R 9/ 4 = R + R 4 Semiconductor Group 6 5--

17 T 965 PG-IP-4- (Plastic ual In-line Package) GP55 Sorts of Packing Package outlines for tubes, trays etc. are contained in our ata ook Package Information. imensions in mm Semiconductor Group 5--