Power-Factor Controller (PFC) TDA 4862 IC for High Power Factor and Active Harmonic Filter

Transcription

1 Power-Factor Controller (PFC) TDA 486 IC for High Power Factor and Active Harmonic Filter Advanced Information Bipolar IC Features IC for sinusoidal line-current consumption Power factor approaching Controls boost converter as an active harmonics filter Internal start-up with low current consumption Zero current detector for discontinuous operation mode High current totem pole gate driver Trimmed ±.4% internal reference Undervoltage lock-out with hysteresis ery low start-up current consumption Pin compatible to world standard Fast overvoltage regulator Current sense input with internal low pass filter P-DIP-8- P-DSO-8- Type Ordering Code Package TDA 486 Q67-A8368-A P-DIP-8- TDA 486 G Q676-A8369-A73 P-DSO-8- = New type Semiconductor Group

2 Description The TDA 486 is excellent convenient for designing a preconverter in ballasts and switched mode power supplies with sinusoidal line current consumption and a power factor approaching unity. The TDA 486 controls a boost converter as an active harmonics filter in a discontinuous mode (free oscillating triangular shaped current mode). The TDA 486 comprises an internal start-up timer, a high gain voltage amplifier, an one quadrant multiplier for approaching unity power factor, a zero current detector, PWM and logic circuitry, and totem pole MOSFET gate driver. Protective features are: input undervoltage lockout with hysteresis, CC zener clamp, cycle-by-cycle current limiting, output voltage limiting for fast and slow load changes up to open circuit, and a sinking gate driver current activated whenever undervoltage mode occurs. The output voltage of this preconverter is regulated with high accuracy. Therefore the device can be used for world-wide line voltages without switches. The TDA 486 is the improved version of the TDA 487 with a pinout equivalent to world standard. TDA 486 G TDA 486 SENSE AOUT MULTIN Ι SENSE IEP748 CC GTDR 6 GND DETIN SENSE AOUT MULTIN Ι SENSE CC GTDR GND DETIN IEP749 Figure Pin Configuration (top view) Semiconductor Group

3 Pin Definitions and Functions Pin Symbol Function SENSE oltage Amplifier Inverting Input; SENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to AOUT it forms an integrator. AOUT oltage Amplifier Output; AOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage will be clamped at. Input voltage less than. is inhibiting the gate driver. If the current flowing into this pin is exceeding an internal defined margin the multiplier output voltage is reduced to prevent the MOSFET from overvoltage damage. 3 MULTIN Multiplier Input; MULTIN is the second multiplier input and connected via a resistive divider to the rectifier output voltage. 4 I SENSE Current Sense Minus; I SENSE is connected to a sense resistor controlling the MOSFET source current. The input is internally clamped at.3 to prevent negative input voltage interaction. An internal low pass filter suppresses voltage spikes when turning the MOSFET on. DETIN Zero Current Detector Input; DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current. 6 GND Ground; All voltages are measured with respect to GND. CC should be bypassed directly to GND with a. µf or larger ceramic capacitor. 7 GTDR Gate Drive Output; GTDR is the output of a totem-pole circuitry for direct driving a MOSFET. A clamping network bypasses low state source current and high state sink current. 8 CC Positive Supply oltage; CC should be connected to a stable source slightly above the CC turn-on threshold for normal operation. A nf or lager ceramic capacitor connected to CC absorbs supply current spikes required to charge external MOSFET gate capacitances. Semiconductor Group

4 Functional Description Introduction Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier and bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitor s voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: the apparent power is higher than the real power that means low power factor condition, the current spikes are non-sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary. With the TDA 486 preconverter a sinusoidal current is achieved which varies in direct instantaneous proportion to the input voltage half sine wave and means a power factor near. This is due to the appearance of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC standard. Operating Description The TDA 486 contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer and an undervoltage lockout circuitry. These functional blocks are described below. oltage Amplifier The voltage amplifier is internally compensated and yields a gain bandwidth of.8 MHz and a phase margin of 8 degrees. The non-inverting input is biased at. and is not pinned out. The inverting input is sensing the output voltage via a resitive devider. The voltage amplifier output AOUT and the inverting input SENSE are connected in a simplest way via an external capacitor. It forms an integrator which monitors the average output voltage over several line cycles. Typically the bandwidth is set below Hz. ln order to keep the output voltage constant the voltage amplifier output is connected to the multiplier input for regulation. Overvoltage Regulator Fast changes of the output voltage can t be regulated by the integrator formed with the voltage amplifier This occurs during initial start-up, sudden load removal, or output arcing and leads to a current peak at the voltage amplifier input while the voltage amplifier s differential input voltages remains zero. The peak current is flowing through the external capacitor into AOUT. Exceeding an internal defined margin causes a regulation circuitry to reduce the multiplier output voltage. Semiconductor Group

5 Functional Description (cont d) MuItiplier A one quadrant multiplier is the crucial circuitry that regulates the gate driver with respect of the DC output voltage and the AC haversine input voltage of the preregulator. Both inputs are designed for good linearity over a wide dynamic range, to 4. for the MULTIN and. to 4. for the AOUT. Current Sense Comparator and RS Latch The multiplier output voltage is compared with the current sense voltage which represents the current through the MOSFET. The current sense comparator in addition with the logic ensures that only a single pulse appears at the drive output during a given cycle. The multiplier output and the current sense threshold are internally clamped at.3. So the gate drive MOSFET is protected against critical operating, as they occur during start up. To prevent the input from negative pulses a special protection circuitry is implemented. Switch-on current peaks are reduced by an internal RC-Filter. Zero Current Detector The zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time is initiated immediately when the inductor current has reached zero. This diminishes the reverse recovery losses of the boost converter diode. Output switch conduction is terminated when the voltage drop of the shunt resistor reaches the threshold level of the multiplier output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current. To prevent false tripping the zero current detector is designed as a Schmitt trigger with a hysteresis of.6. An internal clamp protects the input from overvoltage breakdown, a.6 clamp prevents substrate injection. An external resistor must be used in series with the auxiliary winding to limit the current through the clamps. Timer A restart timer function was added to the IC to eliminate the need for an oscillator when used in stand-alone applications. The timer starts or restarts the TDA 486 if the drive output has been off for more than µs after the inductor current reaches zero. Semiconductor Group

6 Functional Description (cont d) Undervoltage Lockout An undervoltage lockout circuitry enables the output stage when CC reaches the upper threshold CC and terminates the output stage when CC is falling below the lower threshold CCL. In the standby mode the supply current is typically 7 µa. An internal clamp has been added from CC to ground to protect the IC from an overvoltage condition. The external circuitry is created with a start-up resistor connected from CC to the input supply voltage and a storage capacitor from CC to ground. Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode. Output The TDA 486 totem pole output stage is MOSFET compatible. An internal protection circuitry is activated when CC is within the stand by mode and ensures that the MOSFET is turned-off. The totem pole output has been optimized to minimize cross conduction current during high speed operation. The addition of two 4 Ω resistors, one in series with the source output transistor and one in series with the sink output transistor, reduces the cross conduction current. Semiconductor Group

7 Semiconductor Group Figure Block Diagram SENSE AOUT MULTIN Ι SENSE DETIN 3 4 REF oltage Amplifier + Clamp Filter Clamp kω.6. /.9 Over- oltage Regulation pf Multiplier Detector Clamp.3 / 8. Undervoltage Lockout CC Current Comp + TDA 486; G Reference oltage Driver and Logic CC- Z-Clamp IEB747 CC GTDR GND TDA 486

8 Semiconductor Group Figure 3 Application Circuit with TDA 486; G IN AC 9-7 RF-Filter and Rectifier C. µ F R R 3.3 MΩ k Ω C4 nf R kω C 3 µ F MULTIN GND 3 6 R 8 Ω 8 AOUT D N448 Multipler oltage OP + TH µ H Tr Ref R 3 k Ω DETIN Detector + Current OP + TDA 486 G C 6 PWM Logic Driver 47 nf 7 4 D C 47 µ F 4 Q GTDR BUZ 334 Ι SENSE SENSE BYP R 7 Ω. OUT R.6 MΩ R 6 k Ω IES7 TDA 486

9 Absolute Maximum Ratings Parameter Symbol Limit alues Unit Notes min. max. Supply voltage at CC Pin 8 supply + Z-current CC -GND Pin 8 Current into GTDR Pin 7 Clamping current into GTDR Pin 7 Clamping current into GTDR Pin 7 oltage at SENSE Pin oltage at AOUT Pin oltage at MULTIN Pin 3 oltage at I SENSE Pin 4 Current into DETIN Pin Current into DETIN Pin Operating Range CC I CCZ I GTDR I GTDCH I GTDCL SENSE AOUT MULTIN ISENSE I DETINH I DETINL ) CCON means CCH has been exceeded but the supply voltage is still above CCL. The device has switched from standby to active. For CCH and CCL values see Electrical Characteristics. If < CC < CCON, the device is in standby and output GTDR is active low ma ma ma ma ma ma Junction temperature T j 4 C Storage temperature T stg C Thermal resistance system-air TDA 486 TDA 486 G R thsa R thsa 8 K/W K/W observe P max observe P max GTDR > CC GTDR <.3 DETIN >6 DETIN <.9 P-DIP-8- P-DSO-8- Parameter Symbol Limit alues Unit Notes min. max. Supply voltage CC CCON Z ) Z-current I Z ma observe P max Junction temperature T j 4 C oltage at I SENSE ISENSE Z Semiconductor Group

10 Electrical Characteristics Unless otherwise stated, CC =, 4 C < T j < C. Parameter Symbol Limit alues Unit Test Condition min. typ. max. Overall Supply current, OFF I CCL 7 µa < CC < CCH Supply current, ON I CCH 4 6 ma Output low Supply current, dynamic I CCDY 4. 8 ma f DETIN = khz, C GTDR = nf CC turn-on threshold CCH. CC turn-off threshold CCL CC turn-on/off CCHY hysteresis CC clamp Z 7 9 I CCZ = ma oltage Amplifier oltage feedback threshold FB T j = C, Pin to Pin oltage feedback FB.4. Pin to Pin threshold Line regulation FBL m CC = to Input bias current I BSENSE µa Open loop voltage gain ) G 8 db Unity gain bandwidth ) B W.8 MHz Phase margin ) Φ M 8 Degr Inhibit threshold voltage AOUTI. Output current source I AOUTH ma AOUT =, SENSE =.3 Output current sink I AOUTL 4 ma AOUT = 4, SENSE =.8 ) Guaranteed by design, not % tested in production. Semiconductor Group

11 Electrical Characteristics (cont d) Unless otherwise stated, CC =, 4 C < T j < C. Parameter Symbol Limit alues Unit Test Condition Output voltage swing high state Output voltage swing low state min. typ. max. AOUTH I AOUT =. ma SENSE =.3 AOUTL.9 I AOUT =. A SENSE =.8 Overvoltage Regulator Regulation current I RAOUT 3 4 µa AOUT = MULTIN = 4, ISENSE =. Current Comparator Input bias current I BISENSE µa Input offset voltage ISENSEO m MULTIN =, AOUT =.4 Max threshold voltage ISENSEM... Delay to output ) t PHL ns Detector Upper threshold voltage DETINU..7 ( DETIN increasing) Lower threshold voltage DETINL..9 ( DETIN decreasing) Hysteresis DETINHY.6 Input current I BDETIN µa. < DETIN <.7 Input clamp voltage High state Low state DETINHC 4 DETINLC ) Guaranteed by design, not % tested in production..6 I DETIN = ma I DETIN = ma Semiconductor Group

12 Electrical Characteristics (cont d) Unless otherwise stated, CC =, 4 C < T j < C. Parameter Symbol Limit alues Unit Test Condition min. typ. max. Multiplier Input bias current I BMULTIN µa Dynamic voltage range MULTIN AOUT ) K = ISENSE / ( MULTIN ( AOUT FB )) MULTIN AOUT to 3 FB to FB + ) Guaranted by design, not % tested in production. to 4 FB to FB +. AOUT =.7 MULTIN =. Multiplier gain ) K / MULTIN = AOUT = FB + Restart Timer Restart time delay t DLY µs Gate Driver Output voltage low state GTDRL.8.8 Output voltage high state Output voltage active shut down GTDRH I GTDR = ma I GTDR = ma I GTDR = ma I GTDR = ma GTDRU..6 I GTDR = ma CC increasing: < CC < CCH, CC decreasing: < CC < CCL Rise time ) t r C GTDR = nf Fall time ) t f 4 C GTDR = nf Semiconductor Group

13 Supply Current I CC versus Supply oltage CC 6 ma Ι CC IED7 Supply Current I CC versus Junction Temperature T j 6 ma Ι CC IED SENSE = 3 AOUT = 3 MULTIN = ISENSE =. DETIN = T j = C 3 SENSE = 3 AOUT = 3 MULTIN = ISENSE =. DETIN = CC - C T j Turn-ON/-OFF Threshold oltage CC versus Junction Temperature T j CC CCH IED73 Open Loop Gain G and Phase Φ versus Frequency f G db 8 T j A IED74 CC = deg 3. < AOUT < 3. = C 3 Φ Φ 9 8 CCL Φ M 7 - C T j - - khz 4 f Semiconductor Group

14 Threshold oltage Change FB versus Junction Temperature T j m FB IED7 CC = Pin connected to Pin Threshold oltage ISENSE versus Regulation Current I RAOUT IED76.4 ISENSE CC =. -4 C C C C T j µa 34 Ι RAOUT Threshold oltage DETIN versus Junction Temperature T j DETIN 3. / IED77 CC = MULTIN = SENSE = GND ISENSE = GND DETINupper DETINlow C T j Current Sense Threshold ISENSE versus Multiplier Input MULTIN.4 ISENSE AOUT 3.7 =. IED78 4 MULTIN Semiconductor Group

15 Current Sense Threshold ISENSE versus oltage Amplifier Output AOUT.4 ISENSE. MULTIN = 3 IED79 Multiplier Gain K versus Junction Temperature T j. / K.9 CC MULTIN AOUT = = = FB + IED AOUT. - C T j Restart Time Delay t DLY versus Junction Temperature T j 4 µ s t DLY IED76 Output oltage Low/High State SAT versus Load Current I GTDR SAT 6 4 CC = T = ms t p = µ s CC GTDRL at CC = 7 IED76 GTDRH GTDRL 4 - C T j 3 ma 4 Ι GTDR Semiconductor Group

16 Package Outlines Plastic Package, P-DIP-8- (Plastic Dual In-line Package) GPD Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information. Dimensions in mm Semiconductor Group

17 Plastic Package, P-DSO-8- (Plastic Dual Small Outline Package) GPS Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information. SMD = Surface Mounted Device Dimensions in mm Semiconductor Group