Power Management & Supply. Application Note. Version 1.2, Oct AN-PFC-TDA TDA4862. TDA Technical Description.

Transcription

1 ersion 1.2, Oct Application Note TDA4862 TDA Technical Description Authors: Wolfgang Frank Michael Herfurth Published by Infineon Technologies AG Power Management & Supply N e v e r s t o p t h i n k i n g

2 Contents: Short Description... 3 Technical Description TDA Control Method... 3 Characteristics... 3 Power Supply and Self-Start... 3 Driver put... 4 Control amplifier... 4 Overvoltage control...5 Multiplier... 6 Current comparator... 6 Detector... 7 Applications of the TDA Design steps... 9 Input and put section... 9 Multiplier section Boost inductor section Operating frequency f p versus peak input voltage inpk at constant put power P Output voltage controller: Zero Current Detector Auxilliary Power Supply Summary of used Nomenclature References Page 2 of 28

3 Short Description The TDA 4862 integrated circuit controls a boost converter in a way that sinusoidal current is taken from the single-phase line supply and stabilized DC voltage is available at the put. The circuit acts as a harmonic filter which limits the harmonic currents resulting from the pulse charge currents of the capacitor during rectification in a conventional capacitive input rectifier circuit. The power factor which describes the ratio between active and apparent power is almost 1 and line voltage fluctuations are compensated very efficiently, as well. Technical Description TDA4862 Control Method The control method of the harmonic filter is based on the physical relationship between current and voltage at the boost converter choke. The transistor does not switch on until the current in the boost converter diode turns zero. This creates triangular currents at a high frequency in the choke as it is principally shown in figure 1, avoiding high-loss reverse recovery currents of the diode. If triangular currents flow through the boost converter choke uninterruptedly, the mean input current calculated over a high-frequency period is exactly half as high as the peak value of the high frequency choke current. If the peak values of the choke current are on an envelope which is proportional to a sinusoidal low-frequency input voltage, a sinusoidal, I OUT I I IN L IN input current will be drawn from the mains after smoothing by means of an RFI suppression filter. The RFI suppression filter is designed in a way that the valid EMI limits at the inputs are not exceeded. Using this control method, the operating frequency of the active harmonic filter changes with the input voltage and the load. Figure 1: Electrical input parameters and choke current at discontinuous conduction mode operation t Characteristics Power Supply and Self-Start An undervoltage lock with a turn-on threshold of 11 typically and a turn-off threshold of 8.5 typically assures that the IC is functional before the driver put is enabled. In the stand-by state prior to enabling the driver the IC consumes a current of less than 0.2 ma. A startup timer generates a set of pulses for the turn-off flip-flop, if the driver put stays Page 3 of 28

4 in low state levels for longer than 150 µs. In order to guarantee safe supply from a current source the supply voltage pin 8 is internally limited to 17 to ground. Thus, the IC has all functions necessary for low-loss self-start. TDA 4862 OLTAGE AMPLIFIER OUTPUT 2 2,5 Reference C3 2.2 Internal Supply Undervoltage Lock Restart Timer C ZERO CURRENT DETECTOR OLTAGE SENSE 1 OP 0.9 C4 0 0 & 0 S Q 0 0 & CC DRIE OUTPUT 36k & 0 R Q 6 GROUND MULTIPLIER 3 M M Multiplier M3 C1 Q M M1*(M2- FB )*K C m FB p 30k 4 CURRENT SENSE Figure 2: Scheme of TDA4862 Driver put The driver put has been designed to drive power MOSFET with a current capability of ± 500 ma. In order to avoid reverse currents the driver put is equipped with clamping diodes connected to ground and supply voltage with a current rating of 100 ma. In standby state the driver put actively asserts a LOW level with a residual voltage of 1.5 and 5 ma dissipation current. Control amplifier The control amplifier compares the divided put voltage at its inverting input with a highly accurate reference voltage of 2.5, with a maximum deviation of less than ±2% over the total temperature range ( 40 C < T J < 150 C), at its non-inverting input. For the purpose of control loop compensation a feedback network is inserted between the amplifier put (pin 2) and its inverting input (pin 1). A feedback design using only one capacitor as an I-controller causes oscillating transient response, because the boost converter, as a controlled current source, with the storage capacitor at its put delays the phase by almost 90 in no-load and in low-load operation. The transient response is more favorable if the control amplifier is designed as a PIT1-controller (see design steps). Page 4 of 28

5 The put voltage of the control amplifier ranges from 0.9 to 4.3 and can be loaded with a current of 1 ma (source) and 2 ma (sink), respectively. The put voltage of the control amplifier is monitored by a comparator. If the put voltage drops 0.3 below the reference level of 2.5 (i.e. reference voltage) of the M2 multiplier input the driver put will be blocked directly via the turn-off flip-flop. This measure guarantees the stability of the put voltage in complete no-load operation, with interferences from offset voltages at the multiplier put or at the comparator input. The put DC voltage of the boost converter is superimposed by double the mains frequency AC voltage ripple. The amplitude of the superimposed AC voltage depends on the capacity of the storage capacitor and the load. The superimposed AC, which is also fed back via the control amplifier, causes an undesirableed modulation of the line current drawn. Therefore the bandwidth of the controll amplifier is chosen which is considerably lower than twice the mains-frequency. However, this causes the controller to react slowly to sudden load changes which results in voltage overshoots and put breakdowns. Overvoltage control If at the boost converter put a higher voltage than the rated put voltage is generated as a result of voltage transients or load rejection, a current flows back from the put voltage divider to the operational amplifier put via the feedback network. This is shown in figure 3. The current I is measured and in case of a threshold of 30 µa (typ.) is exceeded the multiplier put is controlled to zero potential via a third input M3. This measure causes the input current to be continuously M3 + C4 - M2 0.9 cc OP REF + - oltage Sense I R H 1600k I250µA I 30µA R H 1600k I280µA 2.5 I 30µA 498 R H 3200k I155µA 2.5 I Threshold I30µA I250µA I250µA I125µA oltage Amplifier Output 36k TDA 4862 Compensation Network I R L 10k R L 10k R L 20k Figure 3: Examples of the put voltage divider Page 5 of 28

6 compensated back, thus avoiding uncontrolled oscillations of the line current drawn, as they usually appear with digital measures. The switch-off level of the overvoltage control can be adjusted via the internal resistance of the put voltage divider. In normal operation state the voltage at the tap of the divider is 2.5 (i.e. reference voltage). In case of higher than rated put voltage the excess divider current flows from the tap to the operational amplifier put via the feedback network. The overvoltage control is also guaranteed in the operational phases when the put voltage of the control amplifier reaches the upper limit threshold, because the dissipation current is measured as well. As soon as the put voltage of the control amplifier tends towards the minimum level, the comparator turns off at a level of 2.2 to guarantee safe no-load operation. Multiplier The multiplier generates the turn-off threshold of the current comparator giving consideration to the waveshape of the feed voltage. In a typical application the rectified and divided supply voltage is applied to the input M1 (pin 3). The put voltage of the control amplifier is applied at the input M2 which under constant load and ideal conditions appears as DC voltage with superimposed AC shares. At the put of the multiplier a signal in the wave form of the rectified voltage corresponding to input M1 is generated which can be modified in its amplitude via the DC voltage at input M2. Superimposed AC voltage shares at the input M2 cause an undesired modulation of the line current drawn, unless they are part of the dynamic control processes. The level control range of the input M1 is 0 to 4.0, the reference level being 0. The level control range of the input M2 is 2.5 to 4.5, the reference level being 2.5. For multiplication a further, constant factor C m , which is an internal factor of the multiplier, is effective. Its dimension is -1 in order to comply with the following equation. In this way the current comparator level can be calculated as Qm C m ( pin2 - ref ) pin3. The put voltage of the multiplier is limited to 1.3. This measure causes a defined turn-off threshold for current limitation. In this way, dangerous excess currents are avoided which can arise in particular in the case of an expanded input voltage range because the multiplier with its restricted dynamics re-stabilized the current consumption. Current comparator The current comparator detects the voltage decline at the shunt which is in the source path of the power MOSFET via its inverting input (pin 4) and which should have an intrinsic inductance as low as possible. When switching on the transistor voltage, spikes are generated at the shunt as a result of the intrinsic inductance of the shunt with turn on and the influence of the driver currents. An integrated low-pass filter suppresses these voltage spikes. As soon as the voltage decline at the shunt reaches Page 6 of 28

7 the turn-off threshold defined by the multiplier, the turn-off flip-flop is reset and the driver switches off. The turn-off flip-flop prevents multiple pulses during the switching waveform of the power MOSFET. The turn-off delay time between comparator input and driver put is below 250 ns. Detector The detector finds the point of time when the current in the boost converter choke turned zero and then enables the control of a new pulse cycle. After the current comparator triggers the turn-off process and the power MOSFET blocks, the boost converter diode takes over the current. In this case the polarity of the voltage at the choke winding changes in a way that now a higher level voltage levell ( ) is available at the drainside terminal of the choke compared with the mains rectifier side terminall (level in ) of the choke. As soon as the choke current reaches zero and the boost converter diode blocks, the voltage reverses at the drain side terminal of the choke. The voltage at the choke winding turns zero or changes polarity. A second winding (detector winding) on the choke, which has approximately 1/5 of the number of turns compared with the mains winding, permits the change of polarity of the choke voltage to be registered with detrimental influences. Evaluation is effected by the detector function (pin 5) of the IC, with the drain side polarity of the detector winding being measured by means of a hysteresis-determined comparator. The level for the acceptance of the MOSFET blocks command from the turn-off flip-flop and for setting the flip-flop is 2.5 (i.e. reference voltage) with rising voltage. In case of a voltage decline, which signals the zero crossing of the current, the switching level enabling the driver stage is 1.9. The voltage of the detector winding is applied to pin 5 via a high-ohmic resistance (10k to 47k). Clamping structures are available in the IC which limit the voltage at the input to +5 and +0.6, respectively, at 10 ma maximum. There are cases in which there is no significant detector signal to set the turn-off flip-flop. This may be the case when the supply voltage is switched on, in case of line overvoltage exceeding the put voltage and in no-load and low-load operation, when the voltage controlller specifies intermittant operation. In that case a startup generator is activated which supplies a set of pulses to the turn off flip-flop if the driver put stays on LOW-level longer than 150 µs. Applications of the TDA4862 The following applications demontrate the good performance of the TDA4862 controlling a power factor preconverter. The design steps indicate the method of the calculation of the components values. Lamp ballast designs as well as a design for switched mode power supplies (SMPS) are given here as Page 7 of 28

8 examples. Circuit diagrams and measurement results at different operating conditions establish a good basis for evaluation. The tables of page 17 ff. also consists of a column called I Z which contains the values for the surplus current of the auxiliary power supply for the IC bypassed with a 15 zener diode. The zener current indicates a suffucient IC supply. Therefore it should be low enough to avoid unnecessary losses. There may be also states of operation when the zener current reaches zero. Then the actual supply voltage CC of the IC is figured. Usually a single stage RFI-filter does not accomplish the RFI-standards. Therefore multiple stage RFIfilters are designed into these applications as an example how to suppress resonant oscillations of these filters. Discontinuous conduction mode always results in a high switching efficiency, because it avoids reverse recovery losses of the boost converter diode. A high power factor, low harmonics, a wide input voltage range and a feedback controlled put voltage are the most omportant features of a power factor preconverter. The TDA4862 contains all control and monitoring functions to meet these demands. Page 8 of 28

9 Design steps Input and put section Application 2L-Ballast 1L-Ballast 3L-Ballast SMPS Nominal input voltage innom 120 AC 230 AC 277 AC Minimum input voltage inmin innom 20% 96 AC 184 AC 221 AC 90 AC Maximum input voltage inmax innom + 20% 144 AC 276 AC 332 AC 270 AC Minimum peak input voltage inpkmin 2 innin Maximum peak input voltage inpkmax 2 inmax Estimated minimum efficiency η 0.9 Output power P η P in 75W 53W 110 W 150 W Maximum peak input current I inpkmax 2 P / ( inpmin η) 1.225A 0.453A 0.781A A Maximum high frequency peak current I PkmaxHF 2 I inpkmax 2.45A 0.906A A 5.25 A Maximum current sense threshold ISensemax 1.3 Shunt resistor R11 ISensem / I PkmaxHF 0.53Ω 1.44Ω 0.83 Ω 0.25 Ω Nominal put voltage Recommended minimum: inpkmax DC DC 410 DC Reference voltage ref 2.5 Controller current at pin AOUT I AOUT 30 µa Output voltage divider (Select I R5 250 µa) R5 R4 ref / I R5 R 5 ( ref ) / ref 10k 910k 10k 1640k 10k 1910k 10k 1640k Overvoltage threshold O (Recommended: 1.1 ) Page 9 of 28

10 Multiplier section Application 2-Lamp-Ballast 1L-Ballast 3L-Ballast SMPS Multiplier inputs M1 and M2 dynamic voltage range m1r 3.8 ; m2r 4.5 ref 2 Multiplier put limitation Qmmax ISensemax 1.3 Multiplier gain C m 0.65 m1 (@ Qm 1.3; m2r 2) 1.3 / (2* C m ) 1 From multiplier put characteristic m1lim (@ Qm 1.3; m2r 2) 1.2 Select m1 m1lim inpkmin Select upper resistor of input voltage divider R6 1M 2M 2M 940K Lower resistor of input voltage divider R7 R6! m1lim / ( inpkmin m1lim ) 8.89k 9.27k 7.69k 8.95k Low pass filter capacitor C4 1 / (2π!R2!f) {1 khz<f<3khz} 10 nf 10 nf 10 nf 10 nf Test: Input range: m1 (@ inpkmax ) < m1r 3.8? otherwise select m1 (@ inpkmin ) < m1lim OK 1.80OK 1.80OK 3.62OK Page 10 of 28

11 Boost inductor section In this section two different approaches for the calculation of the transformer primary inductance L P are presented. The first one is recommended for a small input voltage range application or for applications with nearly constant put power, e.g. lamp ballasts. Therefore only one example is executed here. The other one is suitable for the demands of wide range applications like they occur in SMPS. All the values of the sections before are still valid. 2-Lamp-Ballast On-time of power switch: T on L P! I PkmaxHF / in, I PkmaxHF 2 I inpkmax Off-time of power switch: T off L P! I PkmaxHF / ( - in ) Pulse frequency: Design criterion: f p T on 1 + T off in ( L I P in ) Pk max HF Calculate L P according to desired range of pulse frequency (e.g. 80 khz < f p <110 khz) at nominal input voltage innom and rated put power P L P innom ( f p I innom Pk max HF ) innom ( 2P 120 ( ) 0, µ H khz 2 75 W Also possible: Calculate L P by selecting the on-time T on in the range of 3 µs < T on < 6 µs L P T I on innom Pk max HF T on 2 P Both inductances will be appropriate. f p innom ) η innom 2 η 2 5 µ s (120 ) 0,9 innom 432 µ 2 75 W H SMPS-preconverter Design criterion: Calculate L P in order to obtain pulse frequencies higher than 25 khz at maximum peak input voltage and twice of nominal put power and on minimum peak input voltage and twice of nominal put power L 2 2 inpk max ( inpk max ) η (382 ) ( ) 0,9 P < 598 µ fp 2 2P khz W and L 2 2 inpk min ( inpk min ) η (127 ) ( ) 0,9 P < 668 µ fp 2 2P khz W We therefore select L P < 598 µh H H Page 11 of 28

12 Application Example Ballast, innom 120 L ( 120 )² ( ) , 4mH W P OUT 75 W kHz 2 P L 459 µh OUT P OUT Ballast, innom 230 L ( 230 )² ( ) 0,9 116mH W P OUT 55 W kHz 2 P L 2,1 mh OUT P OUT Ballast, innom 277 L ( 277 )² ( ) 0,9 162mH W P OUT 110W kHz 2 P L 1,47mH OUT P OUT SMPS, in L 90mH W P OUT 150W L 600µH P OUT Page 12 of 28

13 Operating frequency f p versus peak input voltage inpk at constant put power P f ( p inpk max ) inpk max L ( P 2 I inpk max inpk max ) inpk max ( L P inpk max 2 2P ) in inpk max ² inpk max ( L P 4 P inpk max ) η Operating frequency f p (ωt) in 2 sinωt ( L P 2 I in in 2 sinωt) 2 sinωt in ( in 2 sinωt) ( in )² η ( in 2 sinωt) L 2 I L 2 P P in P (120 )² 0.9 Example f p ( ωt) ( sinωt) µ H 2 75W Figure 4 shows the pulse frequency dependent on the peak value of the input voltage for constant put power or constant primary inductance respectively. For example, the lower limit of the input voltage in wide range applications is ab 0.3. The corresponding pulse frequency is then 40 % of the maximum pulse frequency. The upper limit in such applications is ab 90 % of the put voltage, which leads to a pulse frequncy of ab 50 % of the maximal value. It is important, that those two frequencies mentioned above are still above 25 khz. f HFACP INACP f MAX INACP OUT Figure 4: Pulse frequency f p as a function of the input peak voltage Page 13 of 28

14 Output voltage controller: Usually a PIT 1 -design is used in PFC-circuits like it is shown in figure 8. The setting of the values of C1, C2 and R1 should hit the following targets: - Good suppression of superimposed AC-share of the put voltage which has twice the frequency of the input voltage, - good behaviour at load changes or changes of the input voltage, - good behaviour at low load conditions. OUT dB k 10dB C1 10k G 3,3Hz 33Hz 100Hz f -10dB Figure 5: Output voltage controller with integral component OUT dB 2,5 910k 10dB C1 C2 10k G 1,6Hz f 3,3Hz 16Hz 33Hz 100Hz R2-10dB Figure 6: Output voltage controller in PIT1-design Page 14 of 28

15 Zero Current Detector The upper threshold of the ZCD is max For a continuous operation the difference between put voltage and maximum input voltage inpkmax a) C10 R12 N P N ZCD D6 R9 and the transformation ratio of the inductor windings have to accomplish the following relation cc N P ZCD NZCD ( inpk max ) > 2. N 75 P The recommended transformation ratio of N ZCD /N P 1/5 meets a minimal voltage difference of 14. If b) C10 D6 cc D7 N ZCD R12 C13 ZCD R9 the detector input voltage doesn t achieve the upper threshold, the IC is operating with the timer frequency. c) C10 D7 R12A N P N ZCD D6 C13 L5 R9 Auxilliary Power Supply cc ZCD An obvious way to supply the IC is to use the detector winding. We have to care, that the supply circuit Figure 7: Auxiliary power supply realized with rectifier (a) and charge pump (b and c) doesn t influence the detector signal. First, in a simple voltage mode supply, we use a diode, a storage capacitor C10 and a current limiting resistor R12. We achieve good results in ballast applications with the following design of the transformation ratio: N N ZCD P ZCD innom ZCD ; R Ω...270Ω Second in a charge pump supply, we use two diodes, two capacitors C10, C13 and one decoupling Resistor R12 or a decoupling inductor L5 (lower losses) and a current limiting resistor R12A, to avoid burn down at resonance frequency. This method of supply is to prefer in SMPS applications with wide input voltage range. The supply current increases with the operating frequency at low load and is not dependend on the input voltage. We achieve good results with the following design of the transformation ratio: N N ZCD P ZCD ZCD 80, C13 3nF...4nF R12 390Ω...270Ω Or C13 1 nf...1.5nf, L5 50 µh...100µh, R12A designed with C13 and L5 as a low-pass filter of Bessel characteristic. Page 15 of 28

16 Applications 500µH L1 1N DC D1 D2 D5 OUT Fuse 1A IN AC 2x10mH L2 C11 µ47 L1: 500µH EF25, N27, gap1mm W175Wdg. 0,40d W215Wdg. 0,22d Q1: BUZ60 (400; 1Ω) 1mH L3 R15 100Ω C5 3300p C6 µ47 C7 3300p U R14 D3 S10K150 R7 9k1 D4 R6 1M C9 µ1 C4 10n MUR115 D6 3 8 C10 47µ/25 TDA R12 270Ω R8 100k R10 12Ω C2 1µ C1 1µ R9 33k R2 5k1 Q1 R11 0Ω5 R4 910k R5 10k C8 47µF 350 GND Figure 8: 75W Power Factor Preconverter with TDA 4862 and innom 120 Page 16 of 28

17 Table 1: Measurement of input and put values P IN real power 120 input for 2 x 35W lamp ballast (C 47µF, L1500µH) RM S I RM S PF THD OUT I OUT OUTAC A 82.20W % A 75W mA A 81.21W % A 75W mA A 79.55W % A 75W mA A 78.68W % A 75W mA A 78.44W % A 75W mA A 35.21W % A 32.5W mA A 34.45W % A 32.5W mA A 34.25W % A 32.5W A 16.54W % A 15W mA A 16.32W % A 15W A 16.24W % A 15W A 8.65W % A 7.5W P OUT η I z (15) or CC Page 17 of 28

18 1500µH L1 MUR DC Fuse 0,5A IN AC 2x18mH L2 C11 µ22 L1: 1500µH EF20, N27, gap1mm W Wdg. 0,33d W 2 18 Wdg. 0,22d Q1: BUZ77A (400, 4Ω) 3mH L3 R15 150Ω C5 3300p C6 µ22 C7 3300p U D1 R14 D3 S10K250 D2 R7 9k1 D4 R6A 1M R6 1M C9 µ1 C4 10n MUR115 C10 47µ/25 D6 R k TDA R12 270Ω R8A 100k R10 12Ω C2 1µ C1 1µ R9 33k R2 5k1 Q1 R11 1Ω5 D5 R4 820k R4 820k R5 10k OUT C8 10µF 450 GND Figure 9: 53W Power Factor Preconverter with TDA 4862 and innom 230 Input Page 18 of 28

19 Table 2: Measurement of input and put values P IN real power 230 input for 50W lamp ballast (C 10µF, L11.5mH) RM S I RM S PF THD OUT I OUT OUTAC A 57.16W % A 53W mA A 56.38W % A 53W mA A 56.02W % A 53W mA A 55.76W % A 53W mA A 55.61W % A 53W mA A 29.36W % A 27W mA A 28.95W % A 27W mA A 28.8W % A 27W mA A 12.68W % A 11W mA A 12.63W % A 11W A 12.60W % A 11W P OUT η I z (15) od. CC Page 19 of 28

20 1500µH L1 MUR DC Fuse 0,8A IN AC 2x18mH L2 C11 µ22 L1: 1500µH EF25, N27, gap2mm W Wdg. 0,38d W 2 17 Wdg. 0,22d Q1: BUZ80A (800, 3Ω) 3mH L3 R15 150Ω C5 3300p C6 µ22 C7 3300p U D1 R14 D3 S10K300 D2 R7 8k2 D4 R6A 1M R6 1M C9 µ1 C4 10n MUR115 D6 3 8 C10 47µ/25 TDA R12 270Ω R8A 120k R10 12Ω C2 1µ C1 1µ R9 33k R2 5k1 Q1 R11 0Ω8 D5 R4A 910k R4 1M R5 10k OUT C8 47µF 350 GND Figure 10: 110W Power Factor Preconverter with TDA 4862 and innom 277 Input Page 20 of 28

21 Table 3: Measurement of input and put values 277 input for 3 x 35W lamp ballast (C 22µF, L11.5mH) RMS I RMS P IN PF THD OUT I OUT P OUT OUTAC η I z (15) real power or CC A 115.8W % A 110W mA A 115.1W % A 110W mA A 114.6W % A 110W mA A 114.2W % A 110W mA A 79.3W % A 75W mA A 78.1W % A 75W mA A 77.9W % A 75W mA A 24.3W % A 22W mA A 24.2W % A 22W A 24.2W % A 22W Page 21 of 28

22 500µH L1 MUR DC D1 D2 R12 D7 C13 L5 D5 OUT Fuse M2,5A IN AC 2x6.8mH L2 L4 1.2mH C11 µ68(x) L1: 500µH RM14, N67, A L 160 W 1 56 Wdg. 60x0.1d W 2 11 Wdg. 0,3d BUZ91 : 600, 0Ω8 1.2mH L3 R15 120Ω C5 3n3(Y) U C6 µ68(x) C7 3n3(Y) R14 SIO S14 K250 B250C5000/3300 D3 R7 9k1 D4 R6A 470k R6 470k C9 µ68 Z15 D8 C4 10n 470Ω 3 8 C10 47µ/25 D6 2xBYT TDA n/400 70µH R8 R8A 120k k R10 12Ω C2 1µ C1 1µ C11 270p R9 33k Q1 BUZ 91 R2 5k1 R13 1k R11 0Ω23 R4A 820k R4 820k C12 µ15 R5 10k C8 150µF 450 GND Figure 11: 150W Universal Input Power Factor Preconverter with TDA 4862 Page 22 of 28

23 Table 4: Measurement of input and put values RM S I RM S P IN real power / 150W Universal input for SMPS (C 150µF, L1500µH) PF THD OUT I OUT OUTAC A 166.4W % mA 150W 10pp mA A 161.0W % mA 150W 10pp mA A 157.2W % mA 150W 10pp mA A 155.9W % mA 150W 10pp mA A 155.0W % mA 150W 10pp mA A 33.9W % mA 30W 2pp mA A 34.0W % mA 30W 2pp mA A 34.3W % mA 30W 2pp mA A 34.3W % mA 30W 2pp mA A 34.0W % mA 30W 2pp mA A 14.1W % mA 9.4W 0.8pp mA 90- max. selfsupply pp P OUT η I z (15) or CC Page 23 of 28

24 750µH L1 MUR DC Fuse M1.6A IN AC 2x6.8mH L2 C11 µ47(x) L1: 750µH E36/11, N27, gap2mm W 1 85 Wdg., 40x0.1d W 2 17 Wdg., 0,3d BUZ90 : 600, 1Ω6 1.2mH L3 R15 120Ω C5 3n3(Y) U C6 µ47(x) C7 3n3(Y) R14 SIO S14 K250 D1 B250C1500/1000 D3 D2 R7 9k1 D4 2x1N4148 R6A 470k R6 470k C9 µ22 C4 10n D7 D6 3 8 C10 47µ/25 C13 3n3/400 TDA R12 470Ω R8 120k R8A 120k R10 12Ω C2 1µ C1 1µ C11 270p R9 33k Q1 BUZ 90 R2 5k1 R13 1k R11 0Ω3 D5 R4A 820k R4 820k R5 10k OUT C8 100µF 450 GND Figure 12: 110W Universal Input Power Factor Preconverter with TDA 4862 Page 24 of 28

25 Table 5: Measurement of input and put values RM S I RM S P IN real power /110W Universal input for SMPS (C 100µF, L1750µH) PF THD OUT I OUT OUTAC A 122.7W % mA 110W 11pp mA A 118.0W % mA 110W 11pp mA A 115.3W % mA 110W 11pp mA A 115.0W % mA 110W 11pp mA A 114.4W % mA 110W 11pp mA A 25.0W % mA 22W 2pp mA A 25.2W % mA 22W 2pp mA A 25.4W % mA 22W 2pp mA A 25.3W % mA 22W 2pp mA A 24.5W % mA 22W 10pp mA pp P OUT η I z (15) or CC Page 25 of 28

26 Summary of used Nomenclature Physics: General identifiers: A... cross area b, B... magnetic inductance C... capacitance d, D... duty cycle f... frequency i, I... current L... inductance N... number of turns p, P... power t, T... time, time-intervals v,... voltage W... energy η... efficiency Special identifiers: A L... inductance factor (BR)CES collector-emitter breakdown voltage of IGBT F... forward voltage of diodes rrm... maximum reverse voltage of diodes K 1, K 2.. ferrite core constants big letters: contant values and time intervals small letters: time variant values Components: C... capacitor D... diode IC... integrated circuit L... inductor R... resistor TR... transformer Indices: AC... alternating current value DC... direct current value BE... basis-emitter value CS... current sense value J... Junction value OPTO. optocoupler value P... primary side value Pk... peak value R... reflected from secondary to primary side S... secondary side value Sh... shunt value ULO.. undervoltage lock value Z... zener value fmin... value at minimum pulse frequency i... running variable in... input value max... maximum value min... minimum value off... turn-off value on... turn-on value... put value p... pulsed rip... ripple value 1,2,3... on-going designator Page 26 of 28

27 References [1] Infineon Technologies AG: TDA4862 Power factor and boost converter controller for high power factor and low THD; data sheet; Infineon Technologies AG; Munich; Germany; 07/01. Page 27 of 28

28 Revision History Application Note Actual Release: 1.2 Date: Previous Release: 1.1 Page of Page of Subjects changed since last release actual prev. Rel. Rel Deleted updated For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or our webpage at CoolMOS and CoolSET are trademarks of Infineon Technologies AG. Edition Published by Infineon Technologies AG, St.-Martin-Strasse 53, D München Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Page 28 of 28