LOGIC. Smart Quad Channel Low-Side Switch. Datasheet TLE 6228 GP. Output Stage. Gate Control

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1 Smart Quad Channel ow-side Switch Features Product Summary Shorted Circuit Protection Overtemperature Protection Overvoltage Protection Parallel Control of the Inputs (PWM Applications) Seperate Diagnostic Pin for Each Channel Power - SO 20 - Package with integrated cooling area Standby mode with low current consumption µc compatible Input Electrostatic Discharge (ESD) Protection Supply voltage S Drain source voltage DS(AZ)max 60 On resistance R ON 1, Ω R ON 3, Ω Output current I D 1,2 (max) 2 x 5 A I D 3,4 (max) 2 x 3 A Application All kinds of resistive and inductive loads (relays,electromagnetic valves) µc compatible power switch for 12 and 24 applications Solenoid control switch in automotive and industrial control systems Robotic Controls P-DSO Ordering Code: Q67006-A9364 General description Quad channel ow-side-switch (2x5A/2x3A) in Smart Power Technology (SPT) with four separate inputs and four open drain DMOS output stages. The TE 6228 GP is fully protected by embedded protection functions and designed for automotive and industrial applications. Each channel has its own status signal for diagnostic feedback. Therefore the TE 6228 GP is particularly suitable for ABS or Powertrain Systems. Block Diagram STBY S ENA GND normal function BB 1 2 as Ch. 1 OGIC SCB / overload overtemperature open load/sh. to gnd 3 4 as Ch. 1 as Ch. 1 Output Stage OUT1 ST ST2 ST3 ST4 as ST 1 as ST 1 as ST 1 Gate Control OUT4 GND 1

2 Detailed Block Diagram S STBY internal supply ENA Overtemperature Channel 4 Overtemperature Channel 1 Open oad 1 OGIC Overload OUT1 ST1 Open oad IPD 4 OGIC Overload OUT ST4 Overtemperature Channel 3 Overtemperature Channel 2 IPD Open oad 2 OGIC Overload OUT ST2 Open oad IPD 3 OGIC Overload OUT ST3 IPD GND 2

3 Pin Description Pin Configuration (Top view) Pin Symbol Function 1 GND Ground 2 OUT1 Power Output channel 1 3 ST1 Status Output channel Control Input channel 4 5 S Supply oltage 6 STBY Standby 7 3 Control Input channel 3 8 ST2 Status Output channel 2 9 OUT2 Power Output channel 2 10 GND Ground 11 GND Ground 12 OUT3 Power Output channel 3 13 ST3 Status Output channel Control Input channel 2 15 GND Ground ogic 16 ENA Enable Input for all four channels 17 1 Control Input channel 1 18 ST4 Status Output channel 4 19 OUT4 Power Output channel 4 20 GND Ground GND 1 20 GND OUT OUT4 ST ST S 5 16 ENA STBY 6 15 GND ST ST3 OUT OUT3 GND GND P - DSO eat slug internally connected to ground pins 3

4 Maximum Ratings for T j = 40 C to 150 C The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Parameter Symbol alues Unit Supply voltage S Continuous drain source voltage (OUT1...OUT4) DS 45 Input voltage 1 to 4, ENA, ENA Input voltage STBY STBY Status output voltage ST oad Dump Protection oad Dump = U P +U S ; U P =13.5 R 1) I =2 Ω; td =400ms; = low or high With R = 5 Ω for Ch. 1,2; 10 Ω for Ch. 3,4 (I D = 2,7A respectively 1,35A) Operating temperature range Storage temperature range oad Dump2 ) 55 T j T stg Output current per channel (see page 6) I D(lim) I D(lim) min A Status output current I ST ma Inductive load switch energy (single pulse) T j = 25 C E AS 50 mj Electrostatic Discharge oltage (human body model) according to MI STD 883D, method and EOS/ESD assn. standard S D umidity Category, D C ESD 2000 IEC Climatic Category, D IEC /150/56 Thermal resistance junction case (die soldered on the frame) junction - min. footprint junction - 6 cm 2 cooling area E R thjc 2 R thja K/W Minimum footprint PCB with heat pipes, backside 6 cm 2 cooling area 1) R I =internal resistance of the load dump test pulse generator D200 2) oaddump is setup withouut connected to the generator per ISO and D

5 Electrical Characteristics Parameter and Conditions Symbol alues Unit S = 4.8 to 18 ; T j = - 40 C to C (unless otherwise specified) min typ max 1. Power Supply ( S ) Supply current (Outputs ON) I S 8 ma Supply current (Outputs OFF) ENA =, STBY = I S 4 ma Standby current STBY = I S 10 µa Operating voltage S Power Outputs ON state resistance Channel 1,2 T j = 25 C I D = 1A; S 9.5 T j = 150 C ON state resistance Channel 3,4 T j = 25 C I D = 1A; S 9.5 T j = 150 C R DS(ON) R DS(ON) Z-Diode clamping voltage (OUT1...4) I D 100 ma DS(AZ) Pull down current STBY =, = I PD µa Output leakage current 3 STBY =, 0 DS 20 I Dlk 5 µa Output turn on time 4 Output turn time 4 Output on fall time 4 Output rise time 4 Overload switch- delay time 4 Output status delay time 4 Failure extension Time for Status Report Input Suppression Time Open oad () filtering Time 5 3. Digital Inputs (1, 2, 3, 4, ENA) I D = 1 A I D = 1 A I D = 1 A I D = 1 A t on t t fall t rise SO - t fo() Input low voltage Input high voltage Input voltage hysteresis 5 ys m Input pull down current = 5 ; S 6.5 I µa Enable pull down current ENA = 5 ; S 6.5 I ENA µa 4. Digital Status Outputs (ST1 - ST4) Open Drain Output voltage low I ST = 2 ma ST 0.5 eakage current high I ST 2 µa Ω Ω µs 3 If the output voltage exceeds 35, this current (zener current of a internal structure) can rise up to 1mA 4 See timing diagram, resistive load condition; S 9 5 This parameter will not be testet but assured by design 5

6 Electrical Characteristics Parameter and Conditions Symbol alues Unit S = 4.8 to 18 ; T j = 40 C to C (unless otherwise specified) min typ max 5. Standby Input (STBY) Input low voltage STBY 0 1 Input high voltage STBY 3.5 S Input current STBY = 18 I STBY 300 µa 6. Diagnostic Functions Open load detection voltage ENA = X, = Open load detection current channel 1,2 ENA = = Open load detection current channel 3,4 ENA = = S 6.5 S 6.5 S 6.5 DS(O) 0.3* S 0.33* S 0.36* S I D(O) 1, ma I D(O) 3, ma Overload detection current channel 1,2 S 6.5 I D(lim) 1, A Overload detection current channel 3,4 S 6.5 I D(lim) 3, A Overtemperature shutdown threshold 5 T th C ysteresis T hys 10 K Pulse Width for static diagnostic output t 500 µs 5 This parameter will not be tested but assured by design 6

7 Application Description This IC is especially designed to drive inductive loads (relays, electromagnetic valves). Integrated clamp-diodes limit the output voltage when inductive loads are discharged. Four open-drain logic outputs indicate the status of the integrated ciruit. The following conditions are monitored and signalled: - overloading of output (also shorted load to supply) in active mode - open and shorted load to ground in active and inactive mode - overtemperature Input Circuits Circuiescription The control and enable inputs, both active high, consist of schmitt triggers with hysteresis. All inputs are provided with pull-down current sources. Not connected inputs are interpreted as low and the respective output stages are switched. In standby mode (STBY = OW ) the current consumption is greatly reduced. The circuit is active when STBY = IG. If the standby function is not used, it is allowed to connect the standby pin directly to S. Status Signals: The status signals are undefined for 2ms after a power up event or a STBY low to high transition. Output Stages The four power outputs consist of DMOS-power transistors with open drains. The output stages are short circuit protected throughout the operating range. Each output has it's own zenerclamp. This causes a voltage limitation at the power transistor when inductive loads are switched. Parallel to the DMOS transistors there are internal pull down current sources. They are provided to detect an open load condition in the state. They will be disconnected in the standby mode. Due to EMI measures there is an internal zenerclamp in parallel to the output stage. It gets active above 33 drain source voltage. This leads to an increasing leakage current up to 1 DS = 40. Protective Circuits The outputs are protected 6) against current overload and overtemperature. If the output current increases above the overload detection threshold I QO for a longer time then SO or the temperature increases above T th, then the power transistor is immediately switched. It remains until the control signal at the input is switched and on again. Fauletection The status outputs indicate the switching state of the output stage. Under normal conditions is: ST = low Output ; ST = high Output on. If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table. 6) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently. 7

8 If current overload or overtemperature occurs for a longer time than SO, the fault condition is latched into an internal register and the output is shutdown. The reset is done by switching the corresponding control input for a time longer than -. Open load is detected for all four channels in on and mode. In the on mode the load current is monitored. If it drops below the specified threshold value IQU then an open load condition is detected. In the mode, the output voltage is monitored. An open load condition is detected when the output voltage of a given channel is below the threshold DS(O), which is typ. 33 % of the supply voltage S. To prevent an open load diagnosis in case of transient oltages on the outputs the open load detection in mode uses a filter of typ. 50µs. Status output at pulse width operation If the input is operated with a pulsed signal, the status does not follow each single pulse of the input signal. An internal delay td of typ. 1.2ms ( min 500 µs) enables a continuous status output signal. See the timing diagrams on the following pages for further information. This internal status delay simplifies diagnostic software for pwm applications. Diagnostic Table In general the status follows the input signal in normal operating conditions. If any error is detected the status is inverted. Operating Condition Standby Input Enable Input Control Input Power Output Status Output STBY ENA Q ST Standby X X Normal function Open load or short to ground Overload or short to supply 1) reset latch 2) Overtemperature 1) reset latch 2) X X X ON ON Note 1) : overload/short-to-supply/overtemperature - events shorter than min. time SO specified in 2.10 will not be latched and not reported at the status pin. 8

9 Note 2) : to reset latched status-output in case of overload/short-to-supply/overtemperature the control input has to go low and stay low for longer than max. input suppression time - specified in 2.13 of the characteristics Failure Situations and Status Report ogic Block Diagram Overtemperature 1...overtemperature 0...normal cond. Gate Driver 1... Output 0...Output ENA 1...enabled 0... disabled Input 1...On 0... Off SO Delay D Delay 60µs S SET Q OUT 1,2ms typ. R CR Q Overload 0...overload 1...normal cond. - when load Delay 60µs OUT 60µs typ. EN Delay D OUT Open load "" 1...open load 0...normal cond. Filter 30µs I EN Delay D OUT Status 0...igh 1...ow Filter Open load "on" 0...open load 1... normal cond. EN Delay D OUT 9

10 Timing Diagrams Output Slope t DS S 85% ton t 15% t f t r t ST t Fig. 1 Overload Switch OFF Delay I D I D(lim) SO I D(O) t ST t Fig. 2 10

11 Test Circuit D = 5 10k 10k 10k 10k ST1 ST2 ST3 ST ENA ST1 ST2 ST3 ST ENA IST1 IST2 IST3 IST4 I1 I2 I3 I4 IENA ISTBY STBY ST1 ST2 ST3 ST ENA STBY OUT1 S S TE 6227 GND OUT2 OUT3 IS OUT4 R 4 ID1 ID2 ID3 ID4 R 3 R 2 R 1 OUT1 OUT2 OUT3 OUT4 DS(OUT4) DS(OUT3) DS(OUT2) DS(OUT1) TE 6228 GP 11

12 Application Circuit Status Output Control Inputs Enable Input D = 5 10k 10k 10k 10k C STBY ST1 ST2 ST3 ST S TE 6228 ENA GND OUT1 OUT2 OUT3 OUT The blocking capacitor C is recommended to avoid critical negative voltage spikes on S in case of battery interruption during OFF-commutation. 12

13 Timing Diagrams of Diagnostic with Pulsed Input Signal Normal condition, resistive load, pulsed input signal t I D ST Fig. 3 Current Overload F current overload condition t I D(lim) I D ST - SO SO t < - : Input suppression time avoids a restart after overtemperature Fig. 4 13

14 Diagnostic status output at different open load current conditions I D I D(O) ST Fig. 5 t I D I D(O) ST t OFF < leads to a static status signal Fig. 6 t I D I D(O) ST t > : Intermittend status signal Fig. 7 14

15 Normal operation, followed by open load condition ~ 55 Open load voltage condition DS 12 33% I D(O) I D ST t fo()- Fig. 8 Overtemperature Overtemperature I D I D(O) t > td- Reset of overload Flip Flop ST SO Fig. 9 15

16 Typical electrical Characteristics Drain-Source on-resistance R DS(ON) = f (T j ) ; s = 9,5 0,45 Typical Drain- Source ON-Resistance Channel 1, 2 Channel 3, 4 0,4 RDS(ON) [Ohm] 0,35 0,3 0,25 0,2 0, Tj[ C] Figure 6 : Typical ON Resistance versus Junction-Temperature Channel 1-4 Output Clamping oltage DS(AZ) = f (T j ) ; I D = 100mA 55 Typical Clamping oltage Channel DS (AZ) [] Tj[ C] Figure 7 : Typical Clamp oltage versus Junction-Temperature Channel

17 Package and ordering code all dimensions in mm P - DSO Ordering code TE 6228 GP Q67006-A x 1.27 = / M A x 45 A / / /-0.1 P 1 DEX MARKG / ) /

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